[LLVMbugs] [Bug 21029] New: Incorrect live-in information in ARM backend

bugzilla-daemon at llvm.org bugzilla-daemon at llvm.org
Mon Sep 22 08:44:04 PDT 2014


            Bug ID: 21029
           Summary: Incorrect live-in information in ARM backend
           Product: libraries
           Version: trunk
          Hardware: Other
                OS: other
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: moritz.roth at arm.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

Created attachment 13065
  --> http://llvm.org/bugs/attachment.cgi?id=13065&action=edit
Reproducer for the given IR

I'm seeing cases in the ARM backend where live registers aren't contained in
the live-in set of the basic block. Take the attached .ll, which I extracted
from LNT/oggenc:

$ llc -mtriple=thumbv6m-eabi -O3 oggenc.ll -print-after-all

After the Prologue/Epilogue Insertion & Frame Finalization pass, this produces
(shortened, with ToT 22/09/2014):

BB#28: derived from LLVM BB %for.cond157.for.cond209.preheader_crit_edge        
    Live Ins: %R2                                                               
    Predecessors according to CFG: BB#33                                        
        %R3<def> = tLDRi %R6, 0, pred:14, pred:%noreg; mem:LD4[FixedStack35]    
        %R5<def> = tLDRi %R6, 1, pred:14, pred:%noreg; mem:LD4[FixedStack34]    
        %R0<def>, %CPSR<def,dead> = tSUBrr %R5, %R3, pred:14, pred:%noreg       
        %R4<def> = tLDRi %R6, 5, pred:14, pred:%noreg; mem:LD4[FixedStack30]    
    Successors according to CFG: BB#29                                          

BB#29: derived from LLVM BB %for.cond209.preheader                              
    Live Ins: %R0 %R4 %R2 %R3 %R5                                               
    Predecessors according to CFG: BB#26 BB#28                                  
        %R1<def>, %CPSR<def,dead> = tADDrr %R0, %R3, pred:14, pred:%noreg       
        tCMPr %R1<kill>, %R4, pred:14, pred:%noreg, %CPSR<imp-def>              
        tBcc <BB#30>, pred:11, pred:%CPSR<kill>                                 
    Successors according to CFG: BB#30(16) BB#45(16)                            

    Live Ins: %R0 %R4 %R2                                                       
    Predecessors according to CFG: BB#29                                        
        tB <BB#35>, pred:14, pred:%noreg                                        
    Successors according to CFG: BB#35                                          

BB#30: derived from LLVM BB %if.end216.lr.ph                                    
    Live Ins: %R0 %R2 %R3 %R5                                                   
    Predecessors according to CFG: BB#29                                        
        %R1<def>, %CPSR<def,dead> = tLSLri %R5<kill>, 2, pred:14, pred:%noreg   
        tSTRi %R2<kill>, %R6, 30, pred:14, pred:%noreg; mem:ST4[FixedStack5]    
        %R2<def>, %CPSR<def,dead> = tLSLri %R0, 2, pred:14, pred:%noreg         
        %R1<def>, %CPSR<def,dead> = tSUBrr %R2, %R1<kill>, pred:14, pred:%noreg 
        tSTRi %R3, %R6, 0, pred:14, pred:%noreg; mem:ST4[FixedStack35]

%R6 is live (it contains the stack pointer) in both BB#28 and BB#30, but not in
the live-in sets of either. Since the value isn't killed or redefined anywhere,
I'd expect it to be live-in in those blocks?

I'm not aware of any miscompilations caused by this, but I'd like to use the
live-in information in an optimization pass and therefore need it to be

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