[LLVMbugs] [Bug 21015] New: Wrong disassembling for SWC2 & SWC3

bugzilla-daemon at llvm.org bugzilla-daemon at llvm.org
Sat Sep 20 19:26:25 PDT 2014


            Bug ID: 21015
           Summary: Wrong disassembling for SWC2 & SWC3
           Product: new-bugs
           Version: trunk
          Hardware: PC
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: junkoi2004 at gmail.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

There are 2 bugs with SWC2 & SWC3

(1) SWC2 seems to be wrongly handled: the disassembling disagree with
assembling on first operand ($0 vs $f0)

$ echo "swc2 \$0, 0(\$zero)"|./Release+Asserts/bin/llvm-mc -assemble -arch=mips
    swc2    $0, 0($zero)            # encoding: [0xe8,0x00,0x00,0x00]

$ echo "0xe8,0x00,0x00,0x00" | ./Release+Asserts/bin/llvm-mc -disassemble
-arch=mips -show-encoding
    swc2    $f0, 0($zero)           # encoding: [0xe8,0x00,0x00,0x00]

(2) Meanwhile, SWC3 can be assembled, but cannot be disassembled

$ echo "swc3 \$0, 0(\$zero)"|./Release+Asserts/bin/llvm-mc -assemble -arch=mips
    swc3    $0, 0($zero)            # encoding: [0xec,0x00,0x00,0x00]

$ echo "0xec,0x00,0x00,0x00" | ./Release+Asserts/bin/llvm-mc -disassemble
-arch=mips -show-encoding
<stdin>:1:1: warning: invalid instruction encoding

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