[LLVMbugs] [Bug 21008] New: X86MCInstLower.cpp:298: void SimplifyShortImmForm(llvm::MCInst&, unsigned int): Assertion `Inst.getOperand(0).isReg() && (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) && ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=21008

            Bug ID: 21008
           Summary: X86MCInstLower.cpp:298: void
                    SimplifyShortImmForm(llvm::MCInst&, unsigned int):
                    Assertion `Inst.getOperand(0).isReg() &&
                    (Inst.getOperand(ImmOp).isImm() ||
                    Inst.getOperand(ImmOp).isExpr()) &&
                    ((Inst.getNumOperands() == 3 &&
                    Inst.getOperand(1).isReg() &&
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: nlewycky at google.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

Testcase x.ii:

struct A {
  A(int);
};
struct B {
  int : 16;
  bool member : 1;
  int pointer;
};
void fn1(bool, A);
void fn2() {
  B b;
  fn1(b.member, 0);
}

Crash:

nlewycky at ducttape:~$
/usr/local/google/home/nlewycky/llvm/Debug+Asserts/bin/clang -cc1 -std=gnu++11
-emit-obj -o /dev/null -w -x c++ x.ii
clang: X86MCInstLower.cpp:298: void SimplifyShortImmForm(llvm::MCInst&,
unsigned int): Assertion `Inst.getOperand(0).isReg() &&
(Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
Inst.getNumOperands() == 2) && "Unexpected instruction!"' failed.

#4  0x00000000031cec76 in SimplifyShortImmForm (Inst=..., Opcode=179) at
X86MCInstLower.cpp:294
#5  0x00000000031d0a26 in (anonymous namespace)::X86MCInstLower::Lower
(this=0x7fffffffc000, MI=0x66e5ca8, OutMI=...) at X86MCInstLower.cpp:645

(gdb) call Inst.dump()
<MCInst 183 <MCOperand Reg:23> <MCOperand Reg:19> <MCOperand Imm:1>>

(gdb) call MF.dump()
# Machine code for function _Z3fn2v: Post SSA
Frame Objects:
  fi#0: size=8, align=8, at location [SP-8]
  fi#1: size=1, align=8, at location [SP-16]
  fi#2: size=4, align=4, at location [SP-20]

BB#0: derived from LLVM BB %entry
        %RSP<def,tied1> = SUB64ri8 %RSP<tied0>, 24, %EFLAGS<imp-def,dead>;
flags: FrameSetup
        %RDI<def> = LEA64r %RSP, 1, %noreg, 8, %noreg
        %ESI<def,tied1> = XOR32rr %ESI<undef,tied0>, %ESI<undef>,
%EFLAGS<imp-def>
        %EAX<def> = MOV32rm %RSP, 1, %noreg, 16, %noreg; mem:LD4[%0]
        %EAX<def,tied1> = SHR32ri %EAX<tied0>, 16, %EFLAGS<imp-def>
        %EAX<def,tied1> = AND32ri %EAX<tied0>, 1, %EFLAGS<imp-def>
        MOV32mr %RSP, 1, %noreg, 4, %noreg, %EAX<kill>; mem:ST4[FixedStack2]
        CALL64pcrel32 <ga:@_ZN1AC1Ei>[TF=6], <regmask>, %RSP<imp-use>,
%RDI<imp-use,kill>, %ESI<imp-use,kill>
        %EAX<def> = MOV32rm %RSP, 1, %noreg, 4, %noreg; mem:LD4[FixedStack2]
        %EDI<def,tied1> = AND32ri %EAX<kill,tied0>, 1, %EFLAGS<imp-def>
        MOV32mr %RSP, 1, %noreg, 4, %noreg, %EDI; mem:ST4[FixedStack2]
        CALL64pcrel32 <ga:@_Z3fn1b1A>[TF=6], <regmask>, %RSP<imp-use>,
%EDI<imp-use,kill>
        %RSP<def,tied1> = ADD64ri8 %RSP<tied0>, 24, %EFLAGS<imp-def,dead>
        RETQ

# End machine code for function _Z3fn2v.

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