[LLVMbugs] [Bug 21675] New: [aarch64] miscompile llvm.ctpop.i32

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=21675

            Bug ID: 21675
           Summary: [aarch64] miscompile llvm.ctpop.i32
           Product: tools
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: normal
          Priority: P
         Component: llc
          Assignee: unassignedbugs at nondot.org
          Reporter: cole945 at gmail.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

This code loads v2i32 to count 1-bits in the 1st element.
The result is wrong, because the 2nd element is also being counted.
The original case counts both elements, this is just a reduced
case in order to reproduce the bug.

Bitcode for reproducing the case
-- >8 -- >8 -- >8 -- >8 -- >8 -- >8 -- >8 -- >8 -- >8 --
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnueabihf"

declare i32 @llvm.ctpop.i32(i32) #1

define i32 @cnt2(<2 x i32> addrspace(1)* %src) {
  %1 = getelementptr inbounds <2 x i32> addrspace(1)* %src, i64 0
  %2 = load <2 x i32> addrspace(1)* %1, align 8

  %3 = extractelement <2 x i32> %2, i64 0
  %4 = tail call i32 @llvm.ctpop.i32(i32 %3) #2

  ret i32 %4
}
-- 8< -- 8< -- 8< -- 8< -- 8< -- 8< -- 8< -- 8< -- 8< --


Actual result:
        ldr     d0, [x0]
        cnt     v0.8b, v0.8b
        uaddlv  h0, v0.8b
        fmov    w0, s0
        ret


Expected result:
        ldr     d0, [x0]
        mov     s0, v0.s[0]    <--
        cnt     v0.8b, v0.8b
        uaddlv  h0, v0.8b
        fmov    w0, s0
        ret


Without the 'mov' to clear upper 32-bit,
the 2nd element is being counted.

I think this is a bug of 'LowerCTPOP'.
Insert-subreg doesn't enforces the semantic of zero-extend.
A explicit zero-extend must be used instead.
Otherwise, the COPY (insert-subreg) will be eliminated by
register-coalescing pass.

-- >8 -- >8 -- >8 -- >8 -- >8 -- >8 -- >8 -- >8 -- >8 --
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp
b/lib/Target/AArch64/AArch64ISelLowering.cpp
index 1d74f6e..69cde10 100644
--- a/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3116,18 +3116,13 @@ SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op,
SelectionDAG &DAG) const {
   SDValue Val = Op.getOperand(0);
   SDLoc DL(Op);
   EVT VT = Op.getValueType();
-  SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);

-  SDValue VecVal;
   if (VT == MVT::i32) {
-    VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
-    VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
-                                       VecVal);
-  } else {
-    VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
+    Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
   }
+  Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);

-  SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
+  SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
   SDValue UaddLV = DAG.getNode(
       ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
       DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
--
-- 8< -- 8< -- 8< -- 8< -- 8< -- 8< -- 8< -- 8< -- 8< --

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