[LLVMbugs] [Bug 20280] New: Load-Store ordering issue for top-down list latency scheduler.

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=20280

            Bug ID: 20280
           Summary: Load-Store ordering issue for top-down list latency
                    scheduler.
           Product: libraries
           Version: trunk
          Hardware: Macintosh
                OS: MacOS X
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: PowerPC
          Assignee: unassignedbugs at nondot.org
          Reporter: iains-llvm at btconnect.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

for the following IR :
; ModuleID = '/Volumes/sc3_src/test-ppc/small-struct.c'
target datalayout = "E-m:o-p:32:32-f64:32:64-n32"
target triple = "powerpc-apple-macosx10.5.0"

%struct.sm = type { i8, i8 }

; Function Attrs: nounwind ssp
define void @foo(%struct.sm* byval %s) #0 {
entry:
  %a = getelementptr inbounds %struct.sm* %s, i32 0, i32 0
  %0 = load i8* %a, align 1, !tbaa !1
  %conv2 = zext i8 %0 to i32
  %add = add nuw nsw i32 %conv2, 3
  %conv1 = trunc i32 %add to i8
  store i8 %conv1, i8* %a, align 1, !tbaa !1
  call void @bar(%struct.sm* byval %s, %struct.sm* byval %s) #2
  ret void
}

declare void @bar(%struct.sm* byval, %struct.sm* byval) #1

attributes #0 = { nounwind ssp "less-precise-fpmad"="false"
"no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"
"no-infs-fp-math"="false" "no-nans-fp-math"="false"
"stack-protector-buffer-size"="8" "unsafe-fp-math"="false"
"use-soft-float"="false" }
attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true"
"no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false"
"no-nans-fp-math"="false" "stack-protector-buffer-size"="8"
"unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { nounwind }

!llvm.ident = !{!0}

!0 = metadata !{metadata !"clang version 3.5.0 (trunk 212556)"}
!1 = metadata !{metadata !2, metadata !3, i64 0}
!2 = metadata !{metadata !"sm", metadata !3, i64 0, metadata !3, i64 1}
!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0}
!4 = metadata !{metadata !"Simple C/C++ TBAA"}

==== the following printout shows that the store of r2 gets delayed (and the
copy to the active register is lost).

# *** IR Dump After If Converter *** ( LOOKS OK ):
# Machine code for function foo: Post SSA
Frame Objects:
  fi#-2: size=4, align=4, fixed, at location [SP-4]
  fi#-1: size=2, align=2, fixed, at location [SP+26]
Function Live Ins: %R3 in %vreg0

BB#0: derived from LLVM BB %entry
    Live Ins: %R3
    %R0<def> = MFLR %LR<imp-use>
    STW %R31, -4, %R1
    STW %R0, 8, %R1
    %R1<def,tied3> = STWU %R1, -64, %R1<tied0>
    %R31<def> = OR %R1, %R1
    STH %R3<kill>, 90, %R31; mem:ST2[%s]
    %R2<def> = LBZ 90, %R31; mem:LD1[%a3](align=2)(tbaa=<badref>)
    %R2<def> = ADDI %R2<kill>, 3
    STB %R2<kill>, 90, %R31; mem:ST1[%a3](align=2)(tbaa=<badref>)
    %R3<def> = LHZ 90, %R31; mem:LD2[FixedStack-1](align=4)
    %R4<def> = OR %R3, %R3
    BL <ga:@bar>, <regmask>, %LR<imp-def>, %RM<imp-use>, %R3<imp-use>,
%R4<imp-use,kill>, %R1<imp-def>
    %R1<def> = ADDI %R1, 64
    %R0<def> = LWZ 8, %R1
    %R31<def> = LWZ -4, %R1
    MTLR %R0, %LR<imp-def>
    BLR %LR<imp-use>, %RM<imp-use>

# End machine code for function foo.

# *** IR Dump After Post RA top-down list latency scheduler *** (LOOKS like
wrong code):
# Machine code for function foo: Post SSA
Frame Objects:
  fi#-2: size=4, align=4, fixed, at location [SP-4]
  fi#-1: size=2, align=2, fixed, at location [SP+26]
Function Live Ins: %R3 in %vreg0

BB#0: derived from LLVM BB %entry
    Live Ins: %R3
    %R0<def> = MFLR %LR<imp-use>
    STW %R31, -4, %R1
    STW %R0<kill>, 8, %R1
    %R1<def,tied3> = STWU %R1, -64, %R1<tied0>
    %R31<def> = OR %R1, %R1
    STH %R3<kill>, 90, %R31; mem:ST2[%s]
    %R3<def> = LHZ 90, %R31; mem:LD2[FixedStack-1](align=4)
    %R2<def> = LBZ 90, %R31; mem:LD1[%a3](align=2)(tbaa=<badref>)
    %R2<def> = ADDI %R2<kill>, 3
    %R4<def> = OR %R3, %R3
    STB %R2<kill>, 90, %R31; mem:ST1[%a3](align=2)(tbaa=<badref>)
^^^^ note that the store is now ordered after the registers are setup for the
call to bar - so the input to bar appears incorrect.
    BL <ga:@bar>, <regmask>, %LR<imp-def>, %RM<imp-use>, %R3<imp-use,kill>,
%R4<imp-use,kill>, %R1<imp-def>
    %R1<def> = ADDI %R1, 64
    %R0<def> = LWZ 8, %R1
    %R31<def> = LWZ -4, %R1
    MTLR %R0<kill>, %LR<imp-def>
    BLR %LR<imp-use>, %RM<imp-use>

# End machine code for function foo.

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