[LLVMbugs] [Bug 20252] New: Incorrect disassembly of X86 INT opcode

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=20252

            Bug ID: 20252
           Summary: Incorrect disassembly of X86 INT opcode
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: mattia.fazzini at gmail.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

The destination operand of x86 INT n opcode specifies an interrupt vector
number from 0 to 255, encoded as an 8-bit unsigned intermediate value. The X86
disassembler of LLVM treats the 8-bit value as a sign-extend value.

I think the following code:

static void translateImmediate(MCInst &mcInst, uint64_t immediate,
                               const OperandSpecifier &operand,
                               InternalInstruction &insn,
                               const MCDisassembler *Dis) {

...

case ENCODING_IB:
      // Special case those X86 instructions that use the imm8 as a set of
      // bits, bit count, etc. and are not sign-extend.
      if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
          Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
          Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
          Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&
          Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &&
          Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri &&
          Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri &&
          Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri &&
          Opcode != X86::VINSERTPSrr)
...
}

should be changed to:

static void translateImmediate(MCInst &mcInst, uint64_t immediate,
                               const OperandSpecifier &operand,
                               InternalInstruction &insn,
                               const MCDisassembler *Dis) {

...
case ENCODING_IB:
      // Special case those X86 instructions that use the imm8 as a set of
      // bits, bit count, etc. and are not sign-extend.
      if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
          Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
          Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
          Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&
          Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &&
          Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri &&
          Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri &&
          Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri &&
          Opcode != X86::VINSERTPSrr && Opcode !=X86::INT)
...
}

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