[LLVMbugs] [Bug 17647] New: ARM backend incorrectly limits smlal and umlal instructions to amv6

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=17647

            Bug ID: 17647
           Summary: ARM backend incorrectly limits smlal and umlal
                    instructions to amv6
           Product: tools
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: llc
          Assignee: unassignedbugs at nondot.org
          Reporter: dpeixott at codeaurora.org
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

If I try to compile a simple test that uses inline asm to generate the smlal
and umlal instructions clang fails with an error like this:

  $ cat smlal.c
  void sfoo(signed a, signed b) {
    signed lo;
    signed hi;
    asm volatile ("smlal %0,%1,%2,%3" : "+&r" (lo), "+&r"(hi) : "r" (a), "r"
(b));
  }

  void ufoo(unsigned a, unsigned b) {
    unsigned lo;
    unsigned hi;
    asm volatile ("umlal %0,%1,%2,%3" : "+&r" (lo), "+&r"(hi) : "r" (a), "r"
(b));
  }

  $ clang  -O -march=armv4 smlal.c -c
  smlal.c:5:17: error: instruction requires: armv6
    asm volatile ("smlal %0,%1,%2,%3" : "+&r" (lo), "+&r"(hi) : "r" (a), "r"
(b) : "cc");
                  ^
  <inline asm>:1:2: note: instantiated into assembly here
          smlal r2,r3,r0,r1
          ^
  smlal.c:11:17: error: instruction requires: armv6
    asm volatile ("umlal %0,%1,%2,%3" : "+&r" (lo), "+&r"(hi) : "r" (a), "r"
(b) : "cc");
                  ^
  <inline asm>:1:2: note: instantiated into assembly here
          umlal r2,r3,r0,r1

If I compile with gcc or disable the integrated assembler (using
-no-integrated-as), it works fine. Looking at the definition for these
instructions in ARMInstrInfo.td I see this:

  def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
                          (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
IIC_iMAC64,
                      "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
           RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM,
HasV6]>;
  def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
                          (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
IIC_iMAC64,
                      "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
           RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM,
HasV6]>;

Both instructions are defined with Requires<[HasV6]>, but the ARM ARM
(A8.8.178) says that these instructions are available in armv4* and above
(encoding A1).

I also see these definitions in the same file:

  def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
                  (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p,
cc_out:$s),
                                4, IIC_iMAC64, [],
               (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo,
GPR:$RHi,
                             pred:$p, cc_out:$s)>,
                             Requires<[IsARM, NoV6]>;
  def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
                  (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p,
cc_out:$s),
                                4, IIC_iMAC64, [],
               (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo,
GPR:$RHi,
                             pred:$p, cc_out:$s)>,
                             Requires<[IsARM, NoV6]>;

I am not sure why these are defined separately for non-v6 targets and what they
are trying to model.

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