[LLVMbugs] [Bug 17921] New: [PATCH] armv5te thumb1 target generated UB code mov tGPR, tGPR (should => adds GPR, GPR, #0)

bugzilla-daemon at llvm.org bugzilla-daemon at llvm.org
Wed Nov 13 17:02:16 PST 2013


            Bug ID: 17921
           Summary: [PATCH] armv5te thumb1 target generated UB code mov
                    tGPR, tGPR (should => adds GPR,GPR,#0)
           Product: libraries
           Version: trunk
          Hardware: All
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: dontbugme at mailinator.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

Dear LLVM ARM backend developers,

llc generates invalid armv5te code, as per

The following patch is a sketch, still somewhat problematic - it should be
active only for armv5te thumb1, and the CPSR clobber might have some unintended
consequences (perhaps this belongs somewhere else than copyPhysReg?)

Someone more well-versed in ARM target please take a look at it.

- anonymous

Index: lib/Target/ARM/Thumb1InstrInfo.cpp
--- lib/Target/ARM/Thumb1InstrInfo.cpp    (revision 194564)
+++ lib/Target/ARM/Thumb1InstrInfo.cpp    (working copy)
@@ -40,10 +40,17 @@

 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I, DebugLoc DL,
                                   unsigned DestReg, unsigned SrcReg,
                                   bool KillSrc) const {
+  if (isARMLowRegister(SrcReg) && isARMLowRegister(DestReg)) {
+    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tADDrr),
DestReg).addReg(ARM::CPSR) // s suffix
+        .addReg(SrcReg, getKillRegState(KillSrc)).addImm(0));
+    return;
+  }
   AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
     .addReg(SrcReg, getKillRegState(KillSrc)));
   assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
          "Thumb1 can only copy GPR registers");

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