[LLVMbugs] [Bug 16038] New: qt4 webcore file results in "Bad machine code: Using an undefined physical register"
bugzilla-daemon at llvm.org
bugzilla-daemon at llvm.org
Thu May 16 13:54:56 PDT 2013
http://llvm.org/bugs/show_bug.cgi?id=16038
Bug ID: 16038
Summary: qt4 webcore file results in "Bad machine code: Using
an undefined physical register"
Product: new-bugs
Version: trunk
Hardware: PC
OS: FreeBSD
Status: NEW
Severity: normal
Priority: P
Component: new bugs
Assignee: unassignedbugs at nondot.org
Reporter: dimitry at andric.com
CC: llvmbugs at cs.uiuc.edu
Classification: Unclassified
Created attachment 10529
--> http://llvm.org/bugs/attachment.cgi?id=10529&action=edit
Testcase for qt4 webkit error in backend
A certain file from FreeBSD's qt4-webkit port causes a "Bad machine code: Using
an undefined physical register ***", when it is compiled for the i386 arch,
with clang 3.3 (branches/release_33 181625).
I have reduced the testcase to just 140 lines, and it is attached. Compile
this with:
clang -O2 -march=i486 -c qt4-webkit-testcase.cpp
which results in (warning, long dump):
======================================================================
qt4-webkit-testcase.cpp:139:3: warning: control reaches end of non-void
function [-Wreturn-type]
}
^
# Machine code for function
_ZNK7WebCore8Position10downstreamENS_27EditingBoundaryCrossingRuleE: Post SSA
Frame Objects:
fi#-3: size=4, align=4, fixed, at location [SP+12]
fi#-2: size=4, align=4, fixed, at location [SP+8]
fi#-1: size=4, align=4, fixed, at location [SP+4]
fi#0: size=12, align=8, at location [SP+4]
BB#0: derived from LLVM BB %entry
%vreg41<def> = MOV32rm <fi#-2>, 1, %noreg, 0, %noreg;
mem:LD4[FixedStack-2] GR32:%vreg41
%vreg1<def> = MOV32rm %vreg41, 1, %noreg, 0, %noreg;
mem:LD4[%m_ptr.i.i.i149](tbaa=!"any pointer") GR32:%vreg1,%vreg41
%vreg0<def> = MOV8rm %vreg41, 1, %noreg, 8, %noreg;
mem:LD1[%m_anchorType](align=4) GR8:%vreg0 GR32:%vreg41
%vreg42<def> = COPY %vreg0; GR8:%vreg42,%vreg0
%vreg42<def,tied1> = AND8ri %vreg42<tied0>, 3, %EFLAGS<imp-def,dead>;
GR8:%vreg42
CMP8ri %vreg42, 1, %EFLAGS<imp-def>; GR8:%vreg42
JNE_4 <BB#12>, %EFLAGS<imp-use,kill>
JMP_4 <BB#1>
Successors according to CFG: BB#1(16) BB#12(16)
BB#1: derived from LLVM BB %cond.true
Predecessors according to CFG: BB#0
TEST32rr %vreg1, %vreg1, %EFLAGS<imp-def>; GR32:%vreg1
JE_4 <BB#3>, %EFLAGS<imp-use,kill>
JMP_4 <BB#2>
Successors according to CFG: BB#3(4) BB#2(64)
BB#2: derived from LLVM BB %if.then.i.i.i43
Predecessors according to CFG: BB#1
INC32m %vreg1, 1, %noreg, 4, %noreg, %EFLAGS<imp-def,dead>;
mem:ST4[%m_refCount.i.i.i.i42](tbaa=!"int")
LD4[%m_refCount.i.i.i.i42](tbaa=!"int") GR32:%vreg1
Successors according to CFG: BB#3
BB#3: derived from LLVM BB
%_ZN3WTF10PassRefPtrIN7WebCore4NodeEEC1IS2_EERKNS_6RefPtrIT_EE.exit
Predecessors according to CFG: BB#1 BB#2
EH_LABEL <MCSym=.Ltmp26>
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg45<def> = COPY %ESP; GR32:%vreg45
MOV32mr %vreg45, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[Stack]
GR32:%vreg45,%vreg1
CALLpcrel32 <ga:@_ZN7WebCore14caretMaxOffsetEPKNS_4NodeE>, <regmask>,
%ESP<imp-use>, %ESP<imp-def>, %EAX<imp-def>
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg46<def> = COPY %EAX; GR32:%vreg46
EH_LABEL <MCSym=.Ltmp27>
JMP_4 <BB#5>
Successors according to CFG: BB#5(1048575) BB#4(1)
BB#4: derived from LLVM BB %lpad.body.thread142, EH LANDING PAD
Live Ins: %EAX %EDX
Predecessors according to CFG: BB#3
EH_LABEL <MCSym=.Ltmp28>
%vreg47<def> = COPY %EAX; GR32:%vreg47
%vreg3<def> = COPY %vreg47; GR32:%vreg3,%vreg47
%vreg140<def> = COPY %vreg3; GR32:%vreg140,%vreg3
JMP_4 <BB#52>
Successors according to CFG: BB#52
BB#5: derived from LLVM BB %invoke.cont5
Predecessors according to CFG: BB#3
%vreg2<def> = COPY %vreg46; GR32:%vreg2,%vreg46
EH_LABEL <MCSym=.Ltmp29>
ADJCALLSTACKDOWN32 8, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg49<def> = COPY %ESP; GR32:%vreg49
MOV32mr %vreg49, 1, %noreg, 4, %noreg, %vreg2; mem:ST4[Stack+4]
GR32:%vreg49,%vreg2
MOV32mr %vreg49, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[Stack]
GR32:%vreg49,%vreg1
CALLpcrel32
<ga:@_ZN7WebCore8Position34anchorTypeForLegacyEditingPositionEPNS_4NodeEi>,
<regmask>, %ESP<imp-use>, %ESP<imp-def>, %EAX<imp-def>
ADJCALLSTACKUP32 8, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg50<def> = COPY %EAX; GR32:%vreg50
EH_LABEL <MCSym=.Ltmp30>
JMP_4 <BB#11>
Successors according to CFG: BB#11(1048575) BB#6(1)
BB#6: derived from LLVM BB %lpad.i, EH LANDING PAD
Live Ins: %EAX %EDX
Predecessors according to CFG: BB#5
EH_LABEL <MCSym=.Ltmp31>
%vreg51<def> = COPY %EAX; GR32:%vreg51
TEST32rr %vreg1, %vreg1, %EFLAGS<imp-def>; GR32:%vreg1
JE_4 <BB#38>, %EFLAGS<imp-use,kill>
JMP_4 <BB#7>
Successors according to CFG: BB#38(1) BB#7(1)
BB#7: derived from LLVM BB %if.then.i.i.i.i62
Predecessors according to CFG: BB#6
%vreg53<def> = MOV32rm %vreg1, 1, %noreg, 4, %noreg;
mem:LD4[%m_refCount.i.i.i.i.i](tbaa=!"int") GR32_NOSP:%vreg53 GR32:%vreg1
%vreg54<def> = LEA32r %vreg53, 1, %noreg, -1, %noreg; GR32:%vreg54
GR32_NOSP:%vreg53
MOV32mr %vreg1, 1, %noreg, 4, %noreg, %vreg54;
mem:ST4[%m_refCount.i.i.i.i.i](tbaa=!"int") GR32:%vreg1,%vreg54
CMP32ri8 %vreg53, 1, %EFLAGS<imp-def>; GR32_NOSP:%vreg53
JG_4 <BB#38>, %EFLAGS<imp-use,kill>
JMP_4 <BB#8>
Successors according to CFG: BB#8(1) BB#38(1)
BB#8: derived from LLVM BB %land.lhs.true.i.i.i.i.i
Predecessors according to CFG: BB#7
CMP32mi8 %vreg1, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>;
mem:LD4[%m_parent.i.i.i.i.i](tbaa=!"any pointer") GR32:%vreg1
JNE_4 <BB#38>, %EFLAGS<imp-use,kill>
JMP_4 <BB#9>
Successors according to CFG: BB#9(1) BB#38(1)
BB#9: derived from LLVM BB %if.then.i.i.i.i.i63
Predecessors according to CFG: BB#8
%vreg56<def> = MOV32rm %vreg1, 1, %noreg, 0, %noreg;
mem:LD4[%11](tbaa=!"vtable pointer") GR32:%vreg56,%vreg1
%vreg57<def> = MOV32rm %vreg56, 1, %noreg, 0, %noreg;
mem:LD4[%vtable.i.i.i.i.i] GR32:%vreg57,%vreg56
EH_LABEL <MCSym=.Ltmp32>
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg58<def> = COPY %ESP; GR32:%vreg58
MOV32mr %vreg58, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[Stack]
GR32:%vreg58,%vreg1
CALL32r %vreg57, <regmask>, %ESP<imp-use>, %ESP<imp-def>; GR32:%vreg57
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
EH_LABEL <MCSym=.Ltmp33>
JMP_4 <BB#38>
Successors according to CFG: BB#38(1) BB#10(1)
BB#10: derived from LLVM BB %terminate.lpad.i, EH LANDING PAD
Live Ins: %EAX %EDX
Predecessors according to CFG: BB#9
EH_LABEL <MCSym=.Ltmp34>
%vreg59<def> = COPY %EAX; GR32:%vreg59
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg61<def> = COPY %ESP; GR32:%vreg61
MOV32mr %vreg61, 1, %noreg, 0, %noreg, %vreg59; mem:ST4[Stack]
GR32:%vreg61,%vreg59
CALLpcrel32 <ga:@__clang_call_terminate>, <regmask>, %ESP<imp-use>,
%ESP<imp-def>
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
BB#11: derived from LLVM BB
%_ZN7WebCore8PositionC2EN3WTF10PassRefPtrINS_4NodeEEEi.exit
Predecessors according to CFG: BB#5
%vreg5<def> = COPY %vreg50; GR32:%vreg5,%vreg50
%vreg63<def> = COPY %vreg5; GR32_ABCD:%vreg63 GR32:%vreg5
%vreg64<def> = COPY %vreg63:sub_8bit; GR8:%vreg64 GR32_ABCD:%vreg63
%vreg65<def> = COPY %vreg64; GR8:%vreg65,%vreg64
%vreg65<def,tied1> = AND8ri %vreg65<tied0>, 3, %EFLAGS<imp-def,dead>;
GR8:%vreg65
%vreg8<def> = COPY %vreg65; GR8:%vreg8,%vreg65
%vreg8<def,tied1> = OR8ri %vreg8<tied0>, 4, %EFLAGS<imp-def,dead>;
GR8:%vreg8
%vreg62<def> = MOV8ri 1; GR8:%vreg62
%vreg130<def> = COPY %vreg8; GR8:%vreg130,%vreg8
%vreg131<def> = COPY %vreg2; GR32:%vreg131,%vreg2
%vreg132<def> = COPY %vreg62; GR8:%vreg132,%vreg62
JMP_4 <BB#15>
Successors according to CFG: BB#15
BB#12: derived from LLVM BB %cond.false
Predecessors according to CFG: BB#0
TEST32rr %vreg1, %vreg1, %EFLAGS<imp-def>; GR32:%vreg1
%vreg129<def> = COPY %vreg0; GR8:%vreg129,%vreg0
JE_4 <BB#14>, %EFLAGS<imp-use,kill>
JMP_4 <BB#13>
Successors according to CFG: BB#14(4) BB#13(64)
BB#13: derived from LLVM BB %if.then.i.i.i.i.i67
Predecessors according to CFG: BB#12
INC32m %vreg1, 1, %noreg, 4, %noreg, %EFLAGS<imp-def,dead>;
mem:ST4[%m_refCount.i.i.i.i.i.i66](tbaa=!"int")
LD4[%m_refCount.i.i.i.i.i.i66](tbaa=!"int") GR32:%vreg1
%vreg9<def> = MOV8rm %vreg41, 1, %noreg, 8, %noreg;
mem:LD1[%sunkaddr151](align=4) GR8:%vreg9 GR32:%vreg41
%vreg129<def> = COPY %vreg9; GR8:%vreg129,%vreg9
Successors according to CFG: BB#14
BB#14: derived from LLVM BB %_ZN7WebCore8PositionC1ERKS0_.exit
Predecessors according to CFG: BB#12 BB#13
%vreg10<def> = COPY %vreg129; GR8:%vreg10,%vreg129
%vreg11<def> = MOV32rm %vreg41, 1, %noreg, 4, %noreg;
mem:LD4[%ref.tmp.sroa.1.4.idx] GR32:%vreg11,%vreg41
%vreg44<def> = MOV8r0 %EFLAGS<imp-def,dead>; GR8:%vreg44
%vreg130<def> = COPY %vreg10; GR8:%vreg130,%vreg10
%vreg131<def> = COPY %vreg11; GR32:%vreg131,%vreg11
%vreg132<def> = COPY %vreg44; GR8:%vreg132,%vreg44
Successors according to CFG: BB#15
BB#15: derived from LLVM BB %cond.end
Predecessors according to CFG: BB#14 BB#11
%vreg12<def> = COPY %vreg130; GR8:%vreg12,%vreg130
%vreg13<def> = COPY %vreg131; GR32:%vreg13,%vreg131
%vreg14<def> = COPY %vreg132; GR8:%vreg14,%vreg132
%vreg15<def> = COPY %vreg132; GR8:%vreg15,%vreg132
%vreg16<def> = COPY %vreg12; GR8:%vreg16,%vreg12
%vreg16<def,tied1> = AND8ri %vreg16<tied0>, 7, %EFLAGS<imp-def,dead>;
GR8:%vreg16
CMP8ri %vreg16, 1, %EFLAGS<imp-def>; GR8:%vreg16
%vreg133<def> = COPY %vreg13; GR32:%vreg133,%vreg13
JNE_4 <BB#17>, %EFLAGS<imp-use,kill>
JMP_4 <BB#16>
Successors according to CFG: BB#16(16) BB#17(16)
BB#16: derived from LLVM BB %if.end.i15.i.i
Predecessors according to CFG: BB#15
EH_LABEL <MCSym=.Ltmp35>
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg67<def> = COPY %ESP; GR32:%vreg67
MOV32mr %vreg67, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[Stack]
GR32:%vreg67,%vreg1
CALLpcrel32 <ga:@_ZN7WebCore20lastOffsetForEditingEPKNS_4NodeE>,
<regmask>, %ESP<imp-use>, %ESP<imp-def>, %EAX<imp-def>
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg68<def> = COPY %EAX; GR32:%vreg68
EH_LABEL <MCSym=.Ltmp36>
%vreg17<def> = COPY %vreg68; GR32:%vreg17,%vreg68
%vreg133<def> = COPY %vreg17; GR32:%vreg133,%vreg17
JMP_4 <BB#17>
Successors according to CFG: BB#17(1048575) BB#41(1)
BB#17: derived from LLVM BB
%_ZNK7WebCore8Position23deprecatedEditingOffsetEv.exit17.i.i
Predecessors according to CFG: BB#15 BB#16
EH_LABEL <MCSym=.Ltmp37>
%vreg18<def> = COPY %vreg133; GR32:%vreg18,%vreg133
ADJCALLSTACKDOWN32 8, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg69<def> = COPY %ESP; GR32:%vreg69
MOV32mr %vreg69, 1, %noreg, 4, %noreg, %vreg18; mem:ST4[Stack+4]
GR32:%vreg69,%vreg18
MOV32mr %vreg69, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[Stack]
GR32:%vreg69,%vreg1
CALLpcrel32 <ga:@_ZNK7WebCore4Node9childNodeEj>, <regmask>,
%ESP<imp-use>, %ESP<imp-def>, %EAX<imp-def>
ADJCALLSTACKUP32 8, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg70<def> = COPY %EAX; GR32:%vreg70
EH_LABEL <MCSym=.Ltmp38>
JMP_4 <BB#18>
Successors according to CFG: BB#18(1048575) BB#41(1)
BB#18: derived from LLVM BB %call4.i.i.noexc
Predecessors according to CFG: BB#17
%vreg19<def> = COPY %vreg70; GR32:%vreg19,%vreg70
CMP8ri %vreg16, 1, %EFLAGS<imp-def>; GR8:%vreg16
%vreg71<def> = SETNEr %EFLAGS<imp-use,kill>; GR8:%vreg71
%vreg73<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg73
TEST32rr %vreg19, %vreg19, %EFLAGS<imp-def>; GR32:%vreg19
%vreg134<def> = COPY %vreg73; GR32:%vreg134,%vreg73
JNE_4 <BB#20>, %EFLAGS<imp-use>
Successors according to CFG: BB#19 BB#20
BB#19: derived from LLVM BB %call4.i.i.noexc
Live Ins: %EFLAGS
Predecessors according to CFG: BB#18
%vreg134<def> = COPY %vreg13; GR32:%vreg134,%vreg13
Successors according to CFG: BB#20
BB#20: derived from LLVM BB %call4.i.i.noexc
Live Ins: %EFLAGS
Predecessors according to CFG: BB#18 BB#19
%vreg20<def> = COPY %vreg134; GR32:%vreg20,%vreg134
JE_4 <BB#21>, %EFLAGS<imp-use,kill>
Successors according to CFG: BB#58(16) BB#21(16)
BB#58:
Predecessors according to CFG: BB#20
%vreg135<def> = COPY %vreg20; GR32:%vreg135,%vreg20
JMP_4 <BB#23>
Successors according to CFG: BB#23
BB#21: derived from LLVM BB %call4.i.i.noexc
Predecessors according to CFG: BB#20
TEST8rr %vreg71, %vreg71, %EFLAGS<imp-def>; GR8:%vreg71
%vreg135<def> = COPY %vreg20; GR32:%vreg135,%vreg20
JNE_4 <BB#23>, %EFLAGS<imp-use,kill>
JMP_4 <BB#22>
Successors according to CFG: BB#23(16) BB#22(16)
BB#22: derived from LLVM BB %if.end.i.i.i
Predecessors according to CFG: BB#21
EH_LABEL <MCSym=.Ltmp39>
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg74<def> = COPY %ESP; GR32:%vreg74
MOV32mr %vreg74, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[Stack]
GR32:%vreg74,%vreg1
CALLpcrel32 <ga:@_ZN7WebCore20lastOffsetForEditingEPKNS_4NodeE>,
<regmask>, %ESP<imp-use>, %ESP<imp-def>, %EAX<imp-def>
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg75<def> = COPY %EAX; GR32:%vreg75
EH_LABEL <MCSym=.Ltmp40>
%vreg21<def> = COPY %vreg75; GR32:%vreg21,%vreg75
%vreg135<def> = COPY %vreg21; GR32:%vreg135,%vreg21
JMP_4 <BB#23>
Successors according to CFG: BB#23(1048575) BB#41(1)
BB#23: derived from LLVM BB %invoke.cont13
Predecessors according to CFG: BB#21 BB#22 BB#58
%vreg22<def> = COPY %vreg135; GR32:%vreg22,%vreg135
TEST32rr %vreg1, %vreg1, %EFLAGS<imp-def>; GR32:%vreg1
%vreg87<def> = SETEr %EFLAGS<imp-use,kill>; GR8:%vreg87
%vreg88<def> = COPY %vreg87; GR8:%vreg88,%vreg87
%vreg88<def,dead,tied1> = OR8rr %vreg88<tied0>, %vreg15,
%EFLAGS<imp-def>; GR8:%vreg88,%vreg15
JNE_4 <BB#27>, %EFLAGS<imp-use,kill>
JMP_4 <BB#24>
Successors according to CFG: BB#27(16) BB#24(16)
BB#24: derived from LLVM BB %if.then.i.i.i.i.i78
Predecessors according to CFG: BB#23
%vreg89<def> = MOV32rm %vreg1, 1, %noreg, 4, %noreg;
mem:LD4[%m_refCount.i.i.i.i.i.i75](tbaa=!"int") GR32_NOSP:%vreg89 GR32:%vreg1
%vreg90<def> = LEA32r %vreg89, 1, %noreg, -1, %noreg; GR32:%vreg90
GR32_NOSP:%vreg89
MOV32mr %vreg1, 1, %noreg, 4, %noreg, %vreg90;
mem:ST4[%m_refCount.i.i.i.i.i.i75](tbaa=!"int") GR32:%vreg1,%vreg90
CMP32ri8 %vreg89, 1, %EFLAGS<imp-def>; GR32_NOSP:%vreg89
JG_4 <BB#27>, %EFLAGS<imp-use,kill>
JMP_4 <BB#25>
Successors according to CFG: BB#25(16) BB#27(16)
BB#25: derived from LLVM BB %land.lhs.true.i.i.i.i.i.i81
Predecessors according to CFG: BB#24
CMP32mi8 %vreg1, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>;
mem:LD4[%m_parent.i.i.i.i.i.i79](tbaa=!"any pointer") GR32:%vreg1
JNE_4 <BB#27>, %EFLAGS<imp-use,kill>
JMP_4 <BB#26>
Successors according to CFG: BB#26(12) BB#27(20)
BB#26: derived from LLVM BB %if.then.i.i.i.i.i.i83
Predecessors according to CFG: BB#25
%vreg92<def> = MOV32rm %vreg1, 1, %noreg, 0, %noreg;
mem:LD4[%25](tbaa=!"vtable pointer") GR32:%vreg92,%vreg1
%vreg93<def> = MOV32rm %vreg92, 1, %noreg, 0, %noreg;
mem:LD4[%vtable.i.i.i.i.i.i82] GR32:%vreg93,%vreg92
EH_LABEL <MCSym=.Ltmp44>
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg94<def> = COPY %ESP; GR32:%vreg94
MOV32mr %vreg94, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[Stack]
GR32:%vreg94,%vreg1
CALL32r %vreg93, <regmask>, %ESP<imp-use>, %ESP<imp-def>; GR32:%vreg93
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
EH_LABEL <MCSym=.Ltmp45>
JMP_4 <BB#27>
Successors according to CFG: BB#27(1048575) BB#40(1)
BB#27: derived from LLVM BB %cleanup.done
Predecessors according to CFG: BB#23 BB#24 BB#25 BB#26
TEST32rr %vreg1, %vreg1, %EFLAGS<imp-def>; GR32:%vreg1
JE_4 <BB#36>, %EFLAGS<imp-use,kill>
JMP_4 <BB#28>
Successors according to CFG: BB#36(16) BB#28(16)
BB#28: derived from LLVM BB %cleanup.done
Predecessors according to CFG: BB#27
%vreg103<def> = COPY %vreg14; GR8:%vreg103,%vreg14
%vreg103<def,dead,tied1> = XOR8ri %vreg103<tied0>, 1, %EFLAGS<imp-def>;
GR8:%vreg103
JNE_4 <BB#36>, %EFLAGS<imp-use,kill>
JMP_4 <BB#29>
Successors according to CFG: BB#36(16) BB#29(16)
BB#29: derived from LLVM BB %if.then.i.i.i.i.i91
Predecessors according to CFG: BB#28
%vreg104<def> = MOV32rm %vreg1, 1, %noreg, 4, %noreg;
mem:LD4[%m_refCount.i.i.i.i.i.i88](tbaa=!"int") GR32_NOSP:%vreg104 GR32:%vreg1
%vreg23<def> = LEA32r %vreg104, 1, %noreg, -1, %noreg; GR32:%vreg23
GR32_NOSP:%vreg104
MOV32mr %vreg1, 1, %noreg, 4, %noreg, %vreg23;
mem:ST4[%m_refCount.i.i.i.i.i.i88](tbaa=!"int") GR32:%vreg1,%vreg23
CMP32ri8 %vreg104, 1, %EFLAGS<imp-def>; GR32_NOSP:%vreg104
%vreg136<def> = COPY %vreg23; GR32:%vreg136,%vreg23
JG_4 <BB#33>, %EFLAGS<imp-use,kill>
JMP_4 <BB#30>
Successors according to CFG: BB#30(16) BB#33(16)
BB#30: derived from LLVM BB %land.lhs.true.i.i.i.i.i.i94
Predecessors according to CFG: BB#29
CMP32mi8 %vreg1, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>;
mem:LD4[%m_parent.i.i.i.i.i.i92](tbaa=!"any pointer") GR32:%vreg1
JNE_4 <BB#32>, %EFLAGS<imp-use,kill>
JMP_4 <BB#31>
Successors according to CFG: BB#31(12) BB#32(20)
BB#31: derived from LLVM BB %if.then.i.i.i.i.i.i96
Predecessors according to CFG: BB#30
%vreg106<def> = MOV32rm %vreg1, 1, %noreg, 0, %noreg;
mem:LD4[%31](tbaa=!"vtable pointer") GR32:%vreg106,%vreg1
%vreg107<def> = MOV32rm %vreg106, 1, %noreg, 0, %noreg;
mem:LD4[%vtable.i.i.i.i.i.i95] GR32:%vreg107,%vreg106
EH_LABEL <MCSym=.Ltmp49>
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg108<def> = COPY %ESP; GR32:%vreg108
MOV32mr %vreg108, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[Stack]
GR32:%vreg108,%vreg1
CALL32r %vreg107, <regmask>, %ESP<imp-use>, %ESP<imp-def>;
GR32:%vreg107
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
EH_LABEL <MCSym=.Ltmp50>
JMP_4 <BB#32>
Successors according to CFG: BB#32(1048575) BB#39(1)
BB#32: derived from LLVM BB %if.then.i.i.i104thread-pre-split
Predecessors according to CFG: BB#30 BB#31
%vreg24<def> = MOV32rm %vreg1, 1, %noreg, 4, %noreg;
mem:LD4[%sunkaddr154](tbaa=!"int") GR32:%vreg24,%vreg1
%vreg136<def> = COPY %vreg24; GR32:%vreg136,%vreg24
Successors according to CFG: BB#33
BB#33: derived from LLVM BB %if.then.i.i.i104
Predecessors according to CFG: BB#29 BB#32
%vreg25<def> = COPY %vreg136; GR32_NOSP:%vreg25 GR32:%vreg136
%vreg121<def> = LEA32r %vreg25, 1, %noreg, -1, %noreg; GR32:%vreg121
GR32_NOSP:%vreg25
MOV32mr %vreg1, 1, %noreg, 4, %noreg, %vreg121;
mem:ST4[%sunkaddr157](tbaa=!"int") GR32:%vreg1,%vreg121
CMP32ri8 %vreg25, 1, %EFLAGS<imp-def>; GR32_NOSP:%vreg25
JG_4 <BB#36>, %EFLAGS<imp-use,kill>
JMP_4 <BB#34>
Successors according to CFG: BB#34(16) BB#36(16)
BB#34: derived from LLVM BB %land.lhs.true.i.i.i.i107
Predecessors according to CFG: BB#33
CMP32mi8 %vreg1, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>;
mem:LD4[%m_parent.i.i.i.i105](tbaa=!"any pointer") GR32:%vreg1
JNE_4 <BB#36>, %EFLAGS<imp-use,kill>
JMP_4 <BB#35>
Successors according to CFG: BB#35(12) BB#36(20)
BB#35: derived from LLVM BB %if.then.i.i.i.i109
Predecessors according to CFG: BB#34
%vreg123<def> = MOV32rm %vreg1, 1, %noreg, 0, %noreg;
mem:LD4[%36](tbaa=!"vtable pointer") GR32:%vreg123,%vreg1
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg124<def> = COPY %ESP; GR32:%vreg124
MOV32mr %vreg124, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[Stack]
GR32:%vreg124,%vreg1
CALL32m %vreg123, 1, %noreg, 0, %noreg, <regmask>, %ESP<imp-use>,
%ESP<imp-def>; mem:LD4[%vtable.i.i.i.i108] GR32:%vreg123
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
Successors according to CFG: BB#36
BB#36: derived from LLVM BB %cleanup.done29
Predecessors according to CFG: BB#27 BB#28 BB#33 BB#34 BB#35
MOV32mr <fi#0>, 1, %noreg, 0, %noreg, %vreg1;
mem:ST4[%lastVisible.sroa.0.0.idx158](align=8) GR32:%vreg1
MOV32mr <fi#0>, 1, %noreg, 4, %noreg, %vreg19;
mem:ST4[%lastVisible.sroa.1.4.idx123] GR32:%vreg19
MOV32mr <fi#0>, 1, %noreg, 8, %noreg, %vreg22;
mem:ST4[%lastVisible.sroa.2.8.idx124](align=8) GR32:%vreg22
%vreg125<def> = LEA32r <fi#0>, 1, %noreg, 0, %noreg; GR32:%vreg125
Successors according to CFG: BB#37
BB#37: derived from LLVM BB %for.cond
Predecessors according to CFG: BB#36 BB#37
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg126<def> = COPY %ESP; GR32:%vreg126
MOV32mr %vreg126, 1, %noreg, 0, %noreg, %vreg125; mem:ST4[Stack]
GR32:%vreg126,%vreg125
CALLpcrel32 <ga:@_ZNK7WebCore16PositionIterator5atEndEv>, <regmask>,
%ESP<imp-use>, %ESP<imp-def>, %AL<imp-def,dead>
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg128<def> = COPY %ESP; GR32:%vreg128
MOV32mr %vreg128, 1, %noreg, 0, %noreg, %vreg125; mem:ST4[Stack]
GR32:%vreg128,%vreg125
CALLpcrel32 <ga:@_ZN7WebCore16PositionIterator9incrementEv>, <regmask>,
%ESP<imp-use>, %ESP<imp-def>
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
JMP_4 <BB#37>
Successors according to CFG: BB#37
BB#38: derived from LLVM BB %lpad.body.thread
Predecessors according to CFG: BB#6 BB#7 BB#8 BB#9
%vreg6<def> = COPY %vreg51; GR32:%vreg6,%vreg51
%vreg26<def> = COPY %vreg6; GR32:%vreg26,%vreg6
%vreg140<def> = COPY %vreg26; GR32:%vreg140,%vreg26
JMP_4 <BB#52>
Successors according to CFG: BB#52
BB#39: derived from LLVM BB %lpad.body, EH LANDING PAD
Live Ins: %EAX %EDX
Predecessors according to CFG: BB#31
EH_LABEL <MCSym=.Ltmp51>
%vreg109<def> = COPY %EAX<kill>; GR32:%vreg109
%vreg28<def> = COPY %vreg109; GR32:%vreg28,%vreg109
%vreg140<def> = COPY %vreg28; GR32:%vreg140,%vreg28
JMP_4 <BB#52>
Successors according to CFG: BB#52
BB#40: derived from LLVM BB %lpad9, EH LANDING PAD
Live Ins: %EAX %EDX
Predecessors according to CFG: BB#26
EH_LABEL <MCSym=.Ltmp46>
%vreg95<def> = COPY %EAX<kill>; GR32:%vreg95
%vreg30<def> = COPY %vreg95; GR32:%vreg30,%vreg95
%vreg138<def> = COPY %vreg1; GR32:%vreg138,%vreg1
%vreg139<def> = COPY %vreg30; GR32:%vreg139,%vreg30
JMP_4 <BB#47>
Successors according to CFG: BB#47
BB#41: derived from LLVM BB %lpad12, EH LANDING PAD
Live Ins: %EAX %EDX
Predecessors according to CFG: BB#16 BB#17 BB#22
EH_LABEL <MCSym=.Ltmp41>
TEST8rr %vreg15, %vreg15, %EFLAGS<imp-def>; GR8:%vreg15
%vreg137<def> = COPY %vreg1; GR32:%vreg137,%vreg1
JNE_4 <BB#43>, %EFLAGS<imp-use,kill>
Successors according to CFG: BB#42 BB#43
BB#42: derived from LLVM BB %lpad12
Predecessors according to CFG: BB#41
%vreg76<def> = MOV32r0 %EFLAGS<imp-def,dead>; GR32:%vreg76
%vreg137<def> = COPY %vreg76; GR32:%vreg137,%vreg76
Successors according to CFG: BB#43
BB#43: derived from LLVM BB %lpad12
Predecessors according to CFG: BB#41 BB#42
%vreg34<def> = COPY %vreg137; GR32:%vreg34,%vreg137
TEST32rr %vreg1, %vreg1, %EFLAGS<imp-def>; GR32:%vreg1
%vreg77<def> = SETEr %EFLAGS<imp-use,kill>; GR8:%vreg77
%vreg78<def> = COPY %EAX; GR32:%vreg78
%vreg32<def> = COPY %vreg78; GR32:%vreg32,%vreg78
%vreg80<def> = COPY %vreg15; GR8:%vreg80,%vreg15
%vreg80<def,dead,tied1> = OR8rr %vreg80<tied0>, %vreg77,
%EFLAGS<imp-def>; GR8:%vreg80,%vreg77
JE_4 <BB#44>, %EFLAGS<imp-use,kill>
Successors according to CFG: BB#59(1) BB#44(1)
BB#59:
Predecessors according to CFG: BB#43
%vreg138<def> = COPY %vreg34; GR32:%vreg138,%vreg34
%vreg139<def> = COPY %vreg32; GR32:%vreg139,%vreg32
JMP_4 <BB#47>
Successors according to CFG: BB#47
BB#44: derived from LLVM BB %if.then.i.i.i.i.i50
Predecessors according to CFG: BB#43
%vreg81<def> = MOV32rm %vreg1, 1, %noreg, 4, %noreg;
mem:LD4[%m_refCount.i.i.i.i.i.i47](tbaa=!"int") GR32_NOSP:%vreg81 GR32:%vreg1
%vreg82<def> = LEA32r %vreg81, 1, %noreg, -1, %noreg; GR32:%vreg82
GR32_NOSP:%vreg81
MOV32mr %vreg1, 1, %noreg, 4, %noreg, %vreg82;
mem:ST4[%m_refCount.i.i.i.i.i.i47](tbaa=!"int") GR32:%vreg1,%vreg82
CMP32ri8 %vreg81, 1, %EFLAGS<imp-def>; GR32_NOSP:%vreg81
JLE_4 <BB#45>, %EFLAGS<imp-use,kill>
Successors according to CFG: BB#45(1) BB#60(1)
BB#60:
Predecessors according to CFG: BB#44
%vreg138<def> = COPY %vreg1; GR32:%vreg138,%vreg1
%vreg139<def> = COPY %vreg32; GR32:%vreg139,%vreg32
JMP_4 <BB#47>
Successors according to CFG: BB#47
BB#45: derived from LLVM BB %land.lhs.true.i.i.i.i.i.i53
Predecessors according to CFG: BB#44
CMP32mi8 %vreg1, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>;
mem:LD4[%m_parent.i.i.i.i.i.i51](tbaa=!"any pointer") GR32:%vreg1
JE_4 <BB#46>, %EFLAGS<imp-use,kill>
Successors according to CFG: BB#46(1) BB#61(1)
BB#61:
Predecessors according to CFG: BB#45
%vreg138<def> = COPY %vreg1; GR32:%vreg138,%vreg1
%vreg139<def> = COPY %vreg32; GR32:%vreg139,%vreg32
JMP_4 <BB#47>
Successors according to CFG: BB#47
BB#46: derived from LLVM BB %if.then.i.i.i.i.i.i55
Predecessors according to CFG: BB#45
%vreg84<def> = MOV32rm %vreg1, 1, %noreg, 0, %noreg;
mem:LD4[%53](tbaa=!"vtable pointer") GR32:%vreg84,%vreg1
%vreg85<def> = MOV32rm %vreg84, 1, %noreg, 0, %noreg;
mem:LD4[%vtable.i.i.i.i.i.i54] GR32:%vreg85,%vreg84
EH_LABEL <MCSym=.Ltmp42>
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg86<def> = COPY %ESP; GR32:%vreg86
MOV32mr %vreg86, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[Stack]
GR32:%vreg86,%vreg1
CALL32r %vreg85, <regmask>, %ESP<imp-use>, %ESP<imp-def>; GR32:%vreg85
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
EH_LABEL <MCSym=.Ltmp43>
%vreg138<def> = COPY %vreg1; GR32:%vreg138,%vreg1
%vreg139<def> = COPY %vreg32; GR32:%vreg139,%vreg32
JMP_4 <BB#47>
Successors according to CFG: BB#47(1) BB#57(1)
BB#47: derived from LLVM BB %ehcleanup
Predecessors according to CFG: BB#46 BB#40 BB#59 BB#60 BB#61
%vreg35<def> = COPY %vreg138; GR32:%vreg35,%vreg138
%vreg36<def> = COPY %vreg139; GR32:%vreg36,%vreg139
TEST8rr %vreg14, %vreg14, %EFLAGS<imp-def>; GR8:%vreg14
JNE_4 <BB#48>, %EFLAGS<imp-use,kill>
Successors according to CFG: BB#48(1) BB#65(1)
BB#65:
Predecessors according to CFG: BB#47
%vreg141<def> = COPY %vreg36; GR32:%vreg141,%vreg36
JMP_4 <BB#56>
Successors according to CFG: BB#56
BB#48: derived from LLVM BB %cleanup.action24
Predecessors according to CFG: BB#47
TEST32rr %vreg35, %vreg35, %EFLAGS<imp-def>; GR32:%vreg35
JNE_4 <BB#49>, %EFLAGS<imp-use,kill>
Successors according to CFG: BB#62(1) BB#49(1)
BB#62:
Predecessors according to CFG: BB#48
%vreg140<def> = COPY %vreg36; GR32:%vreg140,%vreg36
JMP_4 <BB#52>
Successors according to CFG: BB#52
BB#49: derived from LLVM BB %if.then.i.i.i.i.i
Predecessors according to CFG: BB#48
%vreg97<def> = MOV32rm %vreg35, 1, %noreg, 4, %noreg;
mem:LD4[%m_refCount.i.i.i.i.i.i](tbaa=!"int") GR32_NOSP:%vreg97 GR32:%vreg35
%vreg98<def> = LEA32r %vreg97, 1, %noreg, -1, %noreg; GR32:%vreg98
GR32_NOSP:%vreg97
MOV32mr %vreg35, 1, %noreg, 4, %noreg, %vreg98;
mem:ST4[%m_refCount.i.i.i.i.i.i](tbaa=!"int") GR32:%vreg35,%vreg98
CMP32ri8 %vreg97, 1, %EFLAGS<imp-def>; GR32_NOSP:%vreg97
JLE_4 <BB#50>, %EFLAGS<imp-use,kill>
Successors according to CFG: BB#50(1) BB#63(1)
BB#63:
Predecessors according to CFG: BB#49
%vreg140<def> = COPY %vreg36; GR32:%vreg140,%vreg36
JMP_4 <BB#52>
Successors according to CFG: BB#52
BB#50: derived from LLVM BB %land.lhs.true.i.i.i.i.i.i
Predecessors according to CFG: BB#49
CMP32mi8 %vreg35, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>;
mem:LD4[%m_parent.i.i.i.i.i.i](tbaa=!"any pointer") GR32:%vreg35
JE_4 <BB#51>, %EFLAGS<imp-use,kill>
Successors according to CFG: BB#51(1) BB#64(1)
BB#64:
Predecessors according to CFG: BB#50
%vreg140<def> = COPY %vreg36; GR32:%vreg140,%vreg36
JMP_4 <BB#52>
Successors according to CFG: BB#52
BB#51: derived from LLVM BB %if.then.i.i.i.i.i.i
Predecessors according to CFG: BB#50
%vreg100<def> = MOV32rm %vreg35, 1, %noreg, 0, %noreg;
mem:LD4[%58](tbaa=!"vtable pointer") GR32:%vreg100,%vreg35
%vreg101<def> = MOV32rm %vreg100, 1, %noreg, 0, %noreg;
mem:LD4[%vtable.i.i.i.i.i.i] GR32:%vreg101,%vreg100
EH_LABEL <MCSym=.Ltmp47>
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg102<def> = COPY %ESP; GR32:%vreg102
MOV32mr %vreg102, 1, %noreg, 0, %noreg, %vreg35; mem:ST4[Stack]
GR32:%vreg102,%vreg35
CALL32r %vreg101, <regmask>, %ESP<imp-use>, %ESP<imp-def>;
GR32:%vreg101
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
EH_LABEL <MCSym=.Ltmp48>
%vreg140<def> = COPY %vreg36; GR32:%vreg140,%vreg36
JMP_4 <BB#52>
Successors according to CFG: BB#52(1) BB#57(1)
BB#52: derived from LLVM BB %cleanup.action32
Predecessors according to CFG: BB#4 BB#38 BB#51 BB#39 BB#62 BB#63 BB#64
%vreg39<def> = COPY %vreg140; GR32:%vreg39,%vreg140
TEST32rr %vreg1, %vreg1, %EFLAGS<imp-def>; GR32:%vreg1
JNE_4 <BB#53>, %EFLAGS<imp-use,kill>
Successors according to CFG: BB#66(1) BB#53(1)
BB#66:
Predecessors according to CFG: BB#52
%vreg141<def> = COPY %vreg39; GR32:%vreg141,%vreg39
JMP_4 <BB#56>
Successors according to CFG: BB#56
BB#53: derived from LLVM BB %if.then.i.i.i
Predecessors according to CFG: BB#52
%vreg111<def> = MOV32rm %vreg1, 1, %noreg, 4, %noreg;
mem:LD4[%m_refCount.i.i.i.i](tbaa=!"int") GR32_NOSP:%vreg111 GR32:%vreg1
%vreg112<def> = LEA32r %vreg111, 1, %noreg, -1, %noreg; GR32:%vreg112
GR32_NOSP:%vreg111
MOV32mr %vreg1, 1, %noreg, 4, %noreg, %vreg112;
mem:ST4[%m_refCount.i.i.i.i](tbaa=!"int") GR32:%vreg1,%vreg112
CMP32ri8 %vreg111, 1, %EFLAGS<imp-def>; GR32_NOSP:%vreg111
JLE_4 <BB#54>, %EFLAGS<imp-use,kill>
Successors according to CFG: BB#54(1) BB#67(1)
BB#67:
Predecessors according to CFG: BB#53
%vreg141<def> = COPY %vreg39; GR32:%vreg141,%vreg39
JMP_4 <BB#56>
Successors according to CFG: BB#56
BB#54: derived from LLVM BB %land.lhs.true.i.i.i.i
Predecessors according to CFG: BB#53
CMP32mi8 %vreg1, 1, %noreg, 8, %noreg, 0, %EFLAGS<imp-def>;
mem:LD4[%m_parent.i.i.i.i](tbaa=!"any pointer") GR32:%vreg1
JE_4 <BB#55>, %EFLAGS<imp-use,kill>
Successors according to CFG: BB#55(1) BB#68(1)
BB#68:
Predecessors according to CFG: BB#54
%vreg141<def> = COPY %vreg39; GR32:%vreg141,%vreg39
JMP_4 <BB#56>
Successors according to CFG: BB#56
BB#55: derived from LLVM BB %if.then.i.i.i.i
Predecessors according to CFG: BB#54
%vreg114<def> = MOV32rm %vreg1, 1, %noreg, 0, %noreg;
mem:LD4[%64](tbaa=!"vtable pointer") GR32:%vreg114,%vreg1
%vreg115<def> = MOV32rm %vreg114, 1, %noreg, 0, %noreg;
mem:LD4[%vtable.i.i.i.i] GR32:%vreg115,%vreg114
EH_LABEL <MCSym=.Ltmp52>
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg116<def> = COPY %ESP; GR32:%vreg116
MOV32mr %vreg116, 1, %noreg, 0, %noreg, %vreg1; mem:ST4[Stack]
GR32:%vreg116,%vreg1
CALL32r %vreg115, <regmask>, %ESP<imp-use>, %ESP<imp-def>;
GR32:%vreg115
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
EH_LABEL <MCSym=.Ltmp53>
%vreg141<def> = COPY %vreg39; GR32:%vreg141,%vreg39
JMP_4 <BB#56>
Successors according to CFG: BB#56(1) BB#57(1)
BB#56: derived from LLVM BB %eh.resume
Predecessors according to CFG: BB#55 BB#65 BB#66 BB#67 BB#68
%vreg40<def> = COPY %vreg141; GR32:%vreg40,%vreg141
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg120<def> = COPY %ESP; GR32:%vreg120
MOV32mr %vreg120, 1, %noreg, 0, %noreg, %vreg40; mem:ST4[Stack]
GR32:%vreg120,%vreg40
CALLpcrel32 <ga:@_Unwind_Resume>, <regmask>, %ESP<imp-use>,
%ESP<imp-def>
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
BB#57: derived from LLVM BB %terminate.lpad, EH LANDING PAD
Live Ins: %EAX %EDX
Predecessors according to CFG: BB#46 BB#51 BB#55
EH_LABEL <MCSym=.Ltmp54>
%vreg117<def> = COPY %EAX<kill>; GR32:%vreg117
ADJCALLSTACKDOWN32 4, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
%vreg119<def> = COPY %ESP; GR32:%vreg119
MOV32mr %vreg119, 1, %noreg, 0, %noreg, %vreg117; mem:ST4[Stack]
GR32:%vreg119,%vreg117
CALLpcrel32 <ga:@__clang_call_terminate>, <regmask>, %ESP<imp-use>,
%ESP<imp-def>
ADJCALLSTACKUP32 4, 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>,
%ESP<imp-use>
# End machine code for function
_ZNK7WebCore8Position10downstreamENS_27EditingBoundaryCrossingRuleE.
*** Bad machine code: Using an undefined physical register ***
- function:
_ZNK7WebCore8Position10downstreamENS_27EditingBoundaryCrossingRuleE
- basic block: BB#43 lpad12 (0x2a9d666c)
- instruction: %vreg78<def> = COPY %EAX; GR32:%vreg78
- operand 1: %EAX
fatal error: error in backend: Found 1 machine code errors.
======================================================================
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