[LLVMbugs] [Bug 15467] X86 CodeGen: Miscompile vector kernel

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=15467

Arnold Schwaighofer <aschwaighofer at apple.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |INVALID

--- Comment #3 from Arnold Schwaighofer <aschwaighofer at apple.com> ---
Duh, I should be more careful with auto generated code :).

Thanks for taking a look!

Closing as not a bug.
(In reply to comment #1)
> I don't see it's bug but an undefined behavior. X86 has 2 different shift
> behaviors, taking 32-bit integer as examples:
> 
> * scalar shift (SAR/SHL/SRL), the shift amount will be masked 0x1F, as a
> result (x << 32) == (x << 0), (y << 33) == (y << 33)
> * vector shift (PSLL,PSRA,PSRL for immediate shift amount and
> PSLLV,PSRAV,PSRLV for varialble shift amount), the shift amount is maximized
> at 32, as a result (x << 32) == 0 and (y << 33) == 0
> 
> As C doesn't define the behavior of shift when the shift amount is beyond
> the width of the operand type, both behaviors are valid.
> 
> Back to the test reported in this bug. On AVX, there's no variable shift.
> The variable shift is emulated by multiplication. The shift amount is
> converted to (1 << ShAmt) though FP2INT trick. It follows the behavior of
> vector version of shift, i.e. if ShAmt > 31, the result will be 0.
> 
> With the following change, you could ask it to following scalar version
> behavior. But, the fundamental question is which behavior is expected in a
> vectorized code.
> 
> diff --git a/lib/Target/X86/X86ISelLowering.cpp
> b/lib/Target/X86/X86ISelLowering.cpp
> index b19f2f6..7b42424 100644
> --- a/lib/Target/X86/X86ISelLowering.cpp
> +++ b/lib/Target/X86/X86ISelLowering.cpp
> @@ -11608,6 +11608,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op,
> SelectionDAG &DAG) const {
>    if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
>      Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
>  
> +    Op = DAG.getNode(ISD::AND, dl, VT, Op, DAG.getConstant(0x0f800000U,
> VT));
>      Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U,
> VT));
>      Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
>      Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);

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