[LLVMbugs] [Bug 14187] New: Register Coalescing Pass ignores some intermediate register copy
bugzilla-daemon at llvm.org
bugzilla-daemon at llvm.org
Fri Oct 26 06:34:13 PDT 2012
http://llvm.org/bugs/show_bug.cgi?id=14187
Bug #: 14187
Summary: Register Coalescing Pass ignores some intermediate
register copy
Product: new-bugs
Version: trunk
Platform: PC
OS/Version: Linux
Status: NEW
Severity: enhancement
Priority: P
Component: new bugs
AssignedTo: unassignedbugs at nondot.org
ReportedBy: vljn at ovi.com
CC: llvmbugs at cs.uiuc.edu
Classification: Unclassified
Hi,
This is a bug report that follows this discussion on the Mailing List with Ivan
Llopard :
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-October/054865.html
In short : the following machine code block (with AMDGPU backend) :
BB#3: derived from LLVM BB %41
Predecessors according to CFG: BB#1
%vreg10<def> = COPY %vreg32; R600_Reg128:%vreg10,%vreg32
%vreg10:sel_z<def> = COPY %vreg47; R600_Reg128:%vreg10 R600_Reg32:%vreg47
%vreg10:sel_w<def> = COPY %vreg32:sel_w; R600_Reg128:%vreg10,%vreg32
%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF,
1; R600_Reg32:%vreg38
%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg49, 0, 0, 0, %vreg38<kill>, 0, 0,
0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg11,%vreg49,%vreg38
%vreg47<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg47 R600_Reg128:%vreg32
%vreg32<def> = COPY %vreg10; R600_Reg128:%vreg32,%vreg10
%vreg49<def> = COPY %vreg11<kill>; R600_Reg32:%vreg49,%vreg11
JUMP <BB#1>, pred:%noreg
Successors according to CFG: BB#1
Is reduced to :
BB#3: derived from LLVM BB %41
Predecessors according to CFG: BB#1
%vreg10<def> = COPY %vreg32; R600_Reg128:%vreg10,%vreg32
%vreg10:sel_z<def> = COPY %vreg47; R600_Reg128:%vreg10 R600_Reg32:%vreg47
%vreg10:sel_w<def,dead> = COPY %vreg32:sel_w; R600_Reg128:%vreg10,%vreg32
%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF,
1; R600_Reg32:%vreg38
%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg49, 0, 0, 0, %vreg38<kill>, 0, 0,
0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg11,%vreg49,%vreg38
%vreg47<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg47 R600_Reg128:%vreg32
%vreg49<def> = COPY %vreg11<kill>; R600_Reg32:%vreg49,%vreg11
JUMP <BB#1>, pred:%noreg
Successors according to CFG: BB#1
And the corresponding debug output for regalloc is :
Considering merging to R600_Reg128 with %vreg10 in %vreg32
RHS = %vreg10 [976r,992r:0)[992r,1040r:1)[1040r,1120r:2) 0 at 976r 1 at 992r 2
at 1040r
LHS = %vreg32 [416r,448B:1)[448B,704r:0)[880B,1104r:0)[1120r,1168B:2) 0 at
448B-phi 1 at 416r 2 at 1120r
merge %vreg10:0 at 976r into %vreg32:0 at 448B --> @448B
merge %vreg10:2 at 1040r into %vreg32:0 at 448B --> @448B
merge %vreg32:2 at 1120r into %vreg10:2 at 1040r --> @448B
conflict at %vreg10:1 at 992r
taints local %vreg32:0 at 880B to 1104r
tainted lanes used by: %vreg47<def> = COPY %vreg32:sel_z; R600_Reg32:%vreg47
R600_Reg128:%vreg32
Extending: %vreg32 result = [416r,448B:1)[448B,704r:0)[880B,1168B:0) 0 at
448B-phi 1 at 416r
Shrink: [976r,992r:0)[992r,1040r:1)[1040r,1120r:2) 0 at 976r 1 at 992r 2 at
1040r
Shrunk: [976r,992r:0)[992r,1040r:1)[1040r,1040d:2) 0 at 976r 1 at 992r 2 at
1040r
Trivial!
Apparently the Simple Register Coalescer considers "vreg32 = COPYvreg10" as a
dead copy, even if vreg32 is read in another block, and discards it.
The entry MachineFunction to the pass is :
0BBB#0: derived from LLVM BB %0
Live Ins: %T1_X %T1_Y %T1_Z %T1_W
16B%vreg17<def> = COPY %T1_W; R600_TReg32:%vreg17
32B%vreg16<def> = COPY %T1_Z; R600_TReg32:%vreg16
48B%vreg15<def> = COPY %T1_Y; R600_TReg32:%vreg15
64B%vreg14<def> = COPY %T1_X; R600_TReg32:%vreg14
80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19
R600_TReg32:%vreg14
112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21
R600_Reg32:%vreg18
144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19
160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23
R600_TReg32:%vreg15
176B%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21
192B%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2
208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23
240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26
R600_TReg32:%vreg16
256B%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24
272B%vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27
R600_Reg32:%vreg25
288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28
304B%vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27
320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3
R600_Reg32:%vreg28
336B%vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26
352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1
R600_TReg32:%vreg17
368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3
432B%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
Successors according to CFG: BB#1
448BBB#1: derived from LLVM BB %25
Predecessors according to CFG: BB#0 BB#3
464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48
496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49
512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, 0,
0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7
528B%vreg30<def> = COPY %vreg29<kill>; R600_Reg32:%vreg30,%vreg29
544B%PREDICATE_BIT<def> = PRED_X %vreg30<kill>, 152, 16; R600_Reg32:%vreg30
560BJUMP <BB#3>, pred:%PREDICATE_BIT
576BJUMP <BB#2>, pred:%noreg
Successors according to CFG: BB#2(4) BB#3(124)
592BBB#2: derived from LLVM BB %31
Predecessors according to CFG: BB#1
608B%vreg39<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg39 R600_Reg128:%vreg6
624B%T2_X<def> = COPY %vreg39<kill>; R600_Reg32:%vreg39
640B%vreg40<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg40 R600_Reg128:%vreg6
656B%T2_Y<def> = COPY %vreg40<kill>; R600_Reg32:%vreg40
672B%vreg41<def> = COPY %vreg6:sel_z; R600_Reg32:%vreg41 R600_Reg128:%vreg6
688B%T2_Z<def> = COPY %vreg41<kill>; R600_Reg32:%vreg41
704B%vreg42<def> = COPY %vreg6:sel_w<kill>; R600_Reg32:%vreg42
R600_Reg128:%vreg6
720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42
736B%vreg43<def> = COPY %vreg1:sel_x; R600_Reg32:%vreg43 R600_Reg128:%vreg1
752B%T1_X<def> = COPY %vreg43<kill>; R600_Reg32:%vreg43
768B%vreg44<def> = COPY %vreg1:sel_y; R600_Reg32:%vreg44 R600_Reg128:%vreg1
784B%T1_Y<def> = COPY %vreg44<kill>; R600_Reg32:%vreg44
800B%vreg45<def> = COPY %vreg1:sel_z; R600_Reg32:%vreg45 R600_Reg128:%vreg1
816B%T1_Z<def> = COPY %vreg45<kill>; R600_Reg32:%vreg45
832B%vreg46<def> = COPY %vreg1:sel_w<kill>; R600_Reg32:%vreg46
R600_Reg128:%vreg1
848B%T1_W<def> = COPY %vreg46<kill>; R600_Reg32:%vreg46
864BRETURN %T1_W<imp-use>, %T1_Z<imp-use>, %T1_Y<imp-use>, %T1_X<imp-use>,
%T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>,
%T2_X<imp-use,kill>
880BBB#3: derived from LLVM BB %41
Predecessors according to CFG: BB#1
896B%vreg31<def> = COPY %vreg6:sel_x; R600_Reg32:%vreg31 R600_Reg128:%vreg6
912B%vreg32:sel_x<def,read-undef> = COPY %vreg31<kill>; R600_Reg128:%vreg32
R600_Reg32:%vreg31
928B%vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6
944B%vreg35<def> = COPY %vreg32<kill>; R600_Reg128:%vreg35,%vreg32
960B%vreg35:sel_y<def> = COPY %vreg34<kill>; R600_Reg128:%vreg35
R600_Reg32:%vreg34
976B%vreg36<def> = COPY %vreg35<kill>; R600_Reg128:%vreg36,%vreg35
992B%vreg36:sel_z<def> = COPY %vreg5<kill>; R600_Reg128:%vreg36
R600_Reg32:%vreg5
1008B%vreg37<def> = COPY %vreg6:sel_w; R600_Reg32:%vreg37 R600_Reg128:%vreg6
1024B%vreg10<def> = COPY %vreg36<kill>; R600_Reg128:%vreg10,%vreg36
1040B%vreg10:sel_w<def> = COPY %vreg37<kill>; R600_Reg128:%vreg10
R600_Reg32:%vreg37
1056B%vreg9<def> = COPY %vreg6:sel_z<kill>; R600_Reg32:%vreg9
R600_Reg128:%vreg6
1072B%vreg38<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
pred:%PRED_SEL_OFF, 1; R600_Reg32:%vreg38
1088B%vreg11<def> = ADD_INT 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0,
%vreg38<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0;
R600_Reg32:%vreg11,%vreg7,%vreg38
1104B%vreg47<def> = COPY %vreg9<kill>; R600_Reg32:%vreg47,%vreg9
1120B%vreg48<def> = COPY %vreg10<kill>; R600_Reg128:%vreg48,%vreg10
1136B%vreg49<def> = COPY %vreg11<kill>; R600_Reg32:%vreg49,%vreg11
1152BJUMP <BB#1>, pred:%noreg
Successors according to CFG: BB#1
# End machine code for function main.
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