[LLVMbugs] [Bug 13375] New: Teach foldMemoryOperand to turn normal defs into earlyclobbers during spilling

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=13375

             Bug #: 13375
           Summary: Teach foldMemoryOperand to turn normal defs into
                    earlyclobbers during spilling
           Product: libraries
           Version: trunk
          Platform: All
        OS/Version: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Common Code Generator Code
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: borja.ferav at gmail.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified


The function foldMemoryOperand doesn't expect to turn normal defs into
earlyclobbers and vice versa. This happens when the instruction that loads a
frame index has an earlyclobber op.

Currently, this shows up when InlineSpiller::spillAroundUses() calls
InlineSpiller::foldMemoryOperand().

To reproduce the bug with the ARM backend using -march=thumb do the following:
add "Constraints = "@earlyclobber $Rt" in" to the tLDRspi instruction
in ARMInstrThumb.td (around line 620) and compile the following code with
llc at -O3:

target datalayout =
"e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
target triple = "armv4t-generic-generic"
define float @f3(float %days) nounwind readnone {
entry:
  %mul = fmul float %days, 0x3FEF8A6C60000000
  %add = fadd float %mul, 0x40718776A0000000
  %mul1 = fmul float %days, 0x3FEF8A09A0000000
  %add2 = fadd float %mul1, 0x4076587740000000
  %mul3 = fmul float %days, 0x3E81B35CC0000000
  %sub = fsub float 0x3FFEA235C0000000, %mul3
  %call = tail call float @dsin(float %add2) nounwind readnone
  %mul4 = fmul float %sub, %call
  %mul5 = fmul float %days, 0x3E27C04CA0000000
  %sub6 = fsub float 0x3F94790B80000000, %mul5
  %mul7 = fmul float %add2, 2.000000e+00
  %call8 = tail call float @dsin(float %mul7) nounwind readnone
  %mul9 = fmul float %sub6, %call8
  %add10 = fadd float %mul4, %mul9
  %add11 = fadd float %add, %add10
  %mul12 = fmul float %days, 0x3E13C5B640000000
  %sub13 = fsub float 0x3F911C1180000000, %mul12
  %mul14 = fmul float %add, 2.000000e+00
  %call15 = tail call float @dsin(float %mul14) nounwind readnone
  %mul16 = fmul float %call15, 0x3FF1F736C0000000
  %mul17 = fmul float %sub13, 2.000000e+00
  %mul19 = fmul float %mul17, %call
  %sub20 = fsub float %mul16, %mul19
  %mul21 = fmul float %sub13, 4.000000e+00
  %mul22 = fmul float %mul21, 0x3FF1F736C0000000
  %mul24 = fmul float %mul22, %call
  %call26 = tail call float @dcos(float %mul14) nounwind readnone
  %mul27 = fmul float %mul24, %call26
  %add28 = fadd float %sub20, %mul27
  %call29 = tail call float @dsin(float %add11) nounwind readnone
  %mul30 = fmul float %call29, 0x3FF0AB6960000000
  %call31 = tail call float @dasin(float %mul30) nounwind readnone
  %add32 = fadd float %call31, %add28
  ret float %add32
}
declare float @dsin(float) nounwind readnone
declare float @dcos(float) nounwind readnone
declare float @dasin(float) nounwind readnone



The machine verifier will output the following errors:

*** Bad machine code: No live range at def ***
- function:    f3
- basic block: entry 0x9e5d2bc (BB#0) [0B;3360B)
- instruction: 2440e    %vreg51<earlyclobber,def> = tLDRspi <fi#0>, 0,
pred:14, pred:%noreg; mem:LD4[FixedStack0] tGPR:%vreg51
- operand 0:   %vreg51<earlyclobber,def>
2440e is not live in [2440r,2976r:0)  0 at 2440r

*** Bad machine code: Early clobber def must be at an early-clobber slot ***
- function:    f3
Valno #0 is defined at 2440r in [2440r,2976r:0)  0 at 2440r2440r
LLVM ERROR: Found 2 machine code errors.

For reference, the last message of the thread in the mailing list:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-July/051761.html

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