[LLVMbugs] [Bug 13257] New: problem with using dag in class instantation

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=13257

             Bug #: 13257
           Summary: problem with using dag in class instantation
           Product: tools
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: TableGen
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: rkotler at mips.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified


The following fragment from mips16 (not yet checked into main source).

The problem is that I should be able to pass parameters:
I.OutOperandList, I.InOperandList

But instead, I must back substitute what I know the values of these are.
(outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz)


class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, InstrItinClass
itin> :                        
        FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), 
                  !strconcat(asmstr, "\t$rz, $rx, $ry"),
                   pattern, itin>;

class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>:
  FRRR16<I.f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), 
              // tablegen bug: should be I.OutOperandList, I.InOperandList,
     I.AsmString, 
     [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], I.Itinerary
> {
  let isCommutable = isComm;
  let isReMaterializable = 1;
}

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