[LLVMbugs] [Bug 11904] New: Ordered FP compare converted to unordered compares on X86

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=11904

             Bug #: 11904
           Summary: Ordered FP compare converted to unordered compares on
                    X86
           Product: new-bugs
           Version: 2.9
          Platform: PC
        OS/Version: Windows XP
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: jjones at transcella.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified


Created attachment 7982
  --> http://llvm.org/bugs/attachment.cgi?id=7982
IR source file with fcmp olt

Given the IR source file o2.ll,, llc produces o2.s.  In the input, an

 fcmp olt

is turned into an unordered compare in the output x86 code:

 ucomiss

when using "llc o2.bc".

If either argument to the fcmp olt is a QNaN, then the semantics of
the original IR aren't explicitly stated by the LVM Language Reference Manual.
I would assume that the intent is to mimic IEEE floating point.  There, a
comparison predicate that isn't equality or inequality (as is the olt here)
should signal if they receive a NaN operand of either type.  Thus, fcmp olt
should always fault if given 1 or more QNaNs as operands.

However, the ucomiss instruction, as defined in the "Intel® 64 and IA-32
Architectures Software Developer’s Manual Volume 2B:Instruction Set Reference,
N-Z" states

   The UCOMISS instruction differs from the COMISS instruction in that 
   it signals a SIMD floating-point invalid operation exception (#I) 
   only when a source operand is an SNaN.

Thus, llc produces a transformation that turns a program that always
signals when receiving QNaN into one that will not. Instead, a "comiss"
instruction should be generated.

After examination, a partial solution is to modify the code in

ISD::CondCode ISD::getSetCCInverse (lib\CodeGen\SelectionDAG\SelectionDAG.cpp

from:

 if (isInteger)
   Operation ^= 7;   // Flip L, G, E bits, but not U.
 else
   Operation ^= 15;  // Flip all of the condition bits.

to just

 Operation ^= 7;    // Flip L, G, E bits, but not U.

However, this does not appear to be sufficient, as the transformation
still occurs. The issue seems to be in:

SelectionDAGISel::MorphNode(lib\CodeGen\SelectionDAG\SelectionDAGISel.cpp)

with the line:

      SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);

where all the bits of TargetOpc are inverted.  This line is executed for more
than compares and the like, so it isn't clear what further changes are needed.

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