[LLVMbugs] [Bug 11023] New: Poor code generation for odd sized vectors

bugzilla-daemon at llvm.org bugzilla-daemon at llvm.org
Tue Sep 27 05:19:47 PDT 2011


           Summary: Poor code generation for odd sized vectors
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Common Code Generator Code
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: mle+cl at mega-nerd.com
                CC: llvmbugs at cs.uiuc.edu

I'm compiling LLVM IR code like this on x86-64:

  define linkonce ccc <16 x float> @vector_add_float(<16 x float>  %a.78, <16 x
float>  %a.79) align 8  
    %result.80 = fadd <16 x float> %a.78, %a.79
    ret <18 x float> %result.80

This works really well when the vector length (16 in the above) is an integer
multiple of the SSE vector register width (4) resulting in the following
assembler code:

    vector_add_float:                       # @vector_add_float
    # BB#0:                                 # %entry
    addps    %xmm4, %xmm0
    addps    %xmm5, %xmm1
    addps    %xmm6, %xmm2
    addps    %xmm7, %xmm3

However, when the vector length is increased to say 18, the generated code is
rather poor, or rather is code that could easily be improved by hand.

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