[LLVMbugs] [Bug 9366] New: ARM assertion failed while disassembling rsbs reg/reg form

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=9366

           Summary: ARM assertion failed while disassembling rsbs reg/reg
                    form
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: crabtw at gmail.com
                CC: llvmbugs at cs.uiuc.edu


Created an attachment (id=6256)
 --> (http://llvm.org/bugs/attachment.cgi?id=6256)
add RSBSrr

================
$ echo '0x08 0x60 0x77 0xe0' | Debug+Asserts/bin/llvm-mc -debug -arch=arm
--disassemble
Args: Debug+Asserts/bin/llvm-mc -debug -arch=arm --disassemble
Opcode=250 Name=RSBSrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6 
5  4  3  2  1  0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 0| 0: 0: 0: 0| 0: 1: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 0: 0:
0: 0| 1: 0: 0: 0|
-------------------------------------------------------------------------------------------------

        rsbs    r6, r7, r8llvm-mc:
/home/jyyou/src/llvm-trunk/lib/Target/ARM/InstPrinter/../ARMAddressingModes.h:44:
const char* llvm::ARM_AM::getShiftOpcStr(llvm::ARM_AM::ShiftOpc): Assertion `0
&& "Unknown shift opc!"' failed.
================

In this example, it should output "rsbs r6, r7, r8".

It seems that ARMInstrInfo.td lacks defition of RSBSrr.

Attached patch adds the definition.

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