[LLVMbugs] [Bug 9113] subreg regalloc miscompile

bugzilla-daemon at llvm.org bugzilla-daemon at llvm.org
Sun Feb 13 12:56:10 PST 2011


Jakob Stoklund Olesen <stoklund at 2pi.dk> changed:

           What    |Removed                     |Added
             Status|NEW                         |RESOLVED
         Resolution|                            |DUPLICATE

--- Comment #12 from Jakob Stoklund Olesen <stoklund at 2pi.dk> 2011-02-13 14:56:09 CST ---
The codegen peephole pass is breaking SSA form. Note %vreg5 is used before its

# After codegen peephole optimization pass:
# Machine code for function main:
Function Live Outs: %EAX

BB#0: derived from LLVM BB %entry
        %vreg0<def> = MOVZX32rm8 %RIP, 1, %noreg, <ga:@g_14>, %noreg;
mem:LD1[@g_14] GR32:%vreg0
        %vreg1<def> = COPY %vreg0:sub_8bit; GR8:%vreg1 GR32:%vreg0
        %vreg2<def> = MOVSX32rr8 %vreg1; GR32:%vreg2 GR8:%vreg1
        %vreg21<def> = COPY %vreg5:sub_32bit; GR32:%vreg21 GR64:%vreg5
        %vreg20<def> = COPY %vreg21:sub_8bit; GR8:%vreg20 GR32:%vreg21
        %vreg3<def> = INC8r %vreg20, %EFLAGS<imp-def,dead>; GR8:%vreg3,%vreg20
        %vreg19<def> = COPY %vreg2:sub_8bit; GR8:%vreg19 GR32:%vreg2
        %vreg4<def> = XOR8rr %vreg3, %vreg19, %EFLAGS<imp-def,dead>;
        %vreg5<def> = MOVSX64rr32 %vreg2<kill>; GR64:%vreg5 GR32:%vreg2

*** This bug has been marked as a duplicate of bug 8854 ***

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