[LLVMbugs] [Bug 8158] New: Refactor .td file to not have multiple SSE instructions that do the same thing

bugzilla-daemon at llvm.org bugzilla-daemon at llvm.org
Wed Sep 15 15:03:59 PDT 2010


           Summary: Refactor .td file to not have multiple SSE
                    instructions that do the same thing
           Product: libraries
           Version: trunk
          Platform: All
        OS/Version: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: X86
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: bruno.cardoso at gmail.com
                CC: llvmbugs at cs.uiuc.edu

The X86 backend has a bunch of instruction that are duplicated because the
instruction constraints are different. 

A full list of the ambiguous matcher instructions can be printed with:
tblgen -I ../../../include X86.td -gen-asm-matcher -debug-only ambiguous_instrs
-o /dev/null

A famous subset of them are the SSE logical instructions, which have FsXXX
ANDNPDrm, FsANDNPDrm, XORPDrm, FsXORPDrm, ... Their constraints are:

def ANDPSrm { 
  dag OutOperandList = (outs VR128:$dst);
  dag InOperandList = (ins VR128:$src1, f128mem:$src2);
  list<dag> Pattern = [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
(memopv2i64 addr:$src2)))];

def FsANDPSrm { 
  dag OutOperandList = (outs FR32:$dst);
  dag InOperandList = (ins FR32:$src1, f128mem:$src2);
  list<dag> Pattern = [(set FR32:$dst, (X86fand FR32:$src1, (memopfsf32

Some solutions proposed in previous discussions:

1) Some operations, like bit and, is not a legal op on f32, make the
legalizer extend it to v4f32 or some other canonical type for other operations
and make sure they get CSE'd right.

2) Use some pattern matching as:  
def : Pat<(f32 (and foo, bar)),
                  (EXTRACT_SUBREG (PANDrr (INSERT_SUBREG (implicit-def), foo,
(INSERT_SUBREG (implicit-def), bar, sub_ss)),

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