[LLVMbugs] [Bug 8804] New: Missing MemOperands on movss caust lost LICM opportunity

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=8804

           Summary: Missing MemOperands on movss caust lost LICM
                    opportunity
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: X86
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: stoklund at 2pi.dk
                CC: llvmbugs at cs.uiuc.edu


Created an attachment (id=5905)
 --> (http://llvm.org/bugs/attachment.cgi?id=5905)
SingleSource/UnitTests/Vector/build2

The X86 instruction selector can use movss for zextloads of vectors:

def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
          (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;

Unfortunately, this pattern causes the memory operands to be attached to the
SUBREG_TO_REG node instead of the MOVSSrm node:

ISEL: Starting pattern match on root node: 0x101058610: v4f32 =
X86ISD::VZEXT_MOVL 0x101058110 [ID=64]

  Initial Opcode index to 12237
  OpcodeSwitch from 12242 to 12247
  Match failed at index 12262
  Continuing at 12286
  Match failed at index 12288
  Continuing at 12303
  Match failed at index 12315
  Continuing at 12413
  Skipped scope entry (due to false predicate) at index 12417, continuing at
12446
  Skipped scope entry (due to false predicate) at index 12447, continuing at
12476
  Match failed at index 12415
  Continuing at 12477
  Continuing at 12673
  Match failed at index 12675
  Continuing at 12733
  OpcodeSwitch from 12737 to 12742
  TypeSwitch[f32] from 12757 to 12760
MatchAddress: X86ISelAddressMode 0x7fff5fbfdc10
Base_Reg nul Base.FrameIndex 0
 Scale1
IndexReg nul Disp 0
GV nul CP nul
ES nul JT-1 Align0
  Created node: 0x101056e10: f32,ch = MOVSSrm 0x10105d310, 0x10104fc10,
0x10104f310, 0x101056f10, 0x10104f710, 0x100f1e998

  Morphed node: 0x101058610: v4f32,ch = SUBREG_TO_REG 0x101057010, 0x101056e10,
0x101058a10, 0x101056e10:1<Mem:LD4[ConstantPool]>

ISEL: Match complete!
=> 0x101058610: v4f32,ch = SUBREG_TO_REG 0x101057010, 0x101056e10, 0x101058a10,
0x101056e10:1<Mem:LD4[ConstantPool]>

Without the memory operands, machine LICM can't hoist the constant pool load.

-- 
Configure bugmail: http://llvm.org/bugs/userprefs.cgi?tab=email
------- You are receiving this mail because: -------
You are on the CC list for the bug.