[LLVMbugs] [Bug 7787] New: ARM disassembler occasionally drops condition, shift from sbcseq, adcseq, addeq

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=7787

           Summary: ARM disassembler occasionally drops condition, shift
                    from sbcseq, adcseq, addeq
           Product: new-bugs
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: sliedes at cc.hut.fi
                CC: llvmbugs at cs.uiuc.edu


(trunk rev 110038)

Hi,

When cross-validating three different arm disassemblers (objdump, llvm-mc,
libdisarm), I ran into this:

Disassembling instruction 00d60002 with llvm-mc gives 'sbcs r0, r6, r2'.

The SBC (register) instruction is coded as follows:

cond 0000 110S nnnn dddd iiii itt0 mmmm

cond = condition
S = update flags
n = Rn
d = Rd
i = imm5
t = type
m = Rm

cond 0 is eq, therefore the instruction is sbcseq, not sbcs.

The condition eq is similarly dropped from other instructions (also in some
cases, shifts are dropped). I didn't check all these opcodes by hand, but in
these cases objdump and libdisarm agree with each other and disagree with llvm:

opcode:      00b5ffe0
decoded as:  adcs  pc, r5, r0, ror #31
should be:   adcseq  pc, r5, r0, ror #31

opcode: 0087ffc9
decoded as:  add  pc, r7, r9
should be:   addeq  pc, r7, r9, asr #31

opcode: 0087ff2a
decoded as:  add  pc, r7, r10
should be:   addeq  pc, r7, r10, lsr #30

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