[LLVMbugs] [Bug 5194] New: Optimizer deficiency in clang compared to llvm-gcc

bugzilla-daemon at cs.uiuc.edu bugzilla-daemon at cs.uiuc.edu
Wed Oct 14 23:14:54 PDT 2009


http://llvm.org/bugs/show_bug.cgi?id=5194

           Summary: Optimizer deficiency in clang compared to llvm-gcc
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P2
         Component: Scalar Optimizations
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: asl at math.spbu.ru
                CC: llvmbugs at cs.uiuc.edu, regehr at cs.utah.edu


Consider the following C code:

#include <stdint.h>

typedef struct __nesc_unnamed4254 {
  volatile unsigned
    adc12sc : 1,
            enc : 1,
            adc12tovie : 1,
            adc12ovie : 1,
            adc12on : 1,
            refon : 1,
            r2_5v : 1,
            msc : 1,
            sht0 : 4,
            sht1 : 4;
} __attribute((packed))  adc12ctl0_t;

volatile unsigned int ADC12CTL0 __asm ("0x01A0");

adc12ctl0_t getCtl0_b (void)
{
  uint16_t i = ADC12CTL0;
  return * (adc12ctl0_t *)&i;
}


llvm-gcc -O3 yields the following LLVM IR (which is perfect):

@"\010x01A0" = common global i32 0                ; <i32*> [#uses=1]

define i16 @getCtl0_b() nounwind {
entry:
  %0 = volatile load i32* @"\010x01A0", align 4   ; <i32> [#uses=1]
  %1 = trunc i32 %0 to i16                        ; <i16> [#uses=1]
  ret i16 %1
}

clang -O3 emits pretty weird code:

@"\010x01A0" = common global i32 0, align 4       ; <i32*> [#uses=1]

define i64 @getCtl0_b() nounwind {
entry:
  %tmp = volatile load i32* @"\010x01A0"          ; <i32> [#uses=2]
  %conv = trunc i32 %tmp to i16                   ; <i16> [#uses=1]
  %sroa.store.elt = lshr i16 %conv, 8             ; <i16> [#uses=1]
  %tmp7 = zext i32 %tmp to i64                    ; <i64> [#uses=1]
  %tmp9 = zext i16 %sroa.store.elt to i64         ; <i64> [#uses=1]
  %tmp10 = shl i64 %tmp9, 8                       ; <i64> [#uses=1]
  %mask11 = and i64 %tmp7, 255                    ; <i64> [#uses=1]
  %ins12 = or i64 %tmp10, %mask11                 ; <i64> [#uses=1]
  ret i64 %ins12
}

(the original testcase was MSP430, but the problem still exists even on x86)


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