[LLVMbugs] [Bug 3777] New: zext+gep should be optimized away by codegen

[bugzilla-daemon at cs.uiuc.edu]

http://llvm.org/bugs/show_bug.cgi?id=3777

           Summary: zext+gep should be optimized away by codegen
           Product: new-bugs
           Version: unspecified
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: enhancement
          Priority: P2
         Component: new bugs
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: edwintorok at gmail.com
                CC: llvmbugs at cs.uiuc.edu


I noticed that there is a zext from i8 to i64 for the GEP index, and codegen
turns that into a movzbl.

This is the LLVM IR snippet:
%8 = load i8* %7, align 1               ; <i8> [#uses=1]
%9 = zext i8 %8 to i64          ; <i64> [#uses=1]
%10 = getelementptr [256 x i32]* @hex_chars, i64 0, i64 %9              ;
<i32*> [#uses=1]
%11 = load i32* %10, align 4            ; <i32> [#uses=2]

Which gets codegened into:
        movzbl  (%rdi,%rax), %ecx
        movl    hex_chars(,%rcx,4), %ecx

I think the movzbl is not necessary, and it could simply be a movb into %cl,
since the code already assumes that %rcx's upper bits are 0.

BTW, I don't see the upper bits of rcx set in the attached assembly code.
The code works though, so I must be missing something: what guarantees that we
can use %rcx to index when we only loaded into %ecx?


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