[LLVMbugs] [Bug 3732] New: LLC instruction scheduler misbehaves on X86

[bugzilla-daemon at cs.uiuc.edu]

http://llvm.org/bugs/show_bug.cgi?id=3732

           Summary: LLC instruction scheduler misbehaves on X86
           Product: tools
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P2
         Component: llc
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: haohui.mai at gmail.com
                CC: llvmbugs at cs.uiuc.edu


Here is the test case:

; ModuleID = '<stdin>'

declare i32 @foo()

define i32 @bar(i32* %flags) {
entry:
        %flags.addr = load i32* %flags, align 4         ; <i32> [#uses=1]
        %0 = call fastcc i32 @foo() nounwind            ; <i32> [#uses=1]
        call void asm sideeffect "push $0 ; popf",
"imr,~{dirflag},~{fpsr},~{flags},~{cc},~{memory}"(i32 %flags.addr) nounwind
        %1 = icmp eq i32 %0, 0          ; <i1> [#uses=1]
        br i1 %1, label %bb1, label %bb2

bb1:            ; preds = %entry
        ret i32 1

bb2:            ; preds = %entry
        ret i32 2
}

Here is the generated assembly:

bar:
.Leh_func_begin1:
.Llabel1:
        pushl   %esi
        subl    $8, %esp
        movl    16(%esp), %eax
        movl    (%eax), %esi
        call    foo
        movl    %esi, 4(%esp)
        testl   %eax, %eax
        #APP
        push 4(%esp) ; popf
        #NO_APP
        jne     .LBB1_3 # bb2


The POPF instruction is going to change the condition code register, which
means the branch is determined by the contents of %flags rather than the icmp
instruction.

The scheduler puts the TESTL instruction after the popf instructions.


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