[LLVMbugs] [Bug 5754] New: LegalizeVectorTypes asserts on Vector SIGN_EXTEND_INREG

bugzilla-daemon at cs.uiuc.edu bugzilla-daemon at cs.uiuc.edu
Thu Dec 10 18:43:20 PST 2009


           Summary: LegalizeVectorTypes asserts on Vector SIGN_EXTEND_INREG
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: All
            Status: NEW
          Severity: major
          Priority: P2
         Component: Common Code Generator Code
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: micah.villmow at amd.com
                CC: llvmbugs at cs.uiuc.edu

Test case(couresy of Eli Friedman):
define <8 x i32> @a(<8 x i32> %a) {
  %b = trunc <8 x i32> %a to <8 x i16>
  %c = sext <8 x i16> %b to <8 x i32>
  ret <8 x i32> %c

 llvm_unreachable("Do not know how to split the result of this operator!");

Proposed Solution:
1) Disable DAG Combination for vector types // fold (sext (truncate x)) ->
(sextinreg x). in ~DAGCombiner.cpp:3024
2) Enable SplitVecRes_SIGN_EXTEND_INREG in LegalizeVectorTypes.cpp:
void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
                                         SDValue &Hi) {
  SDValue LHSLo, LHSHi;
  GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
  GetSplitDestVTs(N->getOperand(1), RHSLo, RHSHi);
  DebugLoc dl = N->getDebugLoc();

  Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
  Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,

The second solution causes expansion of sign_extend_inreg to assert because
Operand(1) is of type MVT::Other instead of the same type as Operand(0)

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