[LLVMbugs] [Bug 3105] New: TwoAddressInstructionPass fails to correctly handle instruction with multiple results and constraints

[bugzilla-daemon at cs.uiuc.edu]

http://llvm.org/bugs/show_bug.cgi?id=3105

           Summary: TwoAddressInstructionPass fails to correctly handle
                    instruction with multiple results and constraints
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: Linux
            Status: NEW
          Severity: normal
          Priority: P2
         Component: Common Code Generator Code
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: richard at xmos.com
                CC: llvmbugs at cs.uiuc.edu


Running llc -march=xcore -mcpu=xs1b-generic on the following:

define i64 @test(i32 %a, i32 %b) {
entry:
        %0 = sext i32 %a to i64
        %1 = sext i32 %b to i64
        %2 = mul i64 %0, %1
        ret i64 %2
}

results in the following assertion:

llc:
/homelocal/richard/revb2/tools_llvm/src/lib/CodeGen/LiveIntervalAnalysis.cpp:443:
void llvm::LiveIntervals::handleVirtualRegisterDef(llvm::MachineBasicBlock*,
llvm::ilist_iterator<llvm::MachineInstr>, unsigned int, llvm::MachineOperand&,
unsigned int, llvm::LiveInterval&): Assertion `interval.containsOneValue()'
failed.

It looks like the problem is introduced by TwoAddressInstructionPass. The
output of -debug-only=twoaddrinstr is as follows:

********** REWRITING TWO-ADDR INSTRS **********
********** Function: test
        %reg1027<def> = MACCS_l4r %reg1028<def>, %reg1026<kill>, %reg1026,
%reg1024<kill>, %reg1025<kill>
                prepend:        %reg1027<def> = ADD_2rus %reg1026, 0
                rewrite to:     %reg1027<def> = MACCS_l4r %reg1028<def>,
%reg1027, %reg1027, %reg1024<kill>, %reg1025<kill>
                prepend:        %reg1028<def> = ADD_2rus %reg1027, 0
                rewrite to:     %reg1028<def> = MACCS_l4r %reg1028<def>,
%reg1028, %reg1028, %reg1024<kill>, %reg1025<kill>

It produces an instruction with more than one definition of the same register.
This is clearly incorrect. I believe it is this which causes the assertion.


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