[llvm-branch-commits] [llvm-branch] r341783 - Merging r341642:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Sep 10 01:11:27 PDT 2018
Author: hans
Date: Mon Sep 10 01:11:26 2018
New Revision: 341783
URL: http://llvm.org/viewvc/llvm-project?rev=341783&view=rev
Log:
Merging r341642:
------------------------------------------------------------------------
r341642 | tnorthover | 2018-09-07 11:21:25 +0200 (Fri, 07 Sep 2018) | 8 lines
ARM: fix Thumb2 CodeGen for ldrex with folded frame-index.
Because t2LDREX (& t2STREX) were marked as AddrModeNone, but did allow a
FrameIndex operand, rewriteT2FrameIndex asserted. This gives them a
proper addressing-mode and tells the rewriter about it so that encodable
offsets are exploited and others are rejected.
Should fix PR38828.
------------------------------------------------------------------------
Added:
llvm/branches/release_70/test/CodeGen/ARM/ldrex-frame-size.ll
- copied unchanged from r341642, llvm/trunk/test/CodeGen/ARM/ldrex-frame-size.ll
Modified:
llvm/branches/release_70/ (props changed)
llvm/branches/release_70/lib/Target/ARM/ARMFrameLowering.cpp
llvm/branches/release_70/lib/Target/ARM/ARMInstrFormats.td
llvm/branches/release_70/lib/Target/ARM/ARMInstrThumb2.td
llvm/branches/release_70/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
llvm/branches/release_70/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/branches/release_70/test/CodeGen/ARM/ldstrex.ll
Propchange: llvm/branches/release_70/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Sep 10 01:11:26 2018
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338841,338902,338915,338968,339073,339091,339166,339179,339184,339190,339225,339316,339319,339411,339492,339515,339533,339535-339536,339600,339636,339674,339769,339822,339883,339895-339896,339945,340158,340303,340416-340417,340455,340641,340691,340751,340820,340839,340900,340959,341094,341244,341416,341512
+/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338841,338902,338915,338968,339073,339091,339166,339179,339184,339190,339225,339316,339319,339411,339492,339515,339533,339535-339536,339600,339636,339674,339769,339822,339883,339895-339896,339945,340158,340303,340416-340417,340455,340641,340691,340751,340820,340839,340900,340959,341094,341244,341416,341512,341642
Modified: llvm/branches/release_70/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Target/ARM/ARMFrameLowering.cpp?rev=341783&r1=341782&r2=341783&view=diff
==============================================================================
--- llvm/branches/release_70/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/branches/release_70/lib/Target/ARM/ARMFrameLowering.cpp Mon Sep 10 01:11:26 2018
@@ -1514,6 +1514,7 @@ static unsigned estimateRSStackSizeLimit
break;
case ARMII::AddrMode5:
case ARMII::AddrModeT2_i8s4:
+ case ARMII::AddrModeT2_ldrex:
Limit = std::min(Limit, ((1U << 8) - 1) * 4);
break;
case ARMII::AddrModeT2_i12:
Modified: llvm/branches/release_70/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Target/ARM/ARMInstrFormats.td?rev=341783&r1=341782&r2=341783&view=diff
==============================================================================
--- llvm/branches/release_70/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/branches/release_70/lib/Target/ARM/ARMInstrFormats.td Mon Sep 10 01:11:26 2018
@@ -109,6 +109,7 @@ def AddrModeT2_pc : AddrMode<14>;
def AddrModeT2_i8s4 : AddrMode<15>;
def AddrMode_i12 : AddrMode<16>;
def AddrMode5FP16 : AddrMode<17>;
+def AddrModeT2_ldrex : AddrMode<18>;
// Load / store index mode.
class IndexMode<bits<2> val> {
Modified: llvm/branches/release_70/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Target/ARM/ARMInstrThumb2.td?rev=341783&r1=341782&r2=341783&view=diff
==============================================================================
--- llvm/branches/release_70/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/branches/release_70/lib/Target/ARM/ARMInstrThumb2.td Mon Sep 10 01:11:26 2018
@@ -3267,7 +3267,7 @@ def t2LDREXH : T2I_ldrex<0b0101, (outs r
[(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>,
Requires<[IsThumb, HasV8MBaseline]>;
def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr),
- AddrModeNone, 4, NoItinerary,
+ AddrModeT2_ldrex, 4, NoItinerary,
"ldrex", "\t$Rt, $addr", "",
[(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]>,
Requires<[IsThumb, HasV8MBaseline]> {
@@ -3346,7 +3346,7 @@ def t2STREXH : T2I_strex<0b0101, (outs r
def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
t2addrmode_imm0_1020s4:$addr),
- AddrModeNone, 4, NoItinerary,
+ AddrModeT2_ldrex, 4, NoItinerary,
"strex", "\t$Rd, $Rt, $addr", "",
[(set rGPR:$Rd,
(strex_4 rGPR:$Rt, t2addrmode_imm0_1020s4:$addr))]>,
Modified: llvm/branches/release_70/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h?rev=341783&r1=341782&r2=341783&view=diff
==============================================================================
--- llvm/branches/release_70/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h (original)
+++ llvm/branches/release_70/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h Mon Sep 10 01:11:26 2018
@@ -201,7 +201,8 @@ namespace ARMII {
AddrModeT2_pc = 14, // +/- i12 for pc relative data
AddrModeT2_i8s4 = 15, // i8 * 4
AddrMode_i12 = 16,
- AddrMode5FP16 = 17 // i8 * 2
+ AddrMode5FP16 = 17, // i8 * 2
+ AddrModeT2_ldrex = 18, // i8 * 4, with unscaled offset in MCInst
};
inline static const char *AddrModeToString(AddrMode addrmode) {
@@ -224,6 +225,7 @@ namespace ARMII {
case AddrModeT2_pc: return "AddrModeT2_pc";
case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
case AddrMode_i12: return "AddrMode_i12";
+ case AddrModeT2_ldrex:return "AddrModeT2_ldrex";
}
}
Modified: llvm/branches/release_70/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=341783&r1=341782&r2=341783&view=diff
==============================================================================
--- llvm/branches/release_70/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/branches/release_70/lib/Target/ARM/Thumb2InstrInfo.cpp Mon Sep 10 01:11:26 2018
@@ -621,6 +621,11 @@ bool llvm::rewriteT2FrameIndex(MachineIn
// MCInst operand expects already scaled value.
Scale = 1;
assert((Offset & 3) == 0 && "Can't encode this offset!");
+ } else if (AddrMode == ARMII::AddrModeT2_ldrex) {
+ Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
+ NumBits = 8; // 8 bits scaled by 4
+ Scale = 4;
+ assert((Offset & 3) == 0 && "Can't encode this offset!");
} else {
llvm_unreachable("Unsupported addressing mode!");
}
Modified: llvm/branches/release_70/test/CodeGen/ARM/ldstrex.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/test/CodeGen/ARM/ldstrex.ll?rev=341783&r1=341782&r2=341783&view=diff
==============================================================================
--- llvm/branches/release_70/test/CodeGen/ARM/ldstrex.ll (original)
+++ llvm/branches/release_70/test/CodeGen/ARM/ldstrex.ll Mon Sep 10 01:11:26 2018
@@ -142,6 +142,91 @@ define void @excl_addrmode() {
ret void
}
+define void @test_excl_addrmode_folded() {
+; CHECK-LABEL: test_excl_addrmode_folded:
+ %local = alloca i8, i32 4096
+
+ %local.0 = getelementptr i8, i8* %local, i32 4
+ %local32.0 = bitcast i8* %local.0 to i32*
+ call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0)
+ call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0)
+; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #4]
+; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #4]
+
+ %local.1 = getelementptr i8, i8* %local, i32 1020
+ %local32.1 = bitcast i8* %local.1 to i32*
+ call i32 @llvm.arm.ldrex.p0i32(i32* %local32.1)
+ call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.1)
+; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #1020]
+; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #1020]
+
+ ret void
+}
+
+define void @test_excl_addrmode_range() {
+; CHECK-LABEL: test_excl_addrmode_range:
+ %local = alloca i8, i32 4096
+
+ %local.0 = getelementptr i8, i8* %local, i32 1024
+ %local32.0 = bitcast i8* %local.0 to i32*
+ call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0)
+ call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0)
+; CHECK-T2ADDRMODE: mov r[[TMP:[0-9]+]], sp
+; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], r[[TMP]], #1024
+; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
+; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
+
+ ret void
+}
+
+define void @test_excl_addrmode_align() {
+; CHECK-LABEL: test_excl_addrmode_align:
+ %local = alloca i8, i32 4096
+
+ %local.0 = getelementptr i8, i8* %local, i32 2
+ %local32.0 = bitcast i8* %local.0 to i32*
+ call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0)
+ call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0)
+; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp
+; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #2
+; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
+; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
+
+ ret void
+}
+
+define void @test_excl_addrmode_sign() {
+; CHECK-LABEL: test_excl_addrmode_sign:
+ %local = alloca i8, i32 4096
+
+ %local.0 = getelementptr i8, i8* %local, i32 -4
+ %local32.0 = bitcast i8* %local.0 to i32*
+ call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0)
+ call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0)
+; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp
+; CHECK-T2ADDRMODE: subs r[[ADDR:[0-9]+]], #4
+; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
+; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
+
+ ret void
+}
+
+define void @test_excl_addrmode_combination() {
+; CHECK-LABEL: test_excl_addrmode_combination:
+ %local = alloca i8, i32 4096
+ %unused = alloca i8, i32 64
+
+ %local.0 = getelementptr i8, i8* %local, i32 4
+ %local32.0 = bitcast i8* %local.0 to i32*
+ call i32 @llvm.arm.ldrex.p0i32(i32* %local32.0)
+ call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32.0)
+; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #68]
+; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #68]
+
+ ret void
+}
+
+
; LLVM should know, even across basic blocks, that ldrex is setting the high
; bits of its i32 to 0. There should be no zero-extend operation.
define zeroext i8 @test_cross_block_zext_i8(i1 %tst, i8* %addr) {
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