[llvm-branch-commits] [llvm-branch] r346739 - Merging r341919:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Mon Nov 12 21:43:07 2018
New Revision: 346739

URL: http://llvm.org/viewvc/llvm-project?rev=346739&view=rev
Log:
Merging r341919:

------------------------------------------------------------------------
r341919 | atanasyan | 2018-09-11 02:57:25 -0700 (Tue, 11 Sep 2018) | 18 lines

[mips] Add a pattern for 64-bit GPR variant of the `rdhwr` instruction

MIPS ISAs start to support third operand for the `rdhwr` instruction
starting from Revision 6. But LLVM generates assembler code with
three-operands version of this instruction on any MIPS64 ISA. The third
operand is always zero, so in case of direct code generation we get
correct code.

This patch fixes the bug by adding an instruction alias. The same alias
already exists for 32-bit ISA.

Ideally, we also need to reject three-operands version of the `rdhwr`
instruction in an assembler code if ISA revision is less than 6. That is
a task for a separate patch.

This fixes PR38861 (https://bugs.llvm.org/show_bug.cgi?id=38861)

Differential revision: https://reviews.llvm.org/D51773
------------------------------------------------------------------------

Modified:
    llvm/branches/release_70/lib/Target/Mips/Mips64InstrInfo.td
    llvm/branches/release_70/test/CodeGen/Mips/tls.ll

Modified: llvm/branches/release_70/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Target/Mips/Mips64InstrInfo.td?rev=346739&r1=346738&r2=346739&view=diff
==============================================================================
--- llvm/branches/release_70/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/branches/release_70/lib/Target/Mips/Mips64InstrInfo.td Mon Nov 12 21:43:07 2018
@@ -1139,3 +1139,6 @@ def SLTUImm64 : MipsAsmPseudoInst<(outs
                                   "sltu\t$rs, $rt, $imm">, GPR_64;
 def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
                                                   imm64:$imm)>, GPR_64;
+
+def : MipsInstAlias<"rdhwr $rt, $rs",
+                    (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, GPR_64;

Modified: llvm/branches/release_70/test/CodeGen/Mips/tls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/test/CodeGen/Mips/tls.ll?rev=346739&r1=346738&r2=346739&view=diff
==============================================================================
--- llvm/branches/release_70/test/CodeGen/Mips/tls.ll (original)
+++ llvm/branches/release_70/test/CodeGen/Mips/tls.ll Mon Nov 12 21:43:07 2018
@@ -48,14 +48,14 @@ entry:
 ; STATIC32-LABEL:   f1:
 ; STATIC32:   lui     $[[R0:[0-9]+]], %tprel_hi(t1)
 ; STATIC32:   addiu   $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
-; STATIC32:   rdhwr   $3, $29
+; STATIC32:   rdhwr   $3, $29{{$}}
 ; STATIC32:   addu    $[[R2:[0-9]+]], $3, $[[R1]]
 ; STATIC32:   lw      $2, 0($[[R2]])
 
 ; STATIC64-LABEL:   f1:
 ; STATIC64:   lui     $[[R0:[0-9]+]], %tprel_hi(t1)
 ; STATIC64:   daddiu  $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
-; STATIC64:   rdhwr   $3, $29, 0
+; STATIC64:   rdhwr   $3, $29{{$}}
 ; STATIC64:   daddu   $[[R2:[0-9]+]], $3, $[[R0]]
 ; STATIC64:   lw      $2, 0($[[R2]])
 }
@@ -101,7 +101,7 @@ entry:
 ; STATIC32-LABEL:   f2:
 ; STATIC32:   lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
 ; STATIC32:   addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
-; STATIC32:   rdhwr   $3, $29
+; STATIC32:   rdhwr   $3, $29{{$}}
 ; STATIC32:   lw      $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
 ; STATIC32:   addu    $[[R1:[0-9]+]], $3, $[[R0]]
 ; STATIC32:   lw      $2, 0($[[R1]])
@@ -109,7 +109,7 @@ entry:
 ; STATIC64-LABEL:   f2:
 ; STATIC64:   lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(f2)))
 ; STATIC64:   daddiu  $[[GP:[0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f2)))
-; STATIC64:   rdhwr   $3, $29
+; STATIC64:   rdhwr   $3, $29{{$}}
 ; STATIC64:   ld      $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
 ; STATIC64:   daddu   $[[R1:[0-9]+]], $3, $[[R0]]
 ; STATIC64:   lw      $2, 0($[[R1]])