[llvm-branch-commits] [llvm-branch] r331728 - Cherry-pick @=r330950 to google/stable for 2018-04-24

[David L. Jones via llvm-branch-commits]

Author: dlj
Date: Mon May  7 21:11:38 2018
New Revision: 331728

URL: http://llvm.org/viewvc/llvm-project?rev=331728&view=rev
Log:
Cherry-pick @=r330950 to google/stable for 2018-04-24

Modified:
    llvm/branches/google/stable/   (props changed)
    llvm/branches/google/stable/BRANCH_HISTORY
    llvm/branches/google/stable/test/CodeGen/X86/ftrunc.ll

Propchange: llvm/branches/google/stable/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon May  7 21:11:38 2018
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,330893,330947
+/llvm/trunk:155241,330893,330947,330950

Modified: llvm/branches/google/stable/BRANCH_HISTORY
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/google/stable/BRANCH_HISTORY?rev=331728&r1=331727&r2=331728&view=diff
==============================================================================
--- llvm/branches/google/stable/BRANCH_HISTORY (original)
+++ llvm/branches/google/stable/BRANCH_HISTORY Mon May  7 21:11:38 2018
@@ -1,3 +1,4 @@
 @r330764
 @=r330893
 @=r330947
+@=r330950

Modified: llvm/branches/google/stable/test/CodeGen/X86/ftrunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/google/stable/test/CodeGen/X86/ftrunc.ll?rev=331728&r1=331727&r2=331728&view=diff
==============================================================================
--- llvm/branches/google/stable/test/CodeGen/X86/ftrunc.ll (original)
+++ llvm/branches/google/stable/test/CodeGen/X86/ftrunc.ll Mon May  7 21:11:38 2018
@@ -356,3 +356,54 @@ define <4 x double> @trunc_signed_v4f64(
   ret <4 x double> %r
 }
 
+; FIXME: The attribute name is subject to change, but the fold may be
+; guarded to allow existing code to continue working based on its
+; assumptions of float->int overflow.
+
+define float @trunc_unsigned_f32_disable_via_attr(float %x) #1 {
+; SSE2-LABEL: trunc_unsigned_f32_disable_via_attr:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    cvttss2si %xmm0, %rax
+; SSE2-NEXT:    movl %eax, %eax
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2ssq %rax, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE41-LABEL: trunc_unsigned_f32_disable_via_attr:
+; SSE41:       # %bb.0:
+; SSE41-NEXT:    roundss $11, %xmm0, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: trunc_unsigned_f32_disable_via_attr:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vroundss $11, %xmm0, %xmm0, %xmm0
+; AVX1-NEXT:    retq
+  %i = fptoui float %x to i32
+  %r = uitofp i32 %i to float
+  ret float %r
+}
+
+define double @trunc_signed_f64_disable_via_attr(double %x) #1 {
+; SSE2-LABEL: trunc_signed_f64_disable_via_attr:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    cvttsd2si %xmm0, %rax
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2sdq %rax, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE41-LABEL: trunc_signed_f64_disable_via_attr:
+; SSE41:       # %bb.0:
+; SSE41-NEXT:    roundsd $11, %xmm0, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: trunc_signed_f64_disable_via_attr:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vroundsd $11, %xmm0, %xmm0, %xmm0
+; AVX1-NEXT:    retq
+  %i = fptosi double %x to i64
+  %r = sitofp i64 %i to double
+  ret double %r
+}
+
+attributes #1 = { nounwind "fp-cast-overflow-workaround"="true" }
+