[llvm-branch-commits] [llvm-branch] r322671 - Merging r321791 and r321862:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Jan 17 07:54:25 PST 2018
Author: hans
Date: Wed Jan 17 07:54:25 2018
New Revision: 322671
URL: http://llvm.org/viewvc/llvm-project?rev=322671&view=rev
Log:
Merging r321791 and r321862:
------------------------------------------------------------------------
r321791 | sam_parker | 2018-01-04 01:42:27 -0800 (Thu, 04 Jan 2018) | 4 lines
[X86] Codegen test for PR37563
Adding test to ease review of D41628.
------------------------------------------------------------------------
------------------------------------------------------------------------
r321862 | sam_parker | 2018-01-05 00:47:23 -0800 (Fri, 05 Jan 2018) | 10 lines
[DAGCombine] Fix for PR37563
While searching for loads to be narrowed, equal sized loads were not
added to the list, resulting in anyext loads not being converted to
zext loads.
https://bugs.llvm.org/show_bug.cgi?id=35763
Differential Revision: https://reviews.llvm.org/D41628
------------------------------------------------------------------------
Added:
llvm/branches/release_60/test/CodeGen/X86/pr37563.ll
- copied, changed from r321791, llvm/trunk/test/CodeGen/X86/pr37563.ll
Modified:
llvm/branches/release_60/ (props changed)
llvm/branches/release_60/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/branches/release_60/test/CodeGen/ARM/and-load-combine.ll
Propchange: llvm/branches/release_60/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jan 17 07:54:25 2018
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321789,321980,321991,321993,322056,322103,322623
+/llvm/trunk:155241,321789,321791,321862,321980,321991,321993,322056,322103,322623
Modified: llvm/branches/release_60/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=322671&r1=322670&r2=322671&view=diff
==============================================================================
--- llvm/branches/release_60/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/branches/release_60/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jan 17 07:54:25 2018
@@ -3842,9 +3842,16 @@ bool DAGCombiner::SearchForAndLoads(SDNo
EVT ExtVT;
if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) &&
isLegalNarrowLoad(Load, ISD::ZEXTLOAD, ExtVT)) {
- // Only add this load if we can make it more narrow.
- if (ExtVT.bitsLT(Load->getMemoryVT()))
+
+ // ZEXTLOAD is already small enough.
+ if (Load->getExtensionType() == ISD::ZEXTLOAD &&
+ ExtVT.bitsGE(Load->getMemoryVT()))
+ continue;
+
+ // Use LE to convert equal sized loads to zext.
+ if (ExtVT.bitsLE(Load->getMemoryVT()))
Loads.insert(Load);
+
continue;
}
return false;
@@ -3899,11 +3906,13 @@ bool DAGCombiner::BackwardsPropagateMask
if (Loads.size() == 0)
return false;
+ DEBUG(dbgs() << "Backwards propagate AND: "; N->dump());
SDValue MaskOp = N->getOperand(1);
// If it exists, fixup the single node we allow in the tree that needs
// masking.
if (FixupNode) {
+ DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump());
SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode),
FixupNode->getValueType(0),
SDValue(FixupNode, 0), MaskOp);
@@ -3928,6 +3937,7 @@ bool DAGCombiner::BackwardsPropagateMask
// Create narrow loads.
for (auto *Load : Loads) {
+ DEBUG(dbgs() << "Propagate AND back to: "; Load->dump());
SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0),
SDValue(Load, 0), MaskOp);
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And);
Modified: llvm/branches/release_60/test/CodeGen/ARM/and-load-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/ARM/and-load-combine.ll?rev=322671&r1=322670&r2=322671&view=diff
==============================================================================
--- llvm/branches/release_60/test/CodeGen/ARM/and-load-combine.ll (original)
+++ llvm/branches/release_60/test/CodeGen/ARM/and-load-combine.ll Wed Jan 17 07:54:25 2018
@@ -852,8 +852,7 @@ define arm_aapcscc i1 @test6(i8* %x, i8
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r0, [r0]
; ARM-NEXT: uxtb r2, r2
-; ARM-NEXT: and r0, r0, r1
-; ARM-NEXT: uxtb r1, r0
+; ARM-NEXT: and r1, r0, r1
; ARM-NEXT: mov r0, #0
; ARM-NEXT: cmp r1, r2
; ARM-NEXT: movweq r0, #1
@@ -863,8 +862,7 @@ define arm_aapcscc i1 @test6(i8* %x, i8
; ARMEB: @ %bb.0: @ %entry
; ARMEB-NEXT: ldrb r0, [r0]
; ARMEB-NEXT: uxtb r2, r2
-; ARMEB-NEXT: and r0, r0, r1
-; ARMEB-NEXT: uxtb r1, r0
+; ARMEB-NEXT: and r1, r0, r1
; ARMEB-NEXT: mov r0, #0
; ARMEB-NEXT: cmp r1, r2
; ARMEB-NEXT: movweq r0, #1
@@ -872,9 +870,8 @@ define arm_aapcscc i1 @test6(i8* %x, i8
;
; THUMB1-LABEL: test6:
; THUMB1: @ %bb.0: @ %entry
-; THUMB1-NEXT: ldrb r0, [r0]
-; THUMB1-NEXT: ands r0, r1
-; THUMB1-NEXT: uxtb r3, r0
+; THUMB1-NEXT: ldrb r3, [r0]
+; THUMB1-NEXT: ands r3, r1
; THUMB1-NEXT: uxtb r2, r2
; THUMB1-NEXT: movs r0, #1
; THUMB1-NEXT: movs r1, #0
@@ -889,8 +886,7 @@ define arm_aapcscc i1 @test6(i8* %x, i8
; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrb r0, [r0]
; THUMB2-NEXT: uxtb r2, r2
-; THUMB2-NEXT: ands r0, r1
-; THUMB2-NEXT: uxtb r1, r0
+; THUMB2-NEXT: ands r1, r0
; THUMB2-NEXT: movs r0, #0
; THUMB2-NEXT: cmp r1, r2
; THUMB2-NEXT: it eq
Copied: llvm/branches/release_60/test/CodeGen/X86/pr37563.ll (from r321791, llvm/trunk/test/CodeGen/X86/pr37563.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/X86/pr37563.ll?p2=llvm/branches/release_60/test/CodeGen/X86/pr37563.ll&p1=llvm/trunk/test/CodeGen/X86/pr37563.ll&r1=321791&r2=322671&rev=322671&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr37563.ll (original)
+++ llvm/branches/release_60/test/CodeGen/X86/pr37563.ll Wed Jan 17 07:54:25 2018
@@ -10,9 +10,10 @@
define void @PR35763() {
; CHECK-LABEL: PR35763:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movzwl z+{{.*}}(%rip), %eax
-; CHECK-NEXT: orl {{.*}}(%rip), %eax
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
+; CHECK-NEXT: movzwl {{.*}}(%rip), %eax
+; CHECK-NEXT: movzwl z+{{.*}}(%rip), %ecx
+; CHECK-NEXT: orl %eax, %ecx
+; CHECK-NEXT: movq %rcx, {{.*}}(%rip)
; CHECK-NEXT: movl z+{{.*}}(%rip), %eax
; CHECK-NEXT: movzbl z+{{.*}}(%rip), %ecx
; CHECK-NEXT: shlq $32, %rcx
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