[llvm-branch-commits] [llvm-branch] r339664 - Merging r339600:

[Hans Wennborg via llvm-branch-commits]

Author: hans
Date: Tue Aug 14 02:30:11 2018
New Revision: 339664

URL: http://llvm.org/viewvc/llvm-project?rev=339664&view=rev
Log:
Merging r339600:
------------------------------------------------------------------------
r339600 | scott.linder | 2018-08-13 20:44:21 +0200 (Mon, 13 Aug 2018) | 8 lines

[CodeGen] Fix assert in SelectionDAG::computeKnownBits

Fix SelectionDAG::computeKnownBits asserting when handling EXTRACT_SUBVECTOR
when zero extending the demanded elements mask if it is already as long as the
source vector.

Differential Revision: https://reviews.llvm.org/D49574

------------------------------------------------------------------------

Added:
    llvm/branches/release_70/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
      - copied unchanged from r339600, llvm/trunk/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll
Modified:
    llvm/branches/release_70/   (props changed)
    llvm/branches/release_70/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Propchange: llvm/branches/release_70/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Aug 14 02:30:11 2018
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338902,338915,338968,339073,339179,339184,339190,339225,339316,339319,339411,339492
+/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338902,338915,338968,339073,339179,339184,339190,339225,339316,339319,339411,339492,339600

Modified: llvm/branches/release_70/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=339664&r1=339663&r2=339664&view=diff
==============================================================================
--- llvm/branches/release_70/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/branches/release_70/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Aug 14 02:30:11 2018
@@ -2374,7 +2374,7 @@ void SelectionDAG::computeKnownBits(SDVa
     if (SubIdx && SubIdx->getAPIntValue().ule(NumSrcElts - NumElts)) {
       // Offset the demanded elts by the subvector index.
       uint64_t Idx = SubIdx->getZExtValue();
-      APInt DemandedSrc = DemandedElts.zext(NumSrcElts).shl(Idx);
+      APInt DemandedSrc = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);
       computeKnownBits(Src, Known, DemandedSrc, Depth + 1);
     } else {
       computeKnownBits(Src, Known, Depth + 1);
@@ -3533,7 +3533,7 @@ unsigned SelectionDAG::ComputeNumSignBit
     if (SubIdx && SubIdx->getAPIntValue().ule(NumSrcElts - NumElts)) {
       // Offset the demanded elts by the subvector index.
       uint64_t Idx = SubIdx->getZExtValue();
-      APInt DemandedSrc = DemandedElts.zext(NumSrcElts).shl(Idx);
+      APInt DemandedSrc = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx);
       return ComputeNumSignBits(Src, DemandedSrc, Depth + 1);
     }
     return ComputeNumSignBits(Src, Depth + 1);