[llvm-branch-commits] [llvm-branch] r319181 - Merging r319130:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Tue Nov 28 08:35:04 2017
New Revision: 319181

URL: http://llvm.org/viewvc/llvm-project?rev=319181&view=rev
Log:
Merging r319130:

------------------------------------------------------------------------
r319130 | matze | 2017-11-27 17:17:52 -0800 (Mon, 27 Nov 2017) | 7 lines

ARM: Fix PR32578

https://llvm.org/PR32578

I simplified and converted the reproducer into a lit test.

Patch by Vedant Kumar!
------------------------------------------------------------------------

Added:
    llvm/branches/release_50/test/CodeGen/ARM/pr32578.ll
Modified:
    llvm/branches/release_50/lib/Target/ARM/ARMFrameLowering.cpp

Modified: llvm/branches/release_50/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/lib/Target/ARM/ARMFrameLowering.cpp?rev=319181&r1=319180&r2=319181&view=diff
==============================================================================
--- llvm/branches/release_50/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/branches/release_50/lib/Target/ARM/ARMFrameLowering.cpp Tue Nov 28 08:35:04 2017
@@ -479,7 +479,7 @@ void ARMFrameLowering::emitPrologue(Mach
   if (DPRCSSize > 0) {
     // Since vpush register list cannot have gaps, there may be multiple vpush
     // instructions in the prologue.
-    while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
+    while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
       DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(*MBBI));
       LastPush = MBBI++;
     }

Added: llvm/branches/release_50/test/CodeGen/ARM/pr32578.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_50/test/CodeGen/ARM/pr32578.ll?rev=319181&view=auto
==============================================================================
--- llvm/branches/release_50/test/CodeGen/ARM/pr32578.ll (added)
+++ llvm/branches/release_50/test/CodeGen/ARM/pr32578.ll Tue Nov 28 08:35:04 2017
@@ -0,0 +1,27 @@
+; RUN: llc -o - %s | FileCheck %s
+target triple = "armv7"
+
+; CHECK-LABEL: func:
+; CHECK: push {r11, lr}
+; CHECK: vpush {d8}
+; CEHCK: b .LBB0_2
+define arm_aapcscc double @func() {
+  br label %tailrecurse
+
+tailrecurse:
+  %v0 = load i16, i16* undef, align 8
+  %cond36.i = icmp eq i16 %v0, 3
+  br i1 %cond36.i, label %sw.bb.i, label %sw.epilog.i
+
+sw.bb.i:
+  %v1 = load double, double* undef, align 8
+  %call21.i = tail call arm_aapcscc double @func()
+  %mul.i = fmul double %v1, %call21.i
+  ret double %mul.i
+
+sw.epilog.i:
+  tail call arm_aapcscc void @_ZNK10shared_ptrdeEv()
+  br label %tailrecurse
+}
+
+declare arm_aapcscc void @_ZNK10shared_ptrdeEv() local_unnamed_addr