[llvm-branch-commits] [llvm-branch] r281634 - [3.9.1] Merging r281319 [ARM] Support ldr.w in pseudo instruction ldr rd, =immediate

[Renato Golin via llvm-branch-commits]

Author: rengolin
Date: Thu Sep 15 13:10:44 2016
New Revision: 281634

URL: http://llvm.org/viewvc/llvm-project?rev=281634&view=rev
Log:
[3.9.1] Merging r281319 [ARM] Support ldr.w in pseudo instruction ldr rd,=immediate

Added:
    llvm/branches/release_39/test/MC/ARM/ldr-pseudo-wide.s
Modified:
    llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td
    llvm/branches/release_39/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td?rev=281634&r1=281633&r2=281634&view=diff
==============================================================================
--- llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/branches/release_39/lib/Target/ARM/ARMInstrThumb2.td Thu Sep 15 13:10:44 2016
@@ -4819,6 +4819,10 @@ def : t2InstAlias<"add${p} $Rd, pc, $imm
 def t2LDRConstPool
   : t2AsmPseudo<"ldr${p} $Rt, $immediate",
                 (ins GPRnopc:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;
+// Version w/ the .w suffix.
+def : t2InstAlias<"ldr${p}.w $Rt, $immediate",
+                  (t2LDRConstPool GPRnopc:$Rt,
+                  const_pool_asm_imm:$immediate, pred:$p)>;
 
 // PLD/PLDW/PLI with alternate literal form.
 def : t2InstAlias<"pld${p} $addr",

Modified: llvm/branches/release_39/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=281634&r1=281633&r2=281634&view=diff
==============================================================================
--- llvm/branches/release_39/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/branches/release_39/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Sep 15 13:10:44 2016
@@ -6933,6 +6933,9 @@ bool ARMAsmParser::processInstruction(MC
     else if (Inst.getOpcode() == ARM::t2LDRConstPool)
       TmpInst.setOpcode(ARM::t2LDRpci);
     const ARMOperand &PoolOperand =
+      (static_cast<ARMOperand &>(*Operands[2]).isToken() &&
+       static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w") ?
+      static_cast<ARMOperand &>(*Operands[4]) :
       static_cast<ARMOperand &>(*Operands[3]);
     const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm();
     // If SubExprVal is a constant we may be able to use a MOV

Added: llvm/branches/release_39/test/MC/ARM/ldr-pseudo-wide.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/test/MC/ARM/ldr-pseudo-wide.s?rev=281634&view=auto
==============================================================================
--- llvm/branches/release_39/test/MC/ARM/ldr-pseudo-wide.s (added)
+++ llvm/branches/release_39/test/MC/ARM/ldr-pseudo-wide.s Thu Sep 15 13:10:44 2016
@@ -0,0 +1,71 @@
+@ Test case for PR30352
+@ Check that ldr.w is:
+@ accepted and ignored for ARM
+@ accepted and propagated for Thumb2
+@ rejected as needing Thumb2 for Thumb
+
+ at RUN: llvm-mc -triple armv5-unknown-linux-gnueabi %s | FileCheck --check-prefix=CHECK-ARM --check-prefix=CHECK %s
+ at RUN: llvm-mc -triple   armv7-base-apple-darwin %s | FileCheck --check-prefix=CHECK-DARWIN-ARM --check-prefix=CHECK-DARWIN %s
+ at RUN: llvm-mc -triple thumbv7-unknown-linux-gnueabi %s | FileCheck --check-prefix=CHECK-THUMB2 --check-prefix=CHECK %s
+ at RUN: llvm-mc -triple thumbv7-base-apple-darwin %s | FileCheck --check-prefix=CHECK-DARWIN-THUMB2 --check-prefix=CHECK-DARWIN %s
+ at RUN: not llvm-mc -triple thumbv6-unknown-linux-gnueabi %s 2>&1 | FileCheck --check-prefix=CHECK-THUMB %s
+ at RUN: not llvm-mc -triple thumbv6-base-apple-darwin %s 2>&1 | FileCheck --check-prefix=CHECK-THUMB %s
+@ CHECK-LABEL: f1:
+f1:
+  ldr r0, =0x10002
+@ CHECK-ARM: ldr r0, .Ltmp[[TMP0:[0-9]+]]
+@ CHECK-DARWIN-ARM: ldr r0, Ltmp0
+@ CHECK-THUMB2: ldr r0, .Ltmp[[TMP0:[0-9]+]]
+@ CHECK-DARWIN-THUMB2: ldr r0, Ltmp0
+
+  ldr.w r0, =0x10002
+@ CHECK-ARM: ldr r0, .Ltmp[[TMP1:[0-9]+]]
+@ CHECK-DARWIN-ARM: ldr r0, Ltmp1
+@ CHECK-THUMB2: ldr.w r0, .Ltmp[[TMP1:[0-9]+]]
+@ CHECK-DARWIN-THUMB2: ldr.w r0, Ltmp1
+@ CHECK-THUMB: error: instruction requires: thumb2
+@ CHECK-THUMB-NEXT:  ldr.w r0, =0x10002
+
+@ CHECK-LABEL: f2:
+f2:
+  ldr r0, =foo
+@ CHECK-ARM: ldr r0, .Ltmp[[TMP2:[0-9]+]]
+@ CHECK-DARWIN-ARM: ldr r0, Ltmp2
+@ CHECK-THUMB2: ldr r0, .Ltmp[[TMP2:[0-9]+]]
+@ CHECK-DARWIN-THUMB2: ldr r0, Ltmp2
+
+  ldr.w r0, =foo
+@ CHECK-ARM: ldr r0, .Ltmp[[TMP3:[0-9]+]]
+@ CHECK-DARWIN-ARM: ldr r0, Ltmp3
+@ CHECK-THUMB2: ldr.w r0, .Ltmp[[TMP3:[0-9]+]]
+@ CHECK-DARWIN-THUMB2: ldr.w r0, Ltmp3
+@ CHECK-THUMB: error: instruction requires: thumb2
+@ CHECK-THUMB-NEXT:  ldr.w r0, =foo
+
+@ CHECK-LABEL: f3:
+f3:
+  ldr.w r1, =0x1
+@ CHECK-ARM: mov r1, #1
+@ CHECK-DARWIN-ARM: mov r1, #1
+@ CHECK-THUMB2: mov.w r1, #1
+@ CHECK-DARWIN-THUMB2: mov.w r1, #1
+@ CHECK-THUMB: error: instruction requires: thumb2
+@ CHECK-THUMB-NEXT:  ldr.w r1, =0x1
+
+@ CHECK: .Ltmp0:
+@ CHECK-NEXT: .long   65538
+@ CHECK: .Ltmp1:
+@ CHECK-NEXT: .long   65538
+@ CHECK: .Ltmp2:
+@ CHECK-NEXT: .long   foo
+@ CHECK: .Ltmp3:
+@ CHECK-NEXT: .long   foo
+
+@ CHECK-DARWIN: Ltmp0:
+@ CHECK-DARWIN-NEXT: .long   65538
+@ CHECK-DARWIN: Ltmp1:
+@ CHECK-DARWIN-NEXT: .long   65538
+@ CHECK-DARWIN: Ltmp2:
+@ CHECK-DARWIN-NEXT: .long   foo
+@ CHECK-DARWIN: Ltmp3:
+@ CHECK-DARWIN-NEXT: .long   foo