[llvm-branch-commits] [llvm-branch] r271770 - Merging r268287:

[Tom Stellard via llvm-branch-commits]

Author: tstellar
Date: Fri Jun  3 22:43:06 2016
New Revision: 271770

URL: http://llvm.org/viewvc/llvm-project?rev=271770&view=rev
Log:
Merging r268287:

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r268287 | thomas.stellard | 2016-05-02 12:37:56 -0700 (Mon, 02 May 2016) | 19 lines

AMDGPU/SI: Set the kill flag on temp VGPRs used to restore SGPRs from scratch

Summary:
When we restore an SGPR value from scratch, we first load it into a
temporary VGPR and then use v_readlane_b32 to copy the value from the
VGPR back into an SGPR.

We weren't setting the kill flag on the VGPR in the v_readlane_b32
instruction, so the register scavenger wasn't able to re-use this
temp value later.

I wasn't able to create a lit test for this.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D19744

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Modified:
    llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp

Modified: llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=271770&r1=271769&r2=271770&view=diff
==============================================================================
--- llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/branches/release_38/lib/Target/AMDGPU/SIRegisterInfo.cpp Fri Jun  3 22:43:06 2016
@@ -411,7 +411,7 @@ void SIRegisterInfo::eliminateFrameIndex
                   .addMemOperand(MMO);
           BuildMI(*MBB, MI, DL,
                   TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), SubReg)
-                  .addReg(TmpReg)
+                  .addReg(TmpReg, RegState::Kill)
                   .addImm(0)
                   .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
         }