[llvm-branch-commits] [llvm-branch] r258351 - Merging r257940:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Jan 20 13:30:58 PST 2016
Author: hans
Date: Wed Jan 20 15:30:57 2016
New Revision: 258351
URL: http://llvm.org/viewvc/llvm-project?rev=258351&view=rev
Log:
Merging r257940:
------------------------------------------------------------------------
r257940 | djg | 2016-01-15 13:56:40 -0800 (Fri, 15 Jan 2016) | 10 lines
[SelectionDAG] CSE nodes with differing SDNodeFlags
In the optimizer (GVN etc.) when eliminating redundant nodes with different
flags, the flags are ignored for the purposes of testing for congruence, and
then intersected for the purposes of producing a result that supports the union
of all the uses. This commit makes SelectionDAG's CSE do the same thing,
allowing it to CSE nodes in more cases. This fixes PR26063.
Differential Revision: http://reviews.llvm.org/D15957
------------------------------------------------------------------------
Merging r257942:
------------------------------------------------------------------------
r257942 | djg | 2016-01-15 14:07:35 -0800 (Fri, 15 Jan 2016) | 2 lines
Remove a now-empty file left behind by r257940.
------------------------------------------------------------------------
Added:
llvm/branches/release_38/test/CodeGen/ARM/cse-flags.ll
- copied unchanged from r257940, llvm/trunk/test/CodeGen/ARM/cse-flags.ll
Removed:
llvm/branches/release_38/test/CodeGen/X86/2014-05-30-CombineAddNSW.ll
Modified:
llvm/branches/release_38/ (props changed)
llvm/branches/release_38/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/branches/release_38/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Propchange: llvm/branches/release_38/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jan 20 15:30:57 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257902,257905,257925,257929-257930,257977,257979,257997,258168,258207,258221,258273
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258207,258221,258273
Modified: llvm/branches/release_38/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/include/llvm/CodeGen/SelectionDAGNodes.h?rev=258351&r1=258350&r2=258351&view=diff
==============================================================================
--- llvm/branches/release_38/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/branches/release_38/include/llvm/CodeGen/SelectionDAGNodes.h Wed Jan 20 15:30:57 2016
@@ -369,6 +369,18 @@ public:
(UnsafeAlgebra << 3) | (NoNaNs << 4) | (NoInfs << 5) |
(NoSignedZeros << 6) | (AllowReciprocal << 7);
}
+
+ /// Clear any flags in this flag set that aren't also set in Flags.
+ void intersectWith(const SDNodeFlags *Flags) {
+ NoUnsignedWrap &= Flags->NoUnsignedWrap;
+ NoSignedWrap &= Flags->NoSignedWrap;
+ Exact &= Flags->Exact;
+ UnsafeAlgebra &= Flags->UnsafeAlgebra;
+ NoNaNs &= Flags->NoNaNs;
+ NoInfs &= Flags->NoInfs;
+ NoSignedZeros &= Flags->NoSignedZeros;
+ AllowReciprocal &= Flags->AllowReciprocal;
+ }
};
/// Represents one node in the SelectionDAG.
@@ -682,6 +694,9 @@ public:
/// and directly, but it is not to avoid creating a vtable for this class.
const SDNodeFlags *getFlags() const;
+ /// Clear any flags in this node that aren't also set in Flags.
+ void intersectFlagsWith(const SDNodeFlags *Flags);
+
/// Return the number of values defined/returned by this operator.
unsigned getNumValues() const { return NumValues; }
Modified: llvm/branches/release_38/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=258351&r1=258350&r2=258351&view=diff
==============================================================================
--- llvm/branches/release_38/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/branches/release_38/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jan 20 15:30:57 2016
@@ -377,22 +377,6 @@ static void AddNodeIDOperands(FoldingSet
}
}
-/// Add logical or fast math flag values to FoldingSetNodeID value.
-static void AddNodeIDFlags(FoldingSetNodeID &ID, unsigned Opcode,
- const SDNodeFlags *Flags) {
- if (!isBinOpWithFlags(Opcode))
- return;
-
- unsigned RawFlags = 0;
- if (Flags)
- RawFlags = Flags->getRawFlags();
- ID.AddInteger(RawFlags);
-}
-
-static void AddNodeIDFlags(FoldingSetNodeID &ID, const SDNode *N) {
- AddNodeIDFlags(ID, N->getOpcode(), N->getFlags());
-}
-
static void AddNodeIDNode(FoldingSetNodeID &ID, unsigned short OpC,
SDVTList VTList, ArrayRef<SDValue> OpList) {
AddNodeIDOpcode(ID, OpC);
@@ -528,8 +512,6 @@ static void AddNodeIDCustom(FoldingSetNo
}
} // end switch (N->getOpcode())
- AddNodeIDFlags(ID, N);
-
// Target specific memory nodes could also have address spaces to check.
if (N->isTargetMemoryOpcode())
ID.AddInteger(cast<MemSDNode>(N)->getPointerInfo().getAddrSpace());
@@ -851,6 +833,9 @@ SDNode *SelectionDAG::FindModifiedNodeSl
AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
AddNodeIDCustom(ID, N);
SDNode *Node = FindNodeOrInsertPos(ID, N->getDebugLoc(), InsertPos);
+ if (Node)
+ if (const SDNodeFlags *Flags = N->getFlags())
+ Node->intersectFlagsWith(Flags);
return Node;
}
@@ -869,6 +854,9 @@ SDNode *SelectionDAG::FindModifiedNodeSl
AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
AddNodeIDCustom(ID, N);
SDNode *Node = FindNodeOrInsertPos(ID, N->getDebugLoc(), InsertPos);
+ if (Node)
+ if (const SDNodeFlags *Flags = N->getFlags())
+ Node->intersectFlagsWith(Flags);
return Node;
}
@@ -886,6 +874,9 @@ SDNode *SelectionDAG::FindModifiedNodeSl
AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
AddNodeIDCustom(ID, N);
SDNode *Node = FindNodeOrInsertPos(ID, N->getDebugLoc(), InsertPos);
+ if (Node)
+ if (const SDNodeFlags *Flags = N->getFlags())
+ Node->intersectFlagsWith(Flags);
return Node;
}
@@ -3892,10 +3883,12 @@ SDValue SelectionDAG::getNode(unsigned O
SDValue Ops[] = {N1, N2};
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops);
- AddNodeIDFlags(ID, Opcode, Flags);
void *IP = nullptr;
- if (SDNode *E = FindNodeOrInsertPos(ID, DL.getDebugLoc(), IP))
+ if (SDNode *E = FindNodeOrInsertPos(ID, DL.getDebugLoc(), IP)) {
+ if (Flags)
+ E->intersectFlagsWith(Flags);
return SDValue(E, 0);
+ }
N = GetBinarySDNode(Opcode, DL, VTs, N1, N2, Flags);
@@ -6249,10 +6242,12 @@ SDNode *SelectionDAG::getNodeIfExists(un
if (VTList.VTs[VTList.NumVTs - 1] != MVT::Glue) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops);
- AddNodeIDFlags(ID, Opcode, Flags);
void *IP = nullptr;
- if (SDNode *E = FindNodeOrInsertPos(ID, DebugLoc(), IP))
+ if (SDNode *E = FindNodeOrInsertPos(ID, DebugLoc(), IP)) {
+ if (Flags)
+ E->intersectFlagsWith(Flags);
return E;
+ }
}
return nullptr;
}
@@ -6948,6 +6943,11 @@ const SDNodeFlags *SDNode::getFlags() co
return nullptr;
}
+void SDNode::intersectFlagsWith(const SDNodeFlags *Flags) {
+ if (auto *FlagsNode = dyn_cast<BinaryWithFlagsSDNode>(this))
+ FlagsNode->Flags.intersectWith(Flags);
+}
+
SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) {
assert(N->getNumValues() == 1 &&
"Can't unroll a vector with multiple results!");
Removed: llvm/branches/release_38/test/CodeGen/X86/2014-05-30-CombineAddNSW.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/X86/2014-05-30-CombineAddNSW.ll?rev=258350&view=auto
==============================================================================
--- llvm/branches/release_38/test/CodeGen/X86/2014-05-30-CombineAddNSW.ll (original)
+++ llvm/branches/release_38/test/CodeGen/X86/2014-05-30-CombineAddNSW.ll (removed)
@@ -1,20 +0,0 @@
-; RUN: llc < %s -march=x86-64 | FileCheck %s
-; CHECK: addl
-
-; The two additions are the same , but have different flags.
-; In theory this code should never be generated by the frontend, but this
-; tries to test that two identical instructions with two different flags
-; actually generate two different nodes.
-;
-; Normally the combiner would see this condition without the flags
-; and optimize the result of the sub into a register clear
-; (the final result would be 0). With the different flags though the combiner
-; needs to keep the add + sub nodes, because the two nodes result as different
-; nodes and so cannot assume that the subtraction of the two nodes
-; generates 0 as result
-define i32 @foo(i32 %a, i32 %b) {
- %1 = add i32 %a, %b
- %2 = add nsw i32 %a, %b
- %3 = sub i32 %1, %2
- ret i32 %3
-}
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