[llvm-branch-commits] [llvm-branch] r259699 - Merging r259649:
Hans Wennborg via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Feb 3 13:24:31 PST 2016
Author: hans
Date: Wed Feb 3 15:24:31 2016
New Revision: 259699
URL: http://llvm.org/viewvc/llvm-project?rev=259699&view=rev
Log:
Merging r259649:
------------------------------------------------------------------------
r259649 | jamesm | 2016-02-03 07:05:06 -0800 (Wed, 03 Feb 2016) | 11 lines
[DemandedBits] Revert r249687 due to PR26071
This regresses a test in LoopVectorize, so I'll need to go away and think about how to solve this in a way that isn't broken.
>From the writeup in PR26071:
What's happening is that ComputeKnownZeroes is telling us that all bits except the LSB are zero. We're then deciding that only the LSB needs to be demanded from the icmp's inputs.
This is where we're wrong - we're assuming that after simplification the bits that were known zero will continue to be known zero. But they're not - during trivialization the upper bits get changed (because an XOR isn't shrunk), so the icmp fails.
The fault is in demandedbits - its contract does clearly state that a non-demanded bit may either be zero or one.
------------------------------------------------------------------------
Modified:
llvm/branches/release_38/ (props changed)
llvm/branches/release_38/lib/Analysis/DemandedBits.cpp
llvm/branches/release_38/test/Analysis/DemandedBits/basic.ll
llvm/branches/release_38/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll
Propchange: llvm/branches/release_38/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Feb 3 15:24:31 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258690,258729,258891,258971,259228,259236,259342,259346,259375,259645
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258690,258729,258891,258971,259228,259236,259342,259346,259375,259645,259649
Modified: llvm/branches/release_38/lib/Analysis/DemandedBits.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Analysis/DemandedBits.cpp?rev=259699&r1=259698&r2=259699&view=diff
==============================================================================
--- llvm/branches/release_38/lib/Analysis/DemandedBits.cpp (original)
+++ llvm/branches/release_38/lib/Analysis/DemandedBits.cpp Wed Feb 3 15:24:31 2016
@@ -242,13 +242,6 @@ void DemandedBits::determineLiveOperandB
if (OperandNo != 0)
AB = AOut;
break;
- case Instruction::ICmp:
- // Count the number of leading zeroes in each operand.
- ComputeKnownBits(BitWidth, UserI->getOperand(0), UserI->getOperand(1));
- auto NumLeadingZeroes = std::min(KnownZero.countLeadingOnes(),
- KnownZero2.countLeadingOnes());
- AB = ~APInt::getHighBitsSet(BitWidth, NumLeadingZeroes);
- break;
}
}
Modified: llvm/branches/release_38/test/Analysis/DemandedBits/basic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Analysis/DemandedBits/basic.ll?rev=259699&r1=259698&r2=259699&view=diff
==============================================================================
--- llvm/branches/release_38/test/Analysis/DemandedBits/basic.ll (original)
+++ llvm/branches/release_38/test/Analysis/DemandedBits/basic.ll Wed Feb 3 15:24:31 2016
@@ -10,34 +10,3 @@ define i8 @test_mul(i32 %a, i32 %b) {
%3 = trunc i32 %2 to i8
ret i8 %3
}
-
-; CHECK-LABEL: 'test_icmp1'
-; CHECK-DAG: DemandedBits: 0x1 for %3 = icmp eq i32 %1, %2
-; CHECK-DAG: DemandedBits: 0xFFF for %1 = and i32 %a, 255
-; CHECK-DAG: DemandedBits: 0xFFF for %2 = shl i32 %1, 4
-define i1 @test_icmp1(i32 %a, i32 %b) {
- %1 = and i32 %a, 255
- %2 = shl i32 %1, 4
- %3 = icmp eq i32 %1, %2
- ret i1 %3
-}
-
-; CHECK-LABEL: 'test_icmp2'
-; CHECK-DAG: DemandedBits: 0x1 for %3 = icmp eq i32 %1, %2
-; CHECK-DAG: DemandedBits: 0xFFF for %1 = and i32 %a, 255
-; CHECK-DAG: DemandedBits: 0xFF for %2 = ashr i32 %1, 4
-define i1 @test_icmp2(i32 %a, i32 %b) {
- %1 = and i32 %a, 255
- %2 = ashr i32 %1, 4
- %3 = icmp eq i32 %1, %2
- ret i1 %3
-}
-
-; CHECK-LABEL: 'test_icmp3'
-; CHECK-DAG: DemandedBits: 0xFFFFFFFF for %1 = and i32 %a, 255
-; CHECK-DAG: DemandedBits: 0x1 for %2 = icmp eq i32 -1, %1
-define i1 @test_icmp3(i32 %a) {
- %1 = and i32 %a, 255
- %2 = icmp eq i32 -1, %1
- ret i1 %2
-}
Modified: llvm/branches/release_38/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll?rev=259699&r1=259698&r2=259699&view=diff
==============================================================================
--- llvm/branches/release_38/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll (original)
+++ llvm/branches/release_38/test/Transforms/LoopVectorize/AArch64/loop-vectorization-factors.ll Wed Feb 3 15:24:31 2016
@@ -205,39 +205,5 @@ for.body:
br i1 %exitcond, label %for.cond.cleanup, label %for.body
}
-; CHECK-LABEL: @add_g
-; CHECK: load <16 x i8>
-; CHECK: xor <16 x i8>
-; CHECK: icmp ult <16 x i8>
-; CHECK: select <16 x i1> {{.*}}, <16 x i8>
-; CHECK: store <16 x i8>
-define void @add_g(i8* noalias nocapture readonly %p, i8* noalias nocapture readonly %q, i8* noalias nocapture %r, i8 %arg1, i32 %len) #0 {
- %1 = icmp sgt i32 %len, 0
- br i1 %1, label %.lr.ph, label %._crit_edge
-
-.lr.ph: ; preds = %0
- %2 = sext i8 %arg1 to i64
- br label %3
-
-._crit_edge: ; preds = %3, %0
- ret void
-
-; <label>:3 ; preds = %3, %.lr.ph
- %indvars.iv = phi i64 [ 0, %.lr.ph ], [ %indvars.iv.next, %3 ]
- %x4 = getelementptr inbounds i8, i8* %p, i64 %indvars.iv
- %x5 = load i8, i8* %x4
- %x7 = getelementptr inbounds i8, i8* %q, i64 %indvars.iv
- %x8 = load i8, i8* %x7
- %x9 = zext i8 %x5 to i32
- %x10 = xor i32 %x9, 255
- %x11 = icmp ult i32 %x10, 24
- %x12 = select i1 %x11, i32 %x10, i32 24
- %x13 = trunc i32 %x12 to i8
- store i8 %x13, i8* %x4
- %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
- %lftr.wideiv = trunc i64 %indvars.iv.next to i32
- %exitcond = icmp eq i32 %lftr.wideiv, %len
- br i1 %exitcond, label %._crit_edge, label %3
-}
attributes #0 = { nounwind }
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