[llvm-branch-commits] [llvm-branch] r232753 - [release_36] Cherry-pick r232179.

[Andrea Di Biagio]

Author: adibiagio
Date: Thu Mar 19 14:50:11 2015
New Revision: 232753

URL: http://llvm.org/viewvc/llvm-project?rev=232753&view=rev
Log:
[release_36] Cherry-pick r232179.

Original commit message:
[X86][AVX] Fix wrong lowering of v4x64 shuffles into concat_vector plus extract_subvector nodes.

This patch fixes a bug in the shuffle lowering logic implemented by function
'lowerV2X128VectorShuffle'.

The are few cases where function 'lowerV2X128VectorShuffle' wrongly expands a
shuffle of two v4X64 vectors into a CONCAT_VECTORS of two EXTRACT_SUBVECTOR
nodes. The problematic expansion only occurs when the shuffle mask M has an
'undef' element at position 2, and M is equivalent to mask <0,1,4,5>.
In that case, the algorithm propagates the wrong vector to one of the two
new EXTRACT_SUBVECTOR nodes.

Example:
;;
define <4 x double> @test(<4 x double> %A, <4 x double> %B) {
entry:
  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32><i32 undef, i32 1, i32 undef, i32 5>
  ret <4 x double> %0
}
;;

Before this patch, llc (-mattr=+avx) generated:
  vinsertf128 $1, %xmm0, %ymm0, %ymm0

With this patch, llc correctly generates:
  vinsertf128 $1, %xmm1, %ymm0, %ymm0

Added test lower-vec-shuffle-bug.ll

Differential Revision: http://reviews.llvm.org/D8259


Added:
    llvm/branches/release_36/test/CodeGen/X86/lower-vec-shuffle-bug.ll
Modified:
    llvm/branches/release_36/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/branches/release_36/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/X86/X86ISelLowering.cpp?rev=232753&r1=232752&r2=232753&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_36/lib/Target/X86/X86ISelLowering.cpp Thu Mar 19 14:50:11 2015
@@ -10094,12 +10094,12 @@ static SDValue lowerV2X128VectorShuffle(
                                VT.getVectorNumElements() / 2);
   // Check for patterns which can be matched with a single insert of a 128-bit
   // subvector.
-  if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
-      isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
+  bool OnlyUsesV1 = isShuffleEquivalent(Mask, 0, 1, 0, 1);
+  if (OnlyUsesV1 || isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
     SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
                               DAG.getIntPtrConstant(0));
     SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
-                              Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
+                              OnlyUsesV1 ? V1 : V2, DAG.getIntPtrConstant(0));
     return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
   }
   if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {

Added: llvm/branches/release_36/test/CodeGen/X86/lower-vec-shuffle-bug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/test/CodeGen/X86/lower-vec-shuffle-bug.ll?rev=232753&view=auto
==============================================================================
--- llvm/branches/release_36/test/CodeGen/X86/lower-vec-shuffle-bug.ll (added)
+++ llvm/branches/release_36/test/CodeGen/X86/lower-vec-shuffle-bug.ll Thu Mar 19 14:50:11 2015
@@ -0,0 +1,41 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s
+
+define <4 x double> @test1(<4 x double> %A, <4 x double> %B) {
+; CHECK-LABEL: test1:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 undef, i32 1, i32 undef, i32 5>
+  ret <4 x double> %0
+}
+
+define <4 x double> @test2(<4 x double> %A, <4 x double> %B) {
+; CHECK-LABEL: test2:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 undef, i32 1, i32 undef, i32 1>
+  ret <4 x double> %0
+}
+
+define <4 x double> @test3(<4 x double> %A, <4 x double> %B) {
+; CHECK-LABEL: test3:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 0, i32 1, i32 undef, i32 5>
+  ret <4 x double> %0
+}
+
+define <4 x double> @test4(<4 x double> %A, <4 x double> %B) {
+; CHECK-LABEL: test4:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 0, i32 1, i32 undef, i32 1>
+  ret <4 x double> %0
+}