[llvm-branch-commits] [llvm-branch] r244096 - Merging r243984:

Hans Wennborg hans at hanshq.net
Wed Aug 5 11:46:47 PDT 2015 

Author: hans
Date: Wed Aug  5 13:46:46 2015
New Revision: 244096

URL: http://llvm.org/viewvc/llvm-project?rev=244096&view=rev
Log:
Merging r243984:
------------------------------------------------------------------------
r243984 | vkalintiris | 2015-08-04 07:26:35 -0700 (Tue, 04 Aug 2015) | 11 lines

Revert r229675 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.

It introduced two regressions on 64-bit big-endian targets running under N32
(MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4, and
MultiSource/Applications/kimwitu++/kc) The issue is that on 64-bit targets
comparisons such as BEQ compare the whole GPR64 but incorrectly tell the
instruction selector that they operate on GPR32's. This leads to the
elimination of i32->i64 extensions that are actually required by
comparisons to work correctly.

There's currently a patch under review that fixes this problem.
------------------------------------------------------------------------

Modified:
    llvm/branches/release_37/   (props changed)
    llvm/branches/release_37/lib/Target/Mips/Mips64InstrInfo.td
    llvm/branches/release_37/test/CodeGen/Mips/delay-slot-kill.ll
    llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/and.ll
    llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/or.ll
    llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/xor.ll

Propchange: llvm/branches/release_37/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Aug  5 13:46:46 2015
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243057,243116,243263,243294,243361,243469,243485,243500,243519,243531,243589,243609,243636,243638-243640,243745,243986
+/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243057,243116,243263,243294,243361,243469,243485,243500,243519,243531,243589,243609,243636,243638-243640,243745,243984,243986

Modified: llvm/branches/release_37/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/Mips/Mips64InstrInfo.td?rev=244096&r1=244095&r2=244096&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/branches/release_37/lib/Target/Mips/Mips64InstrInfo.td Wed Aug  5 13:46:46 2015
@@ -500,14 +500,6 @@ def : MipsPat<(trunc (assertzext GPR64:$
 def : MipsPat<(i32 (trunc GPR64:$src)),
               (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
 
-// Bypass trunc nodes for bitwise ops.
-def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))),
-              (EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
-def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))),
-              (EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
-def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))),
-              (EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
-
 // variable shift instructions patterns
 def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))),
               (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;

Modified: llvm/branches/release_37/test/CodeGen/Mips/delay-slot-kill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/delay-slot-kill.ll?rev=244096&r1=244095&r2=244096&view=diff
==============================================================================
--- llvm/branches/release_37/test/CodeGen/Mips/delay-slot-kill.ll (original)
+++ llvm/branches/release_37/test/CodeGen/Mips/delay-slot-kill.ll Wed Aug  5 13:46:46 2015
@@ -1,4 +1,6 @@
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s
+; We have to XFAIL this temporarily because of the reversion of r229675.
+; XFAIL: *
 
 ; Currently, the following IR assembly generates a KILL instruction between
 ; the bitwise-and instruction and the return instruction. We verify that the

Modified: llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/and.ll?rev=244096&r1=244095&r2=244096&view=diff
==============================================================================
--- llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/and.ll (original)
+++ llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/and.ll Wed Aug  5 13:46:46 2015
@@ -59,7 +59,10 @@ define signext i32 @and_i32(i32 signext
 entry:
 ; ALL-LABEL: and_i32:
 
-  ; ALL:          and     $2, $4, $5
+  ; GP32:         and     $2, $4, $5
+
+  ; GP64:         and     $[[T0:[0-9]+]], $4, $5
+  ; GP64:         sll     $2, $[[T0]], 0
 
   %r = and i32 %a, %b
   ret i32 %r

Modified: llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/or.ll?rev=244096&r1=244095&r2=244096&view=diff
==============================================================================
--- llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/or.ll (original)
+++ llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/or.ll Wed Aug  5 13:46:46 2015
@@ -59,7 +59,11 @@ define signext i32 @or_i32(i32 signext %
 entry:
 ; ALL-LABEL: or_i32:
 
-  ; ALL:          or     $2, $4, $5
+  ; GP32:         or     $2, $4, $5
+
+  ; GP64:         or     $[[T0:[0-9]+]], $4, $5
+  ; FIXME: The sll instruction below is redundant.
+  ; GP64:         sll     $2, $[[T0]], 0
 
   %r = or i32 %a, %b
   ret i32 %r

Modified: llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/xor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/xor.ll?rev=244096&r1=244095&r2=244096&view=diff
==============================================================================
--- llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/xor.ll (original)
+++ llvm/branches/release_37/test/CodeGen/Mips/llvm-ir/xor.ll Wed Aug  5 13:46:46 2015
@@ -59,7 +59,10 @@ define signext i32 @xor_i32(i32 signext
 entry:
 ; ALL-LABEL: xor_i32:
 
-  ; ALL:          xor     $2, $4, $5
+  ; GP32:         xor     $2, $4, $5
+
+  ; GP64:         xor     $[[T0:[0-9]+]], $4, $5
+  ; GP64:         sll     $2, $[[T0]], 0
 
   %r = xor i32 %a, %b
   ret i32 %r

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