[llvm-branch-commits] [llvm-branch] r235623 - Merging r229226:

[Tom Stellard]

Author: tstellar
Date: Thu Apr 23 14:14:42 2015
New Revision: 235623

URL: http://llvm.org/viewvc/llvm-project?rev=235623&view=rev
Log:
Merging r229226:

------------------------------------------------------------------------
r229226 | Matthew.Arsenault | 2015-02-13 21:55:56 -0500 (Fri, 13 Feb 2015) | 5 lines

R600/SI: Fix copies from SGPR to VCC

This shows up without optimizations when vcc is required
to be used.

------------------------------------------------------------------------

Modified:
    llvm/branches/release_36/lib/Target/R600/SIInstrInfo.cpp

Modified: llvm/branches/release_36/lib/Target/R600/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_36/lib/Target/R600/SIInstrInfo.cpp?rev=235623&r1=235622&r2=235623&view=diff
==============================================================================
--- llvm/branches/release_36/lib/Target/R600/SIInstrInfo.cpp (original)
+++ llvm/branches/release_36/lib/Target/R600/SIInstrInfo.cpp Thu Apr 23 14:14:42 2015
@@ -334,12 +334,17 @@ SIInstrInfo::copyPhysReg(MachineBasicBlo
 
   } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
     if (DestReg == AMDGPU::VCC) {
-      // FIXME: Hack until VReg_1 removed.
+      if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
+        BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
+          .addReg(SrcReg, getKillRegState(KillSrc));
+      } else {
+        // FIXME: Hack until VReg_1 removed.
+        assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
+        BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC)
+          .addImm(0)
+          .addReg(SrcReg, getKillRegState(KillSrc));
+      }
 
-      assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
-      BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC)
-        .addImm(0)
-        .addReg(SrcReg, getKillRegState(KillSrc));
       return;
     }