[llvm-branch-commits] [llvm-branch] r214309 - Merging r213773:

[Justin Holewinski]

Author: jholewinski
Date: Wed Jul 30 09:49:09 2014
New Revision: 214309

URL: http://llvm.org/viewvc/llvm-project?rev=214309&view=rev
Log:
Merging r213773:
------------------------------------------------------------------------
r213773 | jholewinski | 2014-07-23 13:40:45 -0400 (Wed, 23 Jul 2014) | 5 lines

[NVPTX] Make sure we do not generate MULWIDE ISD nodes when optimizations are disabled

With optimizations disabled, we disable the isel patterns for mul.wide; but we
were still generating MULWIDE ISD nodes.  Now, we only try to generate MULWIDE
ISD nodes in DAGCombine if the optimization level is not zero.
------------------------------------------------------------------------


Modified:
    llvm/branches/release_35/   (props changed)
    llvm/branches/release_35/lib/Target/NVPTX/NVPTXISelLowering.cpp
    llvm/branches/release_35/test/CodeGen/NVPTX/mulwide.ll

Propchange: llvm/branches/release_35/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Jul 30 09:49:09 2014
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,213653,213749,213815,213847,213880,213884,213894-213895,213915,214129,214180,214287
+/llvm/trunk:155241,213653,213749,213773,213815,213847,213880,213884,213894-213895,213915,214129,214180,214287

Modified: llvm/branches/release_35/lib/Target/NVPTX/NVPTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=214309&r1=214308&r2=214309&view=diff
==============================================================================
--- llvm/branches/release_35/lib/Target/NVPTX/NVPTXISelLowering.cpp (original)
+++ llvm/branches/release_35/lib/Target/NVPTX/NVPTXISelLowering.cpp Wed Jul 30 09:49:09 2014
@@ -4213,8 +4213,7 @@ static SDValue PerformSHLCombine(SDNode
 
 SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
                                                DAGCombinerInfo &DCI) const {
-  // FIXME: Get this from the DAG somehow
-  CodeGenOpt::Level OptLevel = CodeGenOpt::Aggressive;
+  CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
   switch (N->getOpcode()) {
     default: break;
     case ISD::ADD:

Modified: llvm/branches/release_35/test/CodeGen/NVPTX/mulwide.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_35/test/CodeGen/NVPTX/mulwide.ll?rev=214309&r1=214308&r2=214309&view=diff
==============================================================================
--- llvm/branches/release_35/test/CodeGen/NVPTX/mulwide.ll (original)
+++ llvm/branches/release_35/test/CodeGen/NVPTX/mulwide.ll Wed Jul 30 09:49:09 2014
@@ -1,35 +1,44 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -O3 | FileCheck %s --check-prefix=OPT
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -O0 | FileCheck %s --check-prefix=NOOPT
 
-; CHECK: mulwide16
+; OPT-LABEL: @mulwide16
+; NOOPT-LABEL: @mulwide16
 define i32 @mulwide16(i16 %a, i16 %b) {
-; CHECK: mul.wide.s16
+; OPT: mul.wide.s16
+; NOOPT: mul.lo.s32
   %val0 = sext i16 %a to i32
   %val1 = sext i16 %b to i32
   %val2 = mul i32 %val0, %val1
   ret i32 %val2
 }
 
-; CHECK: mulwideu16
+; OPT-LABEL: @mulwideu16
+; NOOPT-LABEL: @mulwideu16
 define i32 @mulwideu16(i16 %a, i16 %b) {
-; CHECK: mul.wide.u16
+; OPT: mul.wide.u16
+; NOOPT: mul.lo.s32
   %val0 = zext i16 %a to i32
   %val1 = zext i16 %b to i32
   %val2 = mul i32 %val0, %val1
   ret i32 %val2
 }
 
-; CHECK: mulwide32
+; OPT-LABEL: @mulwide32
+; NOOPT-LABEL: @mulwide32
 define i64 @mulwide32(i32 %a, i32 %b) {
-; CHECK: mul.wide.s32
+; OPT: mul.wide.s32
+; NOOPT: mul.lo.s64
   %val0 = sext i32 %a to i64
   %val1 = sext i32 %b to i64
   %val2 = mul i64 %val0, %val1
   ret i64 %val2
 }
 
-; CHECK: mulwideu32
+; OPT-LABEL: @mulwideu32
+; NOOPT-LABEL: @mulwideu32
 define i64 @mulwideu32(i32 %a, i32 %b) {
-; CHECK: mul.wide.u32
+; OPT: mul.wide.u32
+; NOOPT: mul.lo.s64
   %val0 = zext i32 %a to i64
   %val1 = zext i32 %b to i64
   %val2 = mul i64 %val0, %val1