[llvm-branch-commits] [llvm-branch] r206049 - Merging r195971:

[Tom Stellard]

Author: tstellar
Date: Fri Apr 11 14:26:56 2014
New Revision: 206049

URL: http://llvm.org/viewvc/llvm-project?rev=206049&view=rev
Log:
Merging r195971:

------------------------------------------------------------------------
r195971 | juergen | 2013-11-29 22:07:16 -0500 (Fri, 29 Nov 2013) | 2 lines

Force CPU type to unbreak unit tests on Haswell machines.

------------------------------------------------------------------------

Modified:
    llvm/branches/release_34/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
    llvm/branches/release_34/test/CodeGen/X86/fma4-intrinsics-x86_64.ll
    llvm/branches/release_34/test/CodeGen/X86/fp-fast.ll
    llvm/branches/release_34/test/CodeGen/X86/vec_shift4.ll
    llvm/branches/release_34/test/CodeGen/X86/vshift-4.ll

Modified: llvm/branches/release_34/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/CodeGen/X86/2009-06-05-VZextByteShort.ll?rev=206049&r1=206048&r2=206049&view=diff
==============================================================================
--- llvm/branches/release_34/test/CodeGen/X86/2009-06-05-VZextByteShort.ll (original)
+++ llvm/branches/release_34/test/CodeGen/X86/2009-06-05-VZextByteShort.ll Fri Apr 11 14:26:56 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 > %t1
+; RUN: llc < %s -march=x86 -mcpu=core2 > %t1
 ; RUN: grep movzwl %t1 | count 2
 ; RUN: grep movzbl %t1 | count 1
 ; RUN: grep movd %t1 | count 4

Modified: llvm/branches/release_34/test/CodeGen/X86/fma4-intrinsics-x86_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/CodeGen/X86/fma4-intrinsics-x86_64.ll?rev=206049&r1=206048&r2=206049&view=diff
==============================================================================
--- llvm/branches/release_34/test/CodeGen/X86/fma4-intrinsics-x86_64.ll (original)
+++ llvm/branches/release_34/test/CodeGen/X86/fma4-intrinsics-x86_64.ll Fri Apr 11 14:26:56 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -march=x86-64 -mattr=+avx,+fma4 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -march=x86-64 -mcpu=corei7-avx -mattr=+fma4 | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -mattr=+avx,-fma | FileCheck %s
 
 ; VFMADD

Modified: llvm/branches/release_34/test/CodeGen/X86/fp-fast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/CodeGen/X86/fp-fast.ll?rev=206049&r1=206048&r2=206049&view=diff
==============================================================================
--- llvm/branches/release_34/test/CodeGen/X86/fp-fast.ll (original)
+++ llvm/branches/release_34/test/CodeGen/X86/fp-fast.ll Fri Apr 11 14:26:56 2014
@@ -1,4 +1,4 @@
-; RUN: llc -march=x86-64 -mattr=+avx,-fma4 -mtriple=x86_64-apple-darwin -enable-unsafe-fp-math < %s | FileCheck %s
+; RUN: llc -march=x86-64 -mcpu=corei7-avx -enable-unsafe-fp-math < %s | FileCheck %s
 
 ; CHECK-LABEL: test1
 define float @test1(float %a) {

Modified: llvm/branches/release_34/test/CodeGen/X86/vec_shift4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/CodeGen/X86/vec_shift4.ll?rev=206049&r1=206048&r2=206049&view=diff
==============================================================================
--- llvm/branches/release_34/test/CodeGen/X86/vec_shift4.ll (original)
+++ llvm/branches/release_34/test/CodeGen/X86/vec_shift4.ll Fri Apr 11 14:26:56 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+sse4.1 | FileCheck %s
+; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
 
 define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
 entry:

Modified: llvm/branches/release_34/test/CodeGen/X86/vshift-4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/CodeGen/X86/vshift-4.ll?rev=206049&r1=206048&r2=206049&view=diff
==============================================================================
--- llvm/branches/release_34/test/CodeGen/X86/vshift-4.ll (original)
+++ llvm/branches/release_34/test/CodeGen/X86/vshift-4.ll Fri Apr 11 14:26:56 2014
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
+; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s
 
 ; test vector shifts converted to proper SSE2 vector shifts when the shift
 ; amounts are the same when using a shuffle splat.