[llvm-branch-commits] [llvm-branch] r205821 - Merging r200288:

[Tom Stellard]

Author: tstellar
Date: Tue Apr  8 19:20:48 2014
New Revision: 205821

URL: http://llvm.org/viewvc/llvm-project?rev=205821&view=rev
Log:
Merging r200288:

------------------------------------------------------------------------
r200288 | hfinkel | 2014-01-28 00:32:58 -0500 (Tue, 28 Jan 2014) | 5 lines

Handle spilling the PPC GPRC_NOR0 register class

GPRC_NOR0 is not a subclass of GPRC (because it also contains the ZERO pseudo
register). As a result, we also need to check for it in the spilling code.

------------------------------------------------------------------------

Added:
    llvm/branches/release_34/test/CodeGen/PowerPC/spill-nor0.ll
Modified:
    llvm/branches/release_34/lib/Target/PowerPC/PPCInstrInfo.cpp

Modified: llvm/branches/release_34/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=205821&r1=205820&r2=205821&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/branches/release_34/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Apr  8 19:20:48 2014
@@ -570,12 +570,14 @@ PPCInstrInfo::StoreRegToStackSlot(Machin
   // update isStoreToStackSlot.
 
   DebugLoc DL;
-  if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
+  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
+      PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
                                        .addReg(SrcReg,
                                                getKillRegState(isKill)),
                                        FrameIdx));
-  } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
+  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
+             PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
                                        .addReg(SrcReg,
                                                getKillRegState(isKill)),
@@ -695,10 +697,12 @@ PPCInstrInfo::LoadRegFromStackSlot(Machi
   // Note: If additional load instructions are added here,
   // update isLoadFromStackSlot.
 
-  if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
+  if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
+      PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
                                                DestReg), FrameIdx));
-  } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
+  } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
+             PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
                                        FrameIdx));
   } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {

Added: llvm/branches/release_34/test/CodeGen/PowerPC/spill-nor0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/CodeGen/PowerPC/spill-nor0.ll?rev=205821&view=auto
==============================================================================
--- llvm/branches/release_34/test/CodeGen/PowerPC/spill-nor0.ll (added)
+++ llvm/branches/release_34/test/CodeGen/PowerPC/spill-nor0.ll Tue Apr  8 19:20:48 2014
@@ -0,0 +1,23 @@
+; RUN: llc < %s -O0 -mcpu=ppc64 | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @_ZN4llvm3sys17RunningOnValgrindEv() #0 {
+entry:
+  br i1 undef, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  ret void
+
+if.end:                                           ; preds = %entry
+  %0 = call i64 asm sideeffect "mr 3,$1\0A\09mr 4,$2\0A\09rotldi 0,0,3  ; rotldi 0,0,13\0A\09rotldi 0,0,61 ; rotldi 0,0,51\0A\09or 1,1,1\0A\09mr $0,3", "=b,b,b,~{cc},~{memory},~{r3},~{r4}"(i32 0, i64* undef) #0
+  unreachable
+
+; CHECK-LABEL: @_ZN4llvm3sys17RunningOnValgrindEv
+; CHECK: stw
+; CHECK: lwz
+}
+
+attributes #0 = { nounwind }
+