[llvm-branch-commits] [llvm-branch] r196025 - Merging r195903:

[Bill Wendling]

Author: void
Date: Sat Nov 30 22:36:39 2013
New Revision: 196025

URL: http://llvm.org/viewvc/llvm-project?rev=196025&view=rev
Log:
Merging r195903:
------------------------------------------------------------------------
r195903 | haoliu | 2013-11-27 17:07:45 -0800 (Wed, 27 Nov 2013) | 2 lines

AArch64: Fix a bug about disassembling post-index load single element to 4 vectors

------------------------------------------------------------------------

Modified:
    llvm/branches/release_34/   (props changed)
    llvm/branches/release_34/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    llvm/branches/release_34/test/MC/Disassembler/AArch64/neon-instructions.txt

Propchange: llvm/branches/release_34/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Sat Nov 30 22:36:39 2013
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195408,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195493,195514,195528,195547,195567,195573-195576,195590-195591,195599,195632,195635-195636,195670,195677,195679,195682,195684,195713,195716,195769,195773,195779,195782,195787-195788,195791,195798,195803,195812,195827,195834,195843-195844,195878-195881,195887,195915,196004
+/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195408,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195493,195514,195528,195547,195567,195573-195576,195590-195591,195599,195632,195635-195636,195670,195677,195679,195682,195684,195713,195716,195769,195773,195779,195782,195787-195788,195791,195798,195803,195812,195827,195834,195843-195844,195878-195881,195887,195903,195915,196004

Modified: llvm/branches/release_34/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp?rev=196025&r1=196024&r2=196025&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (original)
+++ llvm/branches/release_34/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Sat Nov 30 22:36:39 2013
@@ -1342,13 +1342,13 @@ static DecodeStatus DecodeVLDSTLanePostI
   case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
     switch (Opc) {
     case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
-      TransferBytes = 3; break;
+      TransferBytes = 4; break;
     case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register:
-      TransferBytes = 6; break;
+      TransferBytes = 8; break;
     case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register:
-      TransferBytes = 12; break;
+      TransferBytes = 16; break;
     case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register:
-      TransferBytes = 24; break;
+      TransferBytes = 32; break;
     }
     IsLoad = true;
     NumVecs = 4;

Modified: llvm/branches/release_34/test/MC/Disassembler/AArch64/neon-instructions.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/MC/Disassembler/AArch64/neon-instructions.txt?rev=196025&r1=196024&r2=196025&view=diff
==============================================================================
--- llvm/branches/release_34/test/MC/Disassembler/AArch64/neon-instructions.txt (original)
+++ llvm/branches/release_34/test/MC/Disassembler/AArch64/neon-instructions.txt Sat Nov 30 22:36:39 2013
@@ -2129,7 +2129,8 @@
 # CHECK: ld1 {v0.b}[9], [x0], #1
 # CHECK: ld2 {v15.h, v16.h}[7], [x15], #4
 # CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3
-# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #24
+# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32
+# CHECK: ld4 {v0.h, v1.h, v2.h, v3.h}[7], [x0], x0
 # CHECK: st1 {v0.d}[1], [x0], #8
 # CHECK: st2 {v31.s, v0.s}[3], [sp], #8
 # CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6
@@ -2138,6 +2139,7 @@
 0xef,0x59,0xff,0x4d
 0xff,0xb3,0xc3,0x4d
 0x00,0xa4,0xff,0x4d
+0x00,0x78,0xe0,0x4d
 0x00,0x84,0x9f,0x4d
 0xff,0x93,0xbf,0x4d
 0xef,0x79,0x9f,0x4d