[llvm-branch-commits] [llvm-branch] r195320 - Merging r195272:

[Bill Wendling]

Author: void
Date: Thu Nov 21 01:07:01 2013
New Revision: 195320

URL: http://llvm.org/viewvc/llvm-project?rev=195320&view=rev
Log:
Merging r195272:
------------------------------------------------------------------------
r195272 | hfinkel | 2013-11-20 12:54:55 -0800 (Wed, 20 Nov 2013) | 4 lines

PPC popcnt[dw] do not have record forms

The instruction definitions incorrectly specified that popcntd and popcntw have
record forms; they do not. This mistake was causing invalid code generation.
------------------------------------------------------------------------

Modified:
    llvm/branches/release_34/   (props changed)
    llvm/branches/release_34/lib/Target/PowerPC/PPCInstr64Bit.td
    llvm/branches/release_34/test/CodeGen/PowerPC/optcmp.ll

Propchange: llvm/branches/release_34/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Nov 21 01:07:01 2013
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195138,195152,195157,195161-195162,195193,195318
+/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195138,195152,195157,195161-195162,195193,195272,195318

Modified: llvm/branches/release_34/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/PowerPC/PPCInstr64Bit.td?rev=195320&r1=195319&r2=195320&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/branches/release_34/lib/Target/PowerPC/PPCInstr64Bit.td Thu Nov 21 01:07:01 2013
@@ -529,16 +529,16 @@ defm SRADI  : XSForm_1rc<31, 413, (outs
 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
                         "cntlzd", "$rA, $rS", IntGeneral,
                         [(set i64:$rA, (ctlz i64:$rS))]>;
-defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
-                         "popcntd", "$rA, $rS", IntGeneral,
-                         [(set i64:$rA, (ctpop i64:$rS))]>;
+def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
+                       "popcntd $rA, $rS", IntGeneral,
+                       [(set i64:$rA, (ctpop i64:$rS))]>;
 
 // popcntw also does a population count on the high 32 bits (storing the
 // results in the high 32-bits of the output). We'll ignore that here (which is
 // safe because we never separately use the high part of the 64-bit registers).
-defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS),
-                         "popcntw", "$rA, $rS", IntGeneral,
-                         [(set i32:$rA, (ctpop i32:$rS))]>;
+def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
+                       "popcntw $rA, $rS", IntGeneral,
+                       [(set i32:$rA, (ctpop i32:$rS))]>;
 
 defm DIVD  : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                        "divd", "$rT, $rA, $rB", IntDivD,

Modified: llvm/branches/release_34/test/CodeGen/PowerPC/optcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/CodeGen/PowerPC/optcmp.ll?rev=195320&r1=195319&r2=195320&view=diff
==============================================================================
--- llvm/branches/release_34/test/CodeGen/PowerPC/optcmp.ll (original)
+++ llvm/branches/release_34/test/CodeGen/PowerPC/optcmp.ll Thu Nov 21 01:07:01 2013
@@ -134,3 +134,19 @@ entry:
 ; CHECK-NOT: fsubs. 0, 1, 2
 ; CHECK: stfs 0, 0(5)
 }
+
+declare i64 @llvm.ctpop.i64(i64);
+
+define signext i64 @fooct(i64 signext %a, i64 signext %b, i64* nocapture %c) #0 {
+entry:
+  %sub = sub nsw i64 %a, %b
+  %subc = call i64 @llvm.ctpop.i64(i64 %sub)
+  store i64 %subc, i64* %c, align 4
+  %cmp = icmp sgt i64 %subc, 0
+  %cond = select i1 %cmp, i64 %a, i64 %b
+  ret i64 %cond
+
+; CHECK: @fooct
+; CHECK-NOT: popcntd.
+}
+