[llvm-branch-commits] [llvm-branch] r197321 - Merging r197228:
Bill Wendling
isanbard at gmail.com
Sat Dec 14 00:01:30 PST 2013
Author: void
Date: Sat Dec 14 02:01:30 2013
New Revision: 197321
URL: http://llvm.org/viewvc/llvm-project?rev=197321&view=rev
Log:
Merging r197228:
------------------------------------------------------------------------
r197228 | d0k | 2013-12-13 05:40:24 -0800 (Fri, 13 Dec 2013) | 8 lines
X86: When lowering shl_parts, don't emit shift amounts larger than the bit width.
While it's safe for the X86-specific shift nodes, dag combining will
kill generic nodes. Insert an AND to make it safe, isel will nuke it
as x86's shift instructions have an implicit AND.
Fixes PR16108, which contains a contraption to hit this case in between
constant folders.
------------------------------------------------------------------------
Modified:
llvm/branches/release_34/ (props changed)
llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/release_34/test/CodeGen/X86/legalize-shift-64.ll
Propchange: llvm/branches/release_34/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Sat Dec 14 02:01:30 2013
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195401,195408,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195495,195504-195505,195514,195528,195535,195547,195567,195573-195576,195590-195591,195599,195632,195635-195636,195670,195677,195679,195682,195684,195713,195716,195769,195773,195779,195782,195787-195788,195791,195803,195812,195827,195834,195843-195844,195878-195881,195887,195903,195905,195912,195915,195932,195936-195943,195972-195973,195975-195976,196004,196044-196046,196069,196100,196104,196129,196144,196151,196153,196156,196158,196172,196189-196192,196198-196199,196208-196211,196261,196267,196269,196294,196359-196362,196369,196391,196456,196493,196508,196532-196533,196535,196538,196588,196611-196612,196637-196638,196658,196668,196725,196735,196751,196!
755,19676
8,196806,196858,197089
+/llvm/trunk:155241,195092-195094,195100,195102-195103,195118,195129,195136,195138,195148,195152,195156-195157,195161-195162,195193,195272,195317-195318,195327,195330,195333,195339,195343,195355,195364,195379,195397-195399,195401,195408,195421,195423-195424,195432,195439,195444,195455-195456,195469,195476-195477,195479,195491-195495,195504-195505,195514,195528,195535,195547,195567,195573-195576,195590-195591,195599,195632,195635-195636,195670,195677,195679,195682,195684,195713,195716,195769,195773,195779,195782,195787-195788,195791,195803,195812,195827,195834,195843-195844,195878-195881,195887,195903,195905,195912,195915,195932,195936-195943,195972-195973,195975-195976,196004,196044-196046,196069,196100,196104,196129,196144,196151,196153,196156,196158,196172,196189-196192,196198-196199,196208-196211,196261,196267,196269,196294,196359-196362,196369,196391,196456,196493,196508,196532-196533,196535,196538,196588,196611-196612,196637-196638,196658,196668,196725,196735,196751,196!
755,19676
8,196806,196858,197089,197228
Modified: llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp?rev=197321&r1=197320&r2=197321&view=diff
==============================================================================
--- llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/release_34/lib/Target/X86/X86ISelLowering.cpp Sat Dec 14 02:01:30 2013
@@ -8424,6 +8424,11 @@ SDValue X86TargetLowering::LowerShiftPar
SDValue ShOpLo = Op.getOperand(0);
SDValue ShOpHi = Op.getOperand(1);
SDValue ShAmt = Op.getOperand(2);
+ // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
+ // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
+ // during isel.
+ SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
+ DAG.getConstant(VTBits - 1, MVT::i8));
SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
DAG.getConstant(VTBits - 1, MVT::i8))
: DAG.getConstant(0, VT);
@@ -8431,12 +8436,15 @@ SDValue X86TargetLowering::LowerShiftPar
SDValue Tmp2, Tmp3;
if (Op.getOpcode() == ISD::SHL_PARTS) {
Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
- Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
+ Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
} else {
Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
- Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
+ Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
}
+ // If the shift amount is larger or equal than the width of a part we can't
+ // rely on the results of shld/shrd. Insert a test and select the appropriate
+ // values for large shift amounts.
SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
DAG.getConstant(VTBits, MVT::i8));
SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
Modified: llvm/branches/release_34/test/CodeGen/X86/legalize-shift-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/CodeGen/X86/legalize-shift-64.ll?rev=197321&r1=197320&r2=197321&view=diff
==============================================================================
--- llvm/branches/release_34/test/CodeGen/X86/legalize-shift-64.ll (original)
+++ llvm/branches/release_34/test/CodeGen/X86/legalize-shift-64.ll Sat Dec 14 02:01:30 2013
@@ -64,3 +64,31 @@ define <2 x i64> @test5(<2 x i64> %A, <2
; CHECK: shl
; CHECK: shldl
}
+
+; PR16108
+define i32 @test6() {
+ %x = alloca i32, align 4
+ %t = alloca i64, align 8
+ store i32 1, i32* %x, align 4
+ store i64 1, i64* %t, align 8 ;; DEAD
+ %load = load i32* %x, align 4
+ %shl = shl i32 %load, 8
+ %add = add i32 %shl, -224
+ %sh_prom = zext i32 %add to i64
+ %shl1 = shl i64 1, %sh_prom
+ %cmp = icmp ne i64 %shl1, 4294967296
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ ret i32 1
+
+if.end: ; preds = %entry
+ ret i32 0
+
+; CHECK-LABEL: test6:
+; CHECK-NOT: andb $31
+; CHECK: sete
+; CHECK: movzbl
+; CHECK: xorl $1
+; CHECK: orl
+}
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