[llvm-branch-commits] [llvm-branch] r196521 - Revert r191049 and r191059. They were causing failures. See PR17975.
Bob Wilson
bob.wilson at apple.com
Mon Dec 9 12:54:24 PST 2013
Just for the record, this also reverts 191905.
On Dec 5, 2013, at 10:29 AM, Bill Wendling <isanbard at gmail.com> wrote:
> Author: void
> Date: Thu Dec 5 12:29:11 2013
> New Revision: 196521
>
> URL: http://llvm.org/viewvc/llvm-project?rev=196521&view=rev
> Log:
> Revert r191049 and r191059. They were causing failures. See PR17975.
>
> Removed:
> llvm/branches/release_34/test/CodeGen/X86/rotate3.ll
> Modified:
> llvm/branches/release_34/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>
> Modified: llvm/branches/release_34/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=196521&r1=196520&r2=196521&view=diff
> ==============================================================================
> --- llvm/branches/release_34/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/branches/release_34/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Dec 5 12:29:11 2013
> @@ -3342,7 +3342,6 @@ SDNode *DAGCombiner::MatchRotate(SDValue
> unsigned OpSizeInBits = VT.getSizeInBits();
> SDValue LHSShiftArg = LHSShift.getOperand(0);
> SDValue LHSShiftAmt = LHSShift.getOperand(1);
> - SDValue RHSShiftArg = RHSShift.getOperand(0);
> SDValue RHSShiftAmt = RHSShift.getOperand(1);
>
> // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
> @@ -3402,32 +3401,10 @@ SDNode *DAGCombiner::MatchRotate(SDValue
> // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
> // (rotr x, (sub 32, y))
> if (ConstantSDNode *SUBC =
> - dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
> - if (SUBC->getAPIntValue() == OpSizeInBits) {
> + dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0)))
> + if (SUBC->getAPIntValue() == OpSizeInBits)
> return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg,
> HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
> - } else if (LHSShiftArg.getOpcode() == ISD::ZERO_EXTEND ||
> - LHSShiftArg.getOpcode() == ISD::ANY_EXTEND) {
> - // fold (or (shl (*ext x), (*ext y)),
> - // (srl (*ext x), (*ext (sub 32, y)))) ->
> - // (*ext (rotl x, y))
> - // fold (or (shl (*ext x), (*ext y)),
> - // (srl (*ext x), (*ext (sub 32, y)))) ->
> - // (*ext (rotr x, (sub 32, y)))
> - SDValue LArgExtOp0 = LHSShiftArg.getOperand(0);
> - EVT LArgVT = LArgExtOp0.getValueType();
> - bool HasROTRWithLArg = TLI.isOperationLegalOrCustom(ISD::ROTR, LArgVT);
> - bool HasROTLWithLArg = TLI.isOperationLegalOrCustom(ISD::ROTL, LArgVT);
> - if (HasROTRWithLArg || HasROTLWithLArg) {
> - if (LArgVT.getSizeInBits() == SUBC->getAPIntValue()) {
> - SDValue V =
> - DAG.getNode(HasROTLWithLArg ? ISD::ROTL : ISD::ROTR, DL, LArgVT,
> - LArgExtOp0, HasROTL ? LHSShiftAmt : RHSShiftAmt);
> - return DAG.getNode(LHSShiftArg.getOpcode(), DL, VT, V).getNode();
> - }
> - }
> - }
> - }
> } else if (LExtOp0.getOpcode() == ISD::SUB &&
> RExtOp0 == LExtOp0.getOperand(1)) {
> // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
> @@ -3435,32 +3412,10 @@ SDNode *DAGCombiner::MatchRotate(SDValue
> // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
> // (rotl x, (sub 32, y))
> if (ConstantSDNode *SUBC =
> - dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
> - if (SUBC->getAPIntValue() == OpSizeInBits) {
> + dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0)))
> + if (SUBC->getAPIntValue() == OpSizeInBits)
> return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg,
> HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
> - } else if (RHSShiftArg.getOpcode() == ISD::ZERO_EXTEND ||
> - RHSShiftArg.getOpcode() == ISD::ANY_EXTEND) {
> - // fold (or (shl (*ext x), (*ext (sub 32, y))),
> - // (srl (*ext x), (*ext y))) ->
> - // (*ext (rotl x, y))
> - // fold (or (shl (*ext x), (*ext (sub 32, y))),
> - // (srl (*ext x), (*ext y))) ->
> - // (*ext (rotr x, (sub 32, y)))
> - SDValue RArgExtOp0 = RHSShiftArg.getOperand(0);
> - EVT RArgVT = RArgExtOp0.getValueType();
> - bool HasROTRWithRArg = TLI.isOperationLegalOrCustom(ISD::ROTR, RArgVT);
> - bool HasROTLWithRArg = TLI.isOperationLegalOrCustom(ISD::ROTL, RArgVT);
> - if (HasROTRWithRArg || HasROTLWithRArg) {
> - if (RArgVT.getSizeInBits() == SUBC->getAPIntValue()) {
> - SDValue V =
> - DAG.getNode(HasROTRWithRArg ? ISD::ROTR : ISD::ROTL, DL, RArgVT,
> - RArgExtOp0, HasROTR ? RHSShiftAmt : LHSShiftAmt);
> - return DAG.getNode(RHSShiftArg.getOpcode(), DL, VT, V).getNode();
> - }
> - }
> - }
> - }
> }
>
> return 0;
>
> Removed: llvm/branches/release_34/test/CodeGen/X86/rotate3.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_34/test/CodeGen/X86/rotate3.ll?rev=196520&view=auto
> ==============================================================================
> --- llvm/branches/release_34/test/CodeGen/X86/rotate3.ll (original)
> +++ llvm/branches/release_34/test/CodeGen/X86/rotate3.ll (removed)
> @@ -1,76 +0,0 @@
> -; Check that (or (shl x, y), (srl x, (sub 32, y))) is folded into (rotl x, y)
> -; and (or (shl x, (sub 32, y)), (srl x, r)) into (rotr x, y) even if the
> -; argument is zero extended. Fix for PR16726.
> -
> -; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s
> -
> -define zeroext i8 @rolbyte(i32 %nBits_arg, i8 %x_arg) nounwind readnone {
> -entry:
> - %tmp1 = zext i8 %x_arg to i32
> - %tmp3 = shl i32 %tmp1, %nBits_arg
> - %tmp8 = sub i32 8, %nBits_arg
> - %tmp10 = lshr i32 %tmp1, %tmp8
> - %tmp11 = or i32 %tmp3, %tmp10
> - %tmp12 = trunc i32 %tmp11 to i8
> - ret i8 %tmp12
> -}
> -; CHECK: rolb %cl, %{{[a-z0-9]+}}
> -
> -
> -define zeroext i8 @rorbyte(i32 %nBits_arg, i8 %x_arg) nounwind readnone {
> -entry:
> - %tmp1 = zext i8 %x_arg to i32
> - %tmp3 = lshr i32 %tmp1, %nBits_arg
> - %tmp8 = sub i32 8, %nBits_arg
> - %tmp10 = shl i32 %tmp1, %tmp8
> - %tmp11 = or i32 %tmp3, %tmp10
> - %tmp12 = trunc i32 %tmp11 to i8
> - ret i8 %tmp12
> -}
> -; CHECK: rorb %cl, %{{[a-z0-9]+}}
> -
> -define zeroext i16 @rolword(i32 %nBits_arg, i16 %x_arg) nounwind readnone {
> -entry:
> - %tmp1 = zext i16 %x_arg to i32
> - %tmp3 = shl i32 %tmp1, %nBits_arg
> - %tmp8 = sub i32 16, %nBits_arg
> - %tmp10 = lshr i32 %tmp1, %tmp8
> - %tmp11 = or i32 %tmp3, %tmp10
> - %tmp12 = trunc i32 %tmp11 to i16
> - ret i16 %tmp12
> -}
> -; CHECK: rolw %cl, %{{[a-z0-9]+}}
> -
> -define zeroext i16 @rorword(i32 %nBits_arg, i16 %x_arg) nounwind readnone {
> -entry:
> - %tmp1 = zext i16 %x_arg to i32
> - %tmp3 = lshr i32 %tmp1, %nBits_arg
> - %tmp8 = sub i32 16, %nBits_arg
> - %tmp10 = shl i32 %tmp1, %tmp8
> - %tmp11 = or i32 %tmp3, %tmp10
> - %tmp12 = trunc i32 %tmp11 to i16
> - ret i16 %tmp12
> -}
> -; CHECK: rorw %cl, %{{[a-z0-9]+}}
> -
> -define i64 @roldword(i64 %nBits_arg, i32 %x_arg) nounwind readnone {
> -entry:
> - %tmp1 = zext i32 %x_arg to i64
> - %tmp3 = shl i64 %tmp1, %nBits_arg
> - %tmp8 = sub i64 32, %nBits_arg
> - %tmp10 = lshr i64 %tmp1, %tmp8
> - %tmp11 = or i64 %tmp3, %tmp10
> - ret i64 %tmp11
> -}
> -; CHECK: roll %cl, %{{[a-z0-9]+}}
> -
> -define zeroext i64 @rordword(i64 %nBits_arg, i32 %x_arg) nounwind readnone {
> -entry:
> - %tmp1 = zext i32 %x_arg to i64
> - %tmp3 = lshr i64 %tmp1, %nBits_arg
> - %tmp8 = sub i64 32, %nBits_arg
> - %tmp10 = shl i64 %tmp1, %tmp8
> - %tmp11 = or i64 %tmp3, %tmp10
> - ret i64 %tmp11
> -}
> -; CHECK: rorl %cl, %{{[a-z0-9]+}}
>
>
> _______________________________________________
> llvm-branch-commits mailing list
> llvm-branch-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-branch-commits
More information about the llvm-branch-commits
mailing list