[llvm-branch-commits] [llvm-branch] r166695 - in /llvm/branches/R600/lib/Target/AMDGPU: AMDGPUInstructions.td SIISelLowering.cpp SIInstrFormats.td SIInstrInfo.td SIInstructions.td SIRegisterInfo.td
Tom Stellard
thomas.stellard at amd.com
Thu Oct 25 10:08:44 PDT 2012
Author: tstellar
Date: Thu Oct 25 12:08:43 2012
New Revision: 166695
URL: http://llvm.org/viewvc/llvm-project?rev=166695&view=rev
Log:
SI: Use 64-bit encoding for V_CMP instructions
The 64-bit encoding allows V_CMP instructions to write to any SGPR
rather than just VCC.
Patch by: Michel Dänzer
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Modified:
llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td
llvm/branches/R600/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/branches/R600/lib/Target/AMDGPU/SIInstrFormats.td
llvm/branches/R600/lib/Target/AMDGPU/SIInstrInfo.td
llvm/branches/R600/lib/Target/AMDGPU/SIInstructions.td
llvm/branches/R600/lib/Target/AMDGPU/SIRegisterInfo.td
Modified: llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=166695&r1=166694&r2=166695&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/AMDGPUInstructions.td Thu Oct 25 12:08:43 2012
@@ -33,6 +33,8 @@
}
+def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
+
def COND_EQ : PatLeaf <
(cond),
[{switch(N->get()){{default: return false;
Modified: llvm/branches/R600/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/SIISelLowering.cpp?rev=166695&r1=166694&r2=166695&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/SIISelLowering.cpp Thu Oct 25 12:08:43 2012
@@ -254,16 +254,19 @@
void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const
{
- BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_GT_F32_e32),
- AMDGPU::VCC)
+ unsigned VCC = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
+
+ BuildMI(BB, I, BB.findDebugLoc(I),
+ TII->get(AMDGPU::V_CMP_GT_F32_e32),
+ VCC)
.addReg(AMDGPU::SREG_LIT_0)
.addOperand(MI->getOperand(1));
- BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32))
+ BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32_e32))
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(3))
.addOperand(MI->getOperand(2))
- .addReg(AMDGPU::VCC);
+ .addReg(VCC);
MI->eraseFromParent();
}
Modified: llvm/branches/R600/lib/Target/AMDGPU/SIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/SIInstrFormats.td?rev=166695&r1=166694&r2=166695&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/SIInstrFormats.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/SIInstrFormats.td Thu Oct 25 12:08:43 2012
@@ -21,6 +21,18 @@
//
//===----------------------------------------------------------------------===//
+class VOP3b_2IN <bits<9> op, string opName, RegisterClass dstClass,
+ RegisterClass src0Class, RegisterClass src1Class,
+ list<dag> pattern>
+ : VOP3b <op, (outs dstClass:$vdst),
+ (ins src0Class:$src0, src1Class:$src1, InstFlag:$src2, InstFlag:$sdst,
+ InstFlag:$omod, InstFlag:$neg),
+ opName, pattern
+>;
+
+
+class VOP3_1_32 <bits<9> op, string opName, list<dag> pattern>
+ : VOP3b_2IN <op, opName, SReg_1, AllReg_32, VReg_32, pattern>;
class VOP3_32 <bits<9> op, string opName, list<dag> pattern>
: VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
@@ -42,7 +54,7 @@
: SOP2 <op, (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
class SOP2_VCC <bits<7> op, string opName, list<dag> pattern>
- : SOP2 <op, (outs VCCReg:$vcc), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
+ : SOP2 <op, (outs SReg_1:$vcc), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
string opName, list<dag> pattern> :
@@ -103,13 +115,16 @@
op, (ins arc:$src0, vrc:$src1), opName, pattern
>;
-multiclass VOPC_32 <bits<8> op, string opName, list<dag> pattern> {
+multiclass VOPC_32 <bits<9> op, string opName, list<dag> pattern> {
- def _e32 : VOPC_Helper <op, VReg_32, AllReg_32, opName, pattern>;
+ def _e32 : VOPC_Helper <
+ {op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
+ VReg_32, AllReg_32, opName, pattern
+ >;
- def _e64 : VOP3_32 <
- {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
- opName, []
+ def _e64 : VOP3_1_32 <
+ op,
+ opName, pattern
>;
}
Modified: llvm/branches/R600/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/SIInstrInfo.td?rev=166695&r1=166694&r2=166695&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/SIInstrInfo.td Thu Oct 25 12:08:43 2012
@@ -19,6 +19,16 @@
//===----------------------------------------------------------------------===//
// and operation on 64-bit wide vcc
+def SIsreg1_and : SDNode<"SIISD::VCC_AND", SDTVCCBinaryOp,
+ [SDNPCommutative, SDNPAssociative]
+>;
+
+// Special bitcast node for sharing VCC register between VALU and SALU
+def SIsreg1_bitcast : SDNode<"SIISD::VCC_BITCAST",
+ SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>
+>;
+
+// and operation on 64-bit wide vcc
def SIvcc_and : SDNode<"SIISD::VCC_AND", SDTVCCBinaryOp,
[SDNPCommutative, SDNPAssociative]
>;
@@ -453,6 +463,35 @@
let hasSideEffects = 0;
}
+class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
+ Enc64 <outs, ins, asm, pattern> {
+
+ bits<8> VDST;
+ bits<9> SRC0;
+ bits<9> SRC1;
+ bits<9> SRC2;
+ bits<7> SDST;
+ bits<2> OMOD;
+ bits<3> NEG;
+
+ let Inst{7-0} = VDST;
+ let Inst{14-8} = SDST;
+ let Inst{25-17} = op;
+ let Inst{31-26} = 0x34; //encoding
+ let Inst{40-32} = SRC0;
+ let Inst{49-41} = SRC1;
+ let Inst{58-50} = SRC2;
+ let Inst{60-59} = OMOD;
+ let Inst{63-61} = NEG;
+
+ let EncodingType = 14; // SIInstrEncodingType::VOP3
+ let PostEncoderMethod = "VOPPostEncode";
+
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 0;
+}
+
class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
Modified: llvm/branches/R600/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/SIInstructions.td?rev=166695&r1=166694&r2=166695&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/SIInstructions.td Thu Oct 25 12:08:43 2012
@@ -107,23 +107,35 @@
//def EXP : EXP_ <0x00000000, "EXP", []>;
defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32", []>;
-defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32",
- [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_LT))]
+defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", []>;
+def : Pat <
+ (i1 (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_LT)),
+ (V_CMP_LT_F32_e64 AllReg_32:$src0, VReg_32:$src1)
>;
-defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32",
- [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_EQ))]
+defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", []>;
+def : Pat <
+ (i1 (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_EQ)),
+ (V_CMP_EQ_F32_e64 AllReg_32:$src0, VReg_32:$src1)
>;
-defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32",
- [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_LE))]
+defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", []>;
+def : Pat <
+ (i1 (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_LE)),
+ (V_CMP_LE_F32_e64 AllReg_32:$src0, VReg_32:$src1)
>;
-defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32",
- [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_GT))]
+defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", []>;
+def : Pat <
+ (i1 (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_GT)),
+ (V_CMP_GT_F32_e64 AllReg_32:$src0, VReg_32:$src1)
>;
-defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32",
- [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_NE))]
+defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32", []>;
+def : Pat <
+ (i1 (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_NE)),
+ (V_CMP_LG_F32_e64 AllReg_32:$src0, VReg_32:$src1)
>;
-defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32",
- [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_GE))]
+defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", []>;
+def : Pat <
+ (i1 (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_GE)),
+ (V_CMP_GE_F32_e64 AllReg_32:$src0, VReg_32:$src1)
>;
defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", []>;
defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", []>;
@@ -131,8 +143,10 @@
defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32", []>;
defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32", []>;
defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32", []>;
-defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32",
- [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_NE))]
+defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", []>;
+def : Pat <
+ (i1 (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_NE)),
+ (V_CMP_NEQ_F32_e64 AllReg_32:$src0, VReg_32:$src1)
>;
defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32", []>;
defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32", []>;
@@ -263,23 +277,35 @@
defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64", []>;
defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64", []>;
defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32", []>;
-defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32",
- [(set VCCReg:$dst, (setcc (i32 AllReg_32:$src0), VReg_32:$src1, SETLT))]
+defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", []>;
+def : Pat <
+ (i1 (setcc (i32 AllReg_32:$src0), VReg_32:$src1, COND_LT)),
+ (V_CMP_LT_I32_e64 AllReg_32:$src0, VReg_32:$src1)
>;
-defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32",
- [(set VCCReg:$dst, (setcc (i32 AllReg_32:$src0), VReg_32:$src1, SETEQ))]
+defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", []>;
+def : Pat <
+ (i1 (setcc (i32 AllReg_32:$src0), VReg_32:$src1, COND_EQ)),
+ (V_CMP_EQ_I32_e64 AllReg_32:$src0, VReg_32:$src1)
>;
-defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32",
- [(set VCCReg:$dst, (setcc (i32 AllReg_32:$src0), VReg_32:$src1, SETLE))]
+defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", []>;
+def : Pat <
+ (i1 (setcc (i32 AllReg_32:$src0), VReg_32:$src1, COND_LE)),
+ (V_CMP_LE_I32_e64 AllReg_32:$src0, VReg_32:$src1)
>;
-defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32",
- [(set VCCReg:$dst, (setcc (i32 AllReg_32:$src0), VReg_32:$src1, SETGT))]
+defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", []>;
+def : Pat <
+ (i1 (setcc (i32 AllReg_32:$src0), VReg_32:$src1, COND_GT)),
+ (V_CMP_GT_I32_e64 AllReg_32:$src0, VReg_32:$src1)
>;
-defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32",
- [(set VCCReg:$dst, (setcc (i32 AllReg_32:$src0), VReg_32:$src1, SETNE))]
+defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", []>;
+def : Pat <
+ (i1 (setcc (i32 AllReg_32:$src0), VReg_32:$src1, COND_NE)),
+ (V_CMP_NE_I32_e64 AllReg_32:$src0, VReg_32:$src1)
>;
-defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32",
- [(set VCCReg:$dst, (setcc (i32 AllReg_32:$src0), VReg_32:$src1, SETGE))]
+defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", []>;
+def : Pat <
+ (i1 (setcc (i32 AllReg_32:$src0), VReg_32:$src1, COND_GE)),
+ (V_CMP_GE_I32_e64 AllReg_32:$src0, VReg_32:$src1)
>;
defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32", []>;
@@ -720,31 +746,38 @@
//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>;
//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>;
-/* XXX: No VOP3 version of this instruction yet */
-def V_CNDMASK_B32 : VOP2 <0x00000000, (outs VReg_32:$dst),
- (ins AllReg_32:$src0, VReg_32:$src1, VCCReg:$vcc), "V_CNDMASK_B32",
- [(set (i32 VReg_32:$dst),
- (select VCCReg:$vcc, VReg_32:$src1, AllReg_32:$src0))] > {
-
+def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
+ (ins AllReg_32:$src0, VReg_32:$src1, VCCReg:$vcc), "V_CNDMASK_B32_e32",
+ []
+>{
let DisableEncoding = "$vcc";
}
-//f32 pattern for V_CNDMASK_B32
+def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
+ (ins AllReg_32:$src0, AllReg_32:$src1, SReg_1:$src2, InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
+ "V_CNDMASK_B32_e64",
+ [(set (i32 VReg_32:$dst), (select SReg_1:$src2, AllReg_32:$src1, AllReg_32:$src0))]
+>;
+
+//f32 pattern for V_CNDMASK_B32_e64
def : Pat <
- (f32 (select VCCReg:$vcc, VReg_32:$src0, AllReg_32:$src1)),
- (V_CNDMASK_B32 AllReg_32:$src1, VReg_32:$src0, VCCReg:$vcc)
+ (f32 (select SReg_1:$src2, AllReg_32:$src1, AllReg_32:$src0)),
+ (V_CNDMASK_B32_e64 AllReg_32:$src0, AllReg_32:$src1, SReg_1:$src2)
>;
defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>;
defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>;
-defm V_ADD_F32 : VOP2_32 <
- 0x00000003, "V_ADD_F32",
- [(set VReg_32:$dst, (fadd AllReg_32:$src0, VReg_32:$src1))]
+defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", []>;
+def : Pat <
+ (f32 (fadd AllReg_32:$src0, VReg_32:$src1)),
+ (V_ADD_F32_e32 AllReg_32:$src0, VReg_32:$src1)
>;
-defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32",
- [(set VReg_32:$dst, (fsub AllReg_32:$src0, VReg_32:$src1))]
+defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", []>;
+def : Pat <
+ (f32 (fsub AllReg_32:$src0, VReg_32:$src1)),
+ (V_SUB_F32_e32 AllReg_32:$src0, VReg_32:$src1)
>;
defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", []>;
defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>;
@@ -922,7 +955,7 @@
[(set SReg_64:$dst, (and SReg_64:$src0, SReg_64:$src1))]
>;
def S_AND_VCC : SOP2_VCC <0x0000000f, "S_AND_B64",
- [(set VCCReg:$vcc, (SIvcc_and SReg_64:$src0, SReg_64:$src1))]
+ [(set SReg_1:$vcc, (SIvcc_and SReg_64:$src0, SReg_64:$src1))]
>;
def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>;
def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>;
@@ -1122,6 +1155,16 @@
def : BitConvert <f32, i32, VReg_32>;
def : Pat <
+ (i64 (SIsreg1_bitcast SReg_1:$vcc)),
+ (S_MOV_B64 (COPY_TO_REGCLASS SReg_1:$vcc, SReg_64))
+>;
+
+def : Pat <
+ (i1 (SIsreg1_bitcast SReg_64:$vcc)),
+ (COPY_TO_REGCLASS SReg_64:$vcc, SReg_1)
+>;
+
+def : Pat <
(i64 (SIvcc_bitcast VCCReg:$vcc)),
(S_MOV_B64 (COPY_TO_REGCLASS VCCReg:$vcc, SReg_64))
>;
Modified: llvm/branches/R600/lib/Target/AMDGPU/SIRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/SIRegisterInfo.td?rev=166695&r1=166694&r2=166695&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/SIRegisterInfo.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/SIRegisterInfo.td Thu Oct 25 12:08:43 2012
@@ -122,6 +122,8 @@
def SReg_64 : RegisterClass<"AMDGPU", [i64], 64, (add SGPR_64, VCC, EXEC)>;
+def SReg_1 : RegisterClass<"AMDGPU", [i1], 1, (add VCC, SGPR_64, EXEC)>;
+
def SReg_128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add SGPR_128)>;
def SReg_256 : RegisterClass<"AMDGPU", [v8i32], 256, (add SGPR_256)>;
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