[llvm-branch-commits] [llvm-branch] r165748 [2/2] - in /llvm/branches/R600: ./ bindings/ocaml/executionengine/ bindings/ocaml/llvm/ bindings/ocaml/target/ cmake/modules/ docs/ docs/tutorial/ examples/ExceptionDemo/ examples/Kaleidoscope/Chapter4/ examples/Kaleidoscope/Chapter5/ examples/Kaleidoscope/Chapter6/ examples/Kaleidoscope/Chapter7/ examples/OCaml-Kaleidoscope/Chapter4/ examples/OCaml-Kaleidoscope/Chapter5/ examples/OCaml-Kaleidoscope/Chapter6/ examples/OCaml-Kaleidoscope/Chapter7/ include/llvm-c/ include/llvm/ includ...
Tom Stellard
thomas.stellard at amd.com
Thu Oct 11 14:28:03 PDT 2012
Modified: llvm/branches/R600/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp (original)
+++ llvm/branches/R600/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Thu Oct 11 16:28:00 2012
@@ -136,21 +136,21 @@
void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
- char Value = MI->getOperand(OpNo).getImm();
+ int Value = MI->getOperand(OpNo).getImm();
Value = SignExtend32<5>(Value);
O << (int)Value;
}
void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
- unsigned char Value = MI->getOperand(OpNo).getImm();
+ unsigned int Value = MI->getOperand(OpNo).getImm();
assert(Value <= 31 && "Invalid u5imm argument!");
O << (unsigned int)Value;
}
void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
- unsigned char Value = MI->getOperand(OpNo).getImm();
+ unsigned int Value = MI->getOperand(OpNo).getImm();
assert(Value <= 63 && "Invalid u6imm argument!");
O << (unsigned int)Value;
}
Modified: llvm/branches/R600/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp (original)
+++ llvm/branches/R600/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp Thu Oct 11 16:28:00 2012
@@ -168,7 +168,9 @@
get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpNo);
- assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
+ assert((MI.getOpcode() == PPC::MTCRF ||
+ MI.getOpcode() == PPC::MFOCRF ||
+ MI.getOpcode() == PPC::MTCRF8) &&
(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
return 0x80 >> getPPCRegisterNumbering(MO.getReg());
}
Modified: llvm/branches/R600/lib/Target/PowerPC/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
+++ llvm/branches/R600/lib/Target/PowerPC/PPCAsmPrinter.cpp Thu Oct 11 16:28:00 2012
@@ -437,7 +437,7 @@
bool PPCLinuxAsmPrinter::doFinalization(Module &M) {
- const TargetData *TD = TM.getTargetData();
+ const DataLayout *TD = TM.getDataLayout();
bool isPPC64 = TD->getPointerSizeInBits() == 64;
@@ -545,7 +545,7 @@
void PPCDarwinAsmPrinter::
EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs) {
- bool isPPC64 = TM.getTargetData()->getPointerSizeInBits() == 64;
+ bool isPPC64 = TM.getDataLayout()->getPointerSizeInBits() == 64;
const TargetLoweringObjectFileMachO &TLOFMacho =
static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
@@ -640,7 +640,7 @@
bool PPCDarwinAsmPrinter::doFinalization(Module &M) {
- bool isPPC64 = TM.getTargetData()->getPointerSizeInBits() == 64;
+ bool isPPC64 = TM.getDataLayout()->getPointerSizeInBits() == 64;
// Darwin/PPC always uses mach-o.
const TargetLoweringObjectFileMachO &TLOFMacho =
Modified: llvm/branches/R600/lib/Target/PowerPC/PPCFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/PPCFrameLowering.cpp (original)
+++ llvm/branches/R600/lib/Target/PowerPC/PPCFrameLowering.cpp Thu Oct 11 16:28:00 2012
@@ -193,7 +193,8 @@
// to adjust the stack pointer (we fit in the Red Zone). For 64-bit
// SVR4, we also require a stack frame if we need to spill the CR,
// since this spill area is addressed relative to the stack pointer.
- bool DisableRedZone = MF.getFunction()->getFnAttributes().hasNoRedZoneAttr();
+ bool DisableRedZone = MF.getFunction()->getFnAttributes().
+ hasAttribute(Attributes::NoRedZone);
// FIXME SVR4 The 32-bit SVR4 ABI has no red zone. However, it can
// still generate stackless code if all local vars are reg-allocated.
// Try: (FrameSize <= 224
@@ -255,7 +256,7 @@
// Naked functions have no stack frame pushed, so we don't have a frame
// pointer.
- if (MF.getFunction()->getFnAttributes().hasNakedAttr())
+ if (MF.getFunction()->getFnAttributes().hasAttribute(Attributes::Naked))
return false;
return MF.getTarget().Options.DisableFramePointerElim(MF) ||
Modified: llvm/branches/R600/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/branches/R600/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Oct 11 16:28:00 2012
@@ -701,10 +701,29 @@
}
}
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+
+ // Altivec Vector compare instructions do not set any CR register by default
+ if (LHS.getValueType().isVector()) {
+ unsigned int Opc;
+ if (LHS.getValueType() == MVT::v16i8)
+ Opc = PPC::VCMPEQUB;
+ else if (LHS.getValueType() == MVT::v4i32)
+ Opc = PPC::VCMPEQUW;
+ else if (LHS.getValueType() == MVT::v8i16)
+ Opc = PPC::VCMPEQUH;
+ else if (LHS.getValueType() == MVT::v4f32)
+ Opc = PPC::VCMPEQFP;
+ else
+ llvm_unreachable("Invalid vector compare type: should be expanded by legalize");
+ return CurDAG->SelectNodeTo(N, Opc, LHS.getValueType(), LHS, RHS);
+ }
+
bool Inv;
int OtherCondIdx;
unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
- SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
+ SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
SDValue IntCR;
// Force the ccreg into CR7.
@@ -717,7 +736,7 @@
if (PPCSubTarget.hasMFOCRF() && OtherCondIdx == -1)
IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
CCReg), 0);
- else
+ else
IntCR = SDValue(CurDAG->getMachineNode(PPC::MFCRpseud, dl, MVT::i32,
CR7Reg, CCReg), 0);
Modified: llvm/branches/R600/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/PPCISelLowering.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/R600/lib/Target/PowerPC/PPCISelLowering.cpp Thu Oct 11 16:28:00 2012
@@ -373,6 +373,10 @@
setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
setOperationAction(ISD::STORE , MVT::v4i32, Legal);
+ setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
+ setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
+ setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
+ setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
@@ -538,7 +542,9 @@
}
EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
- return MVT::i32;
+ if (!VT.isVector())
+ return MVT::i32;
+ return VT.changeVectorElementTypeToInteger();
}
//===----------------------------------------------------------------------===//
@@ -1493,7 +1499,7 @@
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = (PtrVT == MVT::i64);
Type *IntPtrTy =
- DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(
+ DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
*DAG.getContext());
TargetLowering::ArgListTy Args;
@@ -1716,12 +1722,16 @@
DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals)
const {
- if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
- return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
- dl, DAG, InVals);
+ if (PPCSubTarget.isSVR4ABI()) {
+ if (PPCSubTarget.isPPC64())
+ return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
+ dl, DAG, InVals);
+ else
+ return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
+ dl, DAG, InVals);
} else {
- return LowerFormalArguments_Darwin_Or_64SVR4(Chain, CallConv, isVarArg, Ins,
- dl, DAG, InVals);
+ return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
+ dl, DAG, InVals);
}
}
@@ -1944,7 +1954,295 @@
}
SDValue
-PPCTargetLowering::LowerFormalArguments_Darwin_Or_64SVR4(
+PPCTargetLowering::LowerFormalArguments_64SVR4(
+ SDValue Chain,
+ CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<ISD::InputArg>
+ &Ins,
+ DebugLoc dl, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals) const {
+ // TODO: add description of PPC stack frame format, or at least some docs.
+ //
+ MachineFunction &MF = DAG.getMachineFunction();
+ MachineFrameInfo *MFI = MF.getFrameInfo();
+ PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
+
+ EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
+ // Potential tail calls could cause overwriting of argument stack slots.
+ bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
+ (CallConv == CallingConv::Fast));
+ unsigned PtrByteSize = 8;
+
+ unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
+ // Area that is at least reserved in caller of this function.
+ unsigned MinReservedArea = ArgOffset;
+
+ static const uint16_t GPR[] = {
+ PPC::X3, PPC::X4, PPC::X5, PPC::X6,
+ PPC::X7, PPC::X8, PPC::X9, PPC::X10,
+ };
+
+ static const uint16_t *FPR = GetFPR();
+
+ static const uint16_t VR[] = {
+ PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
+ PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
+ };
+
+ const unsigned Num_GPR_Regs = array_lengthof(GPR);
+ const unsigned Num_FPR_Regs = 13;
+ const unsigned Num_VR_Regs = array_lengthof(VR);
+
+ unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
+
+ // Add DAG nodes to load the arguments or copy them out of registers. On
+ // entry to a function on PPC, the arguments start after the linkage area,
+ // although the first ones are often in registers.
+
+ SmallVector<SDValue, 8> MemOps;
+ unsigned nAltivecParamsAtEnd = 0;
+ Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
+ for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) {
+ SDValue ArgVal;
+ bool needsLoad = false;
+ EVT ObjectVT = Ins[ArgNo].VT;
+ unsigned ObjSize = ObjectVT.getSizeInBits()/8;
+ unsigned ArgSize = ObjSize;
+ ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
+
+ unsigned CurArgOffset = ArgOffset;
+
+ // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
+ if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
+ ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
+ if (isVarArg) {
+ MinReservedArea = ((MinReservedArea+15)/16)*16;
+ MinReservedArea += CalculateStackSlotSize(ObjectVT,
+ Flags,
+ PtrByteSize);
+ } else
+ nAltivecParamsAtEnd++;
+ } else
+ // Calculate min reserved area.
+ MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
+ Flags,
+ PtrByteSize);
+
+ // FIXME the codegen can be much improved in some cases.
+ // We do not have to keep everything in memory.
+ if (Flags.isByVal()) {
+ // ObjSize is the true size, ArgSize rounded up to multiple of registers.
+ ObjSize = Flags.getByValSize();
+ ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
+ // All aggregates smaller than 8 bytes must be passed right-justified.
+ if (ObjSize==1 || ObjSize==2) {
+ CurArgOffset = CurArgOffset + (4 - ObjSize);
+ }
+ // The value of the object is its address.
+ int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
+ SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
+ InVals.push_back(FIN);
+ if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
+ if (GPR_idx != Num_GPR_Regs) {
+ unsigned VReg;
+ VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
+ EVT ObjType = (ObjSize == 1 ? MVT::i8 :
+ (ObjSize == 2 ? MVT::i16 : MVT::i32));
+ SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
+ MachinePointerInfo(FuncArg,
+ CurArgOffset),
+ ObjType, false, false, 0);
+ MemOps.push_back(Store);
+ ++GPR_idx;
+ }
+
+ ArgOffset += PtrByteSize;
+
+ continue;
+ }
+ for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
+ // Store whatever pieces of the object are in registers
+ // to memory. ArgOffset will be the address of the beginning
+ // of the object.
+ if (GPR_idx != Num_GPR_Regs) {
+ unsigned VReg;
+ VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
+ int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
+ SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
+ SDValue Shifted = Val;
+
+ // For 64-bit SVR4, small structs come in right-adjusted.
+ // Shift them left so the following logic works as expected.
+ if (ObjSize < 8) {
+ SDValue ShiftAmt = DAG.getConstant(64 - 8 * ObjSize, PtrVT);
+ Shifted = DAG.getNode(ISD::SHL, dl, PtrVT, Val, ShiftAmt);
+ }
+
+ SDValue Store = DAG.getStore(Val.getValue(1), dl, Shifted, FIN,
+ MachinePointerInfo(FuncArg, ArgOffset),
+ false, false, 0);
+ MemOps.push_back(Store);
+ ++GPR_idx;
+ ArgOffset += PtrByteSize;
+ } else {
+ ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
+ break;
+ }
+ }
+ continue;
+ }
+
+ switch (ObjectVT.getSimpleVT().SimpleTy) {
+ default: llvm_unreachable("Unhandled argument type!");
+ case MVT::i32:
+ case MVT::i64:
+ if (GPR_idx != Num_GPR_Regs) {
+ unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
+ ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
+
+ if (ObjectVT == MVT::i32) {
+ // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
+ // value to MVT::i64 and then truncate to the correct register size.
+ if (Flags.isSExt())
+ ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
+ DAG.getValueType(ObjectVT));
+ else if (Flags.isZExt())
+ ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
+ DAG.getValueType(ObjectVT));
+
+ ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
+ }
+
+ ++GPR_idx;
+ } else {
+ needsLoad = true;
+ ArgSize = PtrByteSize;
+ }
+ ArgOffset += 8;
+ break;
+
+ case MVT::f32:
+ case MVT::f64:
+ // Every 8 bytes of argument space consumes one of the GPRs available for
+ // argument passing.
+ if (GPR_idx != Num_GPR_Regs) {
+ ++GPR_idx;
+ }
+ if (FPR_idx != Num_FPR_Regs) {
+ unsigned VReg;
+
+ if (ObjectVT == MVT::f32)
+ VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
+ else
+ VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
+
+ ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
+ ++FPR_idx;
+ } else {
+ needsLoad = true;
+ }
+
+ ArgOffset += 8;
+ break;
+ case MVT::v4f32:
+ case MVT::v4i32:
+ case MVT::v8i16:
+ case MVT::v16i8:
+ // Note that vector arguments in registers don't reserve stack space,
+ // except in varargs functions.
+ if (VR_idx != Num_VR_Regs) {
+ unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
+ ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
+ if (isVarArg) {
+ while ((ArgOffset % 16) != 0) {
+ ArgOffset += PtrByteSize;
+ if (GPR_idx != Num_GPR_Regs)
+ GPR_idx++;
+ }
+ ArgOffset += 16;
+ GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
+ }
+ ++VR_idx;
+ } else {
+ // Vectors are aligned.
+ ArgOffset = ((ArgOffset+15)/16)*16;
+ CurArgOffset = ArgOffset;
+ ArgOffset += 16;
+ needsLoad = true;
+ }
+ break;
+ }
+
+ // We need to load the argument to a virtual register if we determined
+ // above that we ran out of physical registers of the appropriate type.
+ if (needsLoad) {
+ int FI = MFI->CreateFixedObject(ObjSize,
+ CurArgOffset + (ArgSize - ObjSize),
+ isImmutable);
+ SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
+ ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
+ false, false, false, 0);
+ }
+
+ InVals.push_back(ArgVal);
+ }
+
+ // Set the size that is at least reserved in caller of this function. Tail
+ // call optimized function's reserved stack space needs to be aligned so that
+ // taking the difference between two stack areas will result in an aligned
+ // stack.
+ PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
+ // Add the Altivec parameters at the end, if needed.
+ if (nAltivecParamsAtEnd) {
+ MinReservedArea = ((MinReservedArea+15)/16)*16;
+ MinReservedArea += 16*nAltivecParamsAtEnd;
+ }
+ MinReservedArea =
+ std::max(MinReservedArea,
+ PPCFrameLowering::getMinCallFrameSize(true, true));
+ unsigned TargetAlign
+ = DAG.getMachineFunction().getTarget().getFrameLowering()->
+ getStackAlignment();
+ unsigned AlignMask = TargetAlign-1;
+ MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
+ FI->setMinReservedArea(MinReservedArea);
+
+ // If the function takes variable number of arguments, make a frame index for
+ // the start of the first vararg value... for expansion of llvm.va_start.
+ if (isVarArg) {
+ int Depth = ArgOffset;
+
+ FuncInfo->setVarArgsFrameIndex(
+ MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
+ Depth, true));
+ SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
+
+ // If this function is vararg, store any remaining integer argument regs
+ // to their spots on the stack so that they may be loaded by deferencing the
+ // result of va_next.
+ for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
+ unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
+ SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
+ SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
+ MachinePointerInfo(), false, false, 0);
+ MemOps.push_back(Store);
+ // Increment the address by four for the next argument to store
+ SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
+ FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
+ }
+ }
+
+ if (!MemOps.empty())
+ Chain = DAG.getNode(ISD::TokenFactor, dl,
+ MVT::Other, &MemOps[0], MemOps.size());
+
+ return Chain;
+}
+
+SDValue
+PPCTargetLowering::LowerFormalArguments_Darwin(
SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg>
@@ -1959,7 +2257,6 @@
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
- bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
// Potential tail calls could cause overwriting of argument stack slots.
bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
(CallConv == CallingConv::Fast));
@@ -2080,11 +2377,8 @@
// ObjSize is the true size, ArgSize rounded up to multiple of registers.
ObjSize = Flags.getByValSize();
ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
- // FOR DARWIN: Objects of size 1 and 2 are right justified, everything
- // else is left justified. This means the memory address is adjusted
- // forwards.
- // FOR 64-BIT SVR4: All aggregates smaller than 8 bytes must be passed
- // right-justified.
+ // Objects of size 1 and 2 are right justified, everything else is
+ // left justified. This means the memory address is adjusted forwards.
if (ObjSize==1 || ObjSize==2) {
CurArgOffset = CurArgOffset + (4 - ObjSize);
}
@@ -2092,8 +2386,7 @@
int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
InVals.push_back(FIN);
- if (ObjSize==1 || ObjSize==2 ||
- (ObjSize==4 && isSVR4ABI)) {
+ if (ObjSize==1 || ObjSize==2) {
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg;
if (isPPC64)
@@ -2128,16 +2421,7 @@
int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
- SDValue Shifted = Val;
-
- // For 64-bit SVR4, small structs come in right-adjusted.
- // Shift them left so the following logic works as expected.
- if (ObjSize < 8 && isSVR4ABI) {
- SDValue ShiftAmt = DAG.getConstant(64 - 8 * ObjSize, PtrVT);
- Shifted = DAG.getNode(ISD::SHL, dl, PtrVT, Val, ShiftAmt);
- }
-
- SDValue Store = DAG.getStore(Val.getValue(1), dl, Shifted, FIN,
+ SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
MachinePointerInfo(FuncArg, ArgOffset),
false, false, 0);
MemOps.push_back(Store);
@@ -6002,7 +6286,8 @@
bool is31 = (getTargetMachine().Options.DisableFramePointerElim(MF) ||
MFI->hasVarSizedObjects()) &&
MFI->getStackSize() &&
- !MF.getFunction()->getFnAttributes().hasNakedAttr();
+ !MF.getFunction()->getFnAttributes().
+ hasAttribute(Attributes::Naked);
unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) :
(is31 ? PPC::R31 : PPC::R1);
SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
Modified: llvm/branches/R600/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/PPCISelLowering.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/branches/R600/lib/Target/PowerPC/PPCISelLowering.h Thu Oct 11 16:28:00 2012
@@ -467,7 +467,13 @@
DebugLoc dl, SelectionDAG &DAG) const;
SDValue
- LowerFormalArguments_Darwin_Or_64SVR4(SDValue Chain,
+ LowerFormalArguments_Darwin(SDValue Chain,
+ CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<ISD::InputArg> &Ins,
+ DebugLoc dl, SelectionDAG &DAG,
+ SmallVectorImpl<SDValue> &InVals) const;
+ SDValue
+ LowerFormalArguments_64SVR4(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG,
Modified: llvm/branches/R600/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/PPCInstr64Bit.td?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/branches/R600/lib/Target/PowerPC/PPCInstr64Bit.td Thu Oct 11 16:28:00 2012
@@ -63,7 +63,7 @@
//
let Defs = [LR8] in
- def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>,
+ def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
PPC970_Unit_BRU;
// Darwin ABI Calls.
@@ -141,31 +141,31 @@
let usesCustomInserter = 1 in {
let Defs = [CR0] in {
def ATOMIC_LOAD_ADD_I64 : Pseudo<
- (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
+ (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64",
[(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
def ATOMIC_LOAD_SUB_I64 : Pseudo<
- (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
+ (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64",
[(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>;
def ATOMIC_LOAD_OR_I64 : Pseudo<
- (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
+ (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64",
[(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>;
def ATOMIC_LOAD_XOR_I64 : Pseudo<
- (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
+ (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64",
[(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>;
def ATOMIC_LOAD_AND_I64 : Pseudo<
- (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
+ (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64",
[(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>;
def ATOMIC_LOAD_NAND_I64 : Pseudo<
- (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
+ (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64",
[(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>;
def ATOMIC_CMP_SWAP_I64 : Pseudo<
- (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "",
+ (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64",
[(set G8RC:$dst,
(atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
def ATOMIC_SWAP_I64 : Pseudo<
- (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "",
+ (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64",
[(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>;
}
}
@@ -247,7 +247,7 @@
PPC970_MicroCode, PPC970_Unit_CRU;
def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
- "", SprMFCR>,
+ "#MFCR8pseud", SprMFCR>,
PPC970_MicroCode, PPC970_Unit_CRU;
def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
@@ -278,7 +278,7 @@
// the POWER3.
let Defs = [X1], Uses = [X1] in
-def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"",
+def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8",
[(set G8RC:$result,
(PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
@@ -626,15 +626,15 @@
"ld $rD, $src", LdStLD,
[(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
- "",
+ "#LDtoc",
[(set G8RC:$rD,
(PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
- "",
+ "#LDtocJTI",
[(set G8RC:$rD,
(PPCtoc_entry tjumptable:$disp, G8RC:$reg))]>, isPPC64;
def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
- "",
+ "#LDtocCPT",
[(set G8RC:$rD,
(PPCtoc_entry tconstpool:$disp, G8RC:$reg))]>, isPPC64;
Modified: llvm/branches/R600/lib/Target/PowerPC/PPCInstrAltivec.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/PPCInstrAltivec.td?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/PPCInstrAltivec.td (original)
+++ llvm/branches/R600/lib/Target/PowerPC/PPCInstrAltivec.td Thu Oct 11 16:28:00 2012
@@ -340,6 +340,28 @@
"vctuxs $vD, $vB, $UIMM", VecFP,
[(set VRRC:$vD,
(int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>;
+
+// Defines with the UIM field set to 0 for floating-point
+// to integer (fp_to_sint/fp_to_uint) conversions and integer
+// to floating-point (sint_to_fp/uint_to_fp) conversions.
+let VA = 0 in {
+def VCFSX_0 : VXForm_1<842, (outs VRRC:$vD), (ins VRRC:$vB),
+ "vcfsx $vD, $vB, 0", VecFP,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcfsx VRRC:$vB, 0))]>;
+def VCTUXS_0 : VXForm_1<906, (outs VRRC:$vD), (ins VRRC:$vB),
+ "vctuxs $vD, $vB, 0", VecFP,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vctuxs VRRC:$vB, 0))]>;
+def VCFUX_0 : VXForm_1<778, (outs VRRC:$vD), (ins VRRC:$vB),
+ "vcfux $vD, $vB, 0", VecFP,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vcfux VRRC:$vB, 0))]>;
+def VCTSXS_0 : VXForm_1<970, (outs VRRC:$vD), (ins VRRC:$vB),
+ "vctsxs $vD, $vB, 0", VecFP,
+ [(set VRRC:$vD,
+ (int_ppc_altivec_vctsxs VRRC:$vB, 0))]>;
+}
def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>;
def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>;
@@ -689,3 +711,13 @@
(v8i16 (VSRAH VRRC:$vA, VRRC:$vB))>;
def : Pat<(v4i32 (sra (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))),
(v4i32 (VSRAW VRRC:$vA, VRRC:$vB))>;
+
+// Float to integer and integer to float conversions
+def : Pat<(v4i32 (fp_to_sint (v4f32 VRRC:$vA))),
+ (VCTSXS_0 VRRC:$vA)>;
+def : Pat<(v4i32 (fp_to_uint (v4f32 VRRC:$vA))),
+ (VCTUXS_0 VRRC:$vA)>;
+def : Pat<(v4f32 (sint_to_fp (v4i32 VRRC:$vA))),
+ (VCFSX_0 VRRC:$vA)>;
+def : Pat<(v4f32 (uint_to_fp (v4i32 VRRC:$vA))),
+ (VCFUX_0 VRRC:$vA)>;
Modified: llvm/branches/R600/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/PPCInstrInfo.td?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/branches/R600/lib/Target/PowerPC/PPCInstrInfo.td Thu Oct 11 16:28:00 2012
@@ -369,9 +369,9 @@
let hasCtrlDep = 1 in {
let Defs = [R1], Uses = [R1] in {
-def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "",
+def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
[(callseq_start timm:$amt)]>;
-def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "",
+def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
[(callseq_end timm:$amt1, timm:$amt2)]>;
}
@@ -380,7 +380,7 @@
}
let Defs = [R1], Uses = [R1] in
-def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
+def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC",
[(set GPRC:$result,
(PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
@@ -389,19 +389,19 @@
let usesCustomInserter = 1, // Expanded after instruction selection.
PPC970_Single = 1 in {
def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
- i32imm:$BROPC), "",
+ i32imm:$BROPC), "#SELECT_CC_I4",
[]>;
def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
- i32imm:$BROPC), "",
+ i32imm:$BROPC), "#SELECT_CC_I8",
[]>;
def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
- i32imm:$BROPC), "",
+ i32imm:$BROPC), "#SELECT_CC_F4",
[]>;
def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
- i32imm:$BROPC), "",
+ i32imm:$BROPC), "#SELECT_CC_F8",
[]>;
def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
- i32imm:$BROPC), "",
+ i32imm:$BROPC), "#SELECT_CC_VRRC",
[]>;
}
@@ -409,16 +409,16 @@
// scavenge a register for it.
let mayStore = 1 in
def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
- "", []>;
+ "#SPILL_CR", []>;
// RESTORE_CR - Indicate that we're restoring the CR register (previously
// spilled), so we'll need to scavenge a register for it.
let mayLoad = 1 in
def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
- "", []>;
+ "#RESTORE_CR", []>;
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
- let isReturn = 1, Uses = [LR, RM] in
+ let isCodeGenOnly = 1, isReturn = 1, Uses = [LR, RM] in
def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
"b${p:cc}lr ${p:reg}", BrB,
[(retflag)]>;
@@ -427,7 +427,7 @@
}
let Defs = [LR] in
- def MovePCtoLR : Pseudo<(outs), (ins), "", []>,
+ def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
PPC970_Unit_BRU;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
@@ -439,10 +439,11 @@
// BCC represents an arbitrary conditional branch on a predicate.
// FIXME: should be able to write a pattern for PPCcondbranch, but can't use
- // a two-value operand where a dag node expects two operands. :(
- def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
- "b${cond:cc} ${cond:reg}, $dst"
- /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
+ // a two-value operand where a dag node expects two operands. :(
+ let isCodeGenOnly = 1 in
+ def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst),
+ "b${cond:cc} ${cond:reg}, $dst"
+ /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
let Defs = [CTR], Uses = [CTR] in {
def BDZ : IForm_ext<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
@@ -564,81 +565,81 @@
let usesCustomInserter = 1 in {
let Defs = [CR0] in {
def ATOMIC_LOAD_ADD_I8 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8",
[(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_SUB_I8 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8",
[(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_AND_I8 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8",
[(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_OR_I8 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8",
[(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_XOR_I8 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8",
[(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_NAND_I8 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8",
[(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_ADD_I16 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16",
[(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_SUB_I16 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16",
[(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_AND_I16 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16",
[(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_OR_I16 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16",
[(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_XOR_I16 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16",
[(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_NAND_I16 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16",
[(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_ADD_I32 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32",
[(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_SUB_I32 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32",
[(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_AND_I32 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32",
[(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_OR_I32 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32",
[(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_XOR_I32 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32",
[(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_LOAD_NAND_I32 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32",
[(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
def ATOMIC_CMP_SWAP_I8 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8",
[(set GPRC:$dst,
(atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
def ATOMIC_CMP_SWAP_I16 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
[(set GPRC:$dst,
(atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
def ATOMIC_CMP_SWAP_I32 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
[(set GPRC:$dst,
(atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
def ATOMIC_SWAP_I8 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8",
[(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
def ATOMIC_SWAP_I16 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16",
[(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
def ATOMIC_SWAP_I32 : Pseudo<
- (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
+ (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32",
[(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
}
}
@@ -1207,7 +1208,7 @@
//
// FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
- "", SprMFCR>,
+ "#MFCRpseud", SprMFCR>,
PPC970_MicroCode, PPC970_Unit_CRU;
def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
Modified: llvm/branches/R600/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/branches/R600/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Oct 11 16:28:00 2012
@@ -596,7 +596,7 @@
// to Offset to get the correct offset.
// Naked functions have stack size 0, although getStackSize may not reflect that
// because we didn't call all the pieces that compute it for naked functions.
- if (!MF.getFunction()->getFnAttributes().hasNakedAttr())
+ if (!MF.getFunction()->getFnAttributes().hasAttribute(Attributes::Naked))
Offset += MFI->getStackSize();
// If we can, encode the offset directly into the instruction. If this is a
Modified: llvm/branches/R600/lib/Target/PowerPC/PPCSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/PPCSubtarget.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/PPCSubtarget.cpp (original)
+++ llvm/branches/R600/lib/Target/PowerPC/PPCSubtarget.cpp Thu Oct 11 16:28:00 2012
@@ -66,7 +66,7 @@
// Silently force 64-bit register use on ppc64.
Use64BitRegs = true;
}
-
+
// If the user requested use of 64-bit regs, but the cpu selected doesn't
// support it, ignore.
if (use64BitRegs() && !has64BitSupport())
Modified: llvm/branches/R600/lib/Target/PowerPC/PPCSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/PPCSubtarget.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/PPCSubtarget.h (original)
+++ llvm/branches/R600/lib/Target/PowerPC/PPCSubtarget.h Thu Oct 11 16:28:00 2012
@@ -108,9 +108,9 @@
/// selection.
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
- /// getTargetDataString - Return the pointer size and type alignment
+ /// getDataLayoutString - Return the pointer size and type alignment
/// properties of this subtarget.
- const char *getTargetDataString() const {
+ const char *getDataLayoutString() const {
// Note, the alignment values for f64 and i64 on ppc64 in Darwin
// documentation are wrong; these are correct (i.e. "what gcc does").
return isPPC64() ? "E-p:64:64-f64:64:64-i64:64:64-f128:64:128-n32:64"
Modified: llvm/branches/R600/lib/Target/PowerPC/PPCTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/PPCTargetMachine.cpp (original)
+++ llvm/branches/R600/lib/Target/PowerPC/PPCTargetMachine.cpp Thu Oct 11 16:28:00 2012
@@ -40,7 +40,7 @@
bool is64Bit)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS, is64Bit),
- DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
+ DL(Subtarget.getDataLayoutString()), InstrInfo(*this),
FrameLowering(Subtarget), JITInfo(*this, is64Bit),
TLInfo(*this), TSInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()) {
Modified: llvm/branches/R600/lib/Target/PowerPC/PPCTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/PowerPC/PPCTargetMachine.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/PowerPC/PPCTargetMachine.h (original)
+++ llvm/branches/R600/lib/Target/PowerPC/PPCTargetMachine.h Thu Oct 11 16:28:00 2012
@@ -21,7 +21,7 @@
#include "PPCISelLowering.h"
#include "PPCSelectionDAGInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
namespace llvm {
@@ -29,7 +29,7 @@
///
class PPCTargetMachine : public LLVMTargetMachine {
PPCSubtarget Subtarget;
- const TargetData DataLayout; // Calculates type size & alignment
+ const DataLayout DL; // Calculates type size & alignment
PPCInstrInfo InstrInfo;
PPCFrameLowering FrameLowering;
PPCJITInfo JITInfo;
@@ -58,7 +58,7 @@
return &InstrInfo.getRegisterInfo();
}
- virtual const TargetData *getTargetData() const { return &DataLayout; }
+ virtual const DataLayout *getDataLayout() const { return &DL; }
virtual const PPCSubtarget *getSubtargetImpl() const { return &Subtarget; }
virtual const InstrItineraryData *getInstrItineraryData() const {
return &InstrItins;
Modified: llvm/branches/R600/lib/Target/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/README.txt?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/README.txt (original)
+++ llvm/branches/R600/lib/Target/README.txt Thu Oct 11 16:28:00 2012
@@ -152,7 +152,7 @@
//===---------------------------------------------------------------------===//
-For vector types, TargetData.cpp::getTypeInfo() returns alignment that is equal
+For vector types, DataLayout.cpp::getTypeInfo() returns alignment that is equal
to the type size. It works but can be overly conservative as the alignment of
specific vector types are target dependent.
Modified: llvm/branches/R600/lib/Target/Sparc/SparcFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/Sparc/SparcFrameLowering.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/Sparc/SparcFrameLowering.cpp (original)
+++ llvm/branches/R600/lib/Target/Sparc/SparcFrameLowering.cpp Thu Oct 11 16:28:00 2012
@@ -20,7 +20,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/CommandLine.h"
Modified: llvm/branches/R600/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/Sparc/SparcISelLowering.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/branches/R600/lib/Target/Sparc/SparcISelLowering.cpp Thu Oct 11 16:28:00 2012
@@ -637,7 +637,7 @@
PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
Type *ElementTy = Ty->getElementType();
- return getTargetData()->getTypeAllocSize(ElementTy);
+ return getDataLayout()->getTypeAllocSize(ElementTy);
}
//===----------------------------------------------------------------------===//
Modified: llvm/branches/R600/lib/Target/Sparc/SparcTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/Sparc/SparcTargetMachine.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/Sparc/SparcTargetMachine.cpp (original)
+++ llvm/branches/R600/lib/Target/Sparc/SparcTargetMachine.cpp Thu Oct 11 16:28:00 2012
@@ -33,7 +33,7 @@
bool is64bit)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS, is64bit),
- DataLayout(Subtarget.getDataLayout()),
+ DL(Subtarget.getDataLayout()),
InstrInfo(Subtarget),
TLInfo(*this), TSInfo(*this),
FrameLowering(Subtarget) {
Modified: llvm/branches/R600/lib/Target/Sparc/SparcTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/Sparc/SparcTargetMachine.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/Sparc/SparcTargetMachine.h (original)
+++ llvm/branches/R600/lib/Target/Sparc/SparcTargetMachine.h Thu Oct 11 16:28:00 2012
@@ -20,14 +20,14 @@
#include "SparcSelectionDAGInfo.h"
#include "SparcSubtarget.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
class SparcTargetMachine : public LLVMTargetMachine {
SparcSubtarget Subtarget;
- const TargetData DataLayout; // Calculates type size & alignment
+ const DataLayout DL; // Calculates type size & alignment
SparcInstrInfo InstrInfo;
SparcTargetLowering TLInfo;
SparcSelectionDAGInfo TSInfo;
@@ -52,7 +52,7 @@
virtual const SparcSelectionDAGInfo* getSelectionDAGInfo() const {
return &TSInfo;
}
- virtual const TargetData *getTargetData() const { return &DataLayout; }
+ virtual const DataLayout *getDataLayout() const { return &DL; }
// Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
Modified: llvm/branches/R600/lib/Target/Target.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/Target.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/Target.cpp (original)
+++ llvm/branches/R600/lib/Target/Target.cpp Thu Oct 11 16:28:00 2012
@@ -16,7 +16,7 @@
#include "llvm-c/Initialization.h"
#include "llvm/InitializePasses.h"
#include "llvm/PassManager.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/LLVMContext.h"
#include <cstring>
@@ -24,7 +24,7 @@
using namespace llvm;
void llvm::initializeTarget(PassRegistry &Registry) {
- initializeTargetDataPass(Registry);
+ initializeDataLayoutPass(Registry);
initializeTargetLibraryInfoPass(Registry);
}
@@ -33,11 +33,11 @@
}
LLVMTargetDataRef LLVMCreateTargetData(const char *StringRep) {
- return wrap(new TargetData(StringRep));
+ return wrap(new DataLayout(StringRep));
}
void LLVMAddTargetData(LLVMTargetDataRef TD, LLVMPassManagerRef PM) {
- unwrap(PM)->add(new TargetData(*unwrap(TD)));
+ unwrap(PM)->add(new DataLayout(*unwrap(TD)));
}
void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef TLI,
Removed: llvm/branches/R600/lib/Target/TargetData.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/TargetData.cpp?rev=165747&view=auto
==============================================================================
--- llvm/branches/R600/lib/Target/TargetData.cpp (original)
+++ llvm/branches/R600/lib/Target/TargetData.cpp (removed)
@@ -1,665 +0,0 @@
-//===-- TargetData.cpp - Data size & alignment routines --------------------==//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines target properties related to datatype size/offset/alignment
-// information.
-//
-// This structure should be created once, filled in if the defaults are not
-// correct and then passed around by const&. None of the members functions
-// require modification to the object.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/Target/TargetData.h"
-#include "llvm/Constants.h"
-#include "llvm/DerivedTypes.h"
-#include "llvm/Module.h"
-#include "llvm/Support/GetElementPtrTypeIterator.h"
-#include "llvm/Support/MathExtras.h"
-#include "llvm/Support/ManagedStatic.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Support/Mutex.h"
-#include "llvm/ADT/DenseMap.h"
-#include <algorithm>
-#include <cstdlib>
-using namespace llvm;
-
-// Handle the Pass registration stuff necessary to use TargetData's.
-
-// Register the default SparcV9 implementation...
-INITIALIZE_PASS(TargetData, "targetdata", "Target Data Layout", false, true)
-char TargetData::ID = 0;
-
-//===----------------------------------------------------------------------===//
-// Support for StructLayout
-//===----------------------------------------------------------------------===//
-
-StructLayout::StructLayout(StructType *ST, const TargetData &TD) {
- assert(!ST->isOpaque() && "Cannot get layout of opaque structs");
- StructAlignment = 0;
- StructSize = 0;
- NumElements = ST->getNumElements();
-
- // Loop over each of the elements, placing them in memory.
- for (unsigned i = 0, e = NumElements; i != e; ++i) {
- Type *Ty = ST->getElementType(i);
- unsigned TyAlign = ST->isPacked() ? 1 : TD.getABITypeAlignment(Ty);
-
- // Add padding if necessary to align the data element properly.
- if ((StructSize & (TyAlign-1)) != 0)
- StructSize = TargetData::RoundUpAlignment(StructSize, TyAlign);
-
- // Keep track of maximum alignment constraint.
- StructAlignment = std::max(TyAlign, StructAlignment);
-
- MemberOffsets[i] = StructSize;
- StructSize += TD.getTypeAllocSize(Ty); // Consume space for this data item
- }
-
- // Empty structures have alignment of 1 byte.
- if (StructAlignment == 0) StructAlignment = 1;
-
- // Add padding to the end of the struct so that it could be put in an array
- // and all array elements would be aligned correctly.
- if ((StructSize & (StructAlignment-1)) != 0)
- StructSize = TargetData::RoundUpAlignment(StructSize, StructAlignment);
-}
-
-
-/// getElementContainingOffset - Given a valid offset into the structure,
-/// return the structure index that contains it.
-unsigned StructLayout::getElementContainingOffset(uint64_t Offset) const {
- const uint64_t *SI =
- std::upper_bound(&MemberOffsets[0], &MemberOffsets[NumElements], Offset);
- assert(SI != &MemberOffsets[0] && "Offset not in structure type!");
- --SI;
- assert(*SI <= Offset && "upper_bound didn't work");
- assert((SI == &MemberOffsets[0] || *(SI-1) <= Offset) &&
- (SI+1 == &MemberOffsets[NumElements] || *(SI+1) > Offset) &&
- "Upper bound didn't work!");
-
- // Multiple fields can have the same offset if any of them are zero sized.
- // For example, in { i32, [0 x i32], i32 }, searching for offset 4 will stop
- // at the i32 element, because it is the last element at that offset. This is
- // the right one to return, because anything after it will have a higher
- // offset, implying that this element is non-empty.
- return SI-&MemberOffsets[0];
-}
-
-//===----------------------------------------------------------------------===//
-// TargetAlignElem, TargetAlign support
-//===----------------------------------------------------------------------===//
-
-TargetAlignElem
-TargetAlignElem::get(AlignTypeEnum align_type, unsigned abi_align,
- unsigned pref_align, uint32_t bit_width) {
- assert(abi_align <= pref_align && "Preferred alignment worse than ABI!");
- TargetAlignElem retval;
- retval.AlignType = align_type;
- retval.ABIAlign = abi_align;
- retval.PrefAlign = pref_align;
- retval.TypeBitWidth = bit_width;
- return retval;
-}
-
-bool
-TargetAlignElem::operator==(const TargetAlignElem &rhs) const {
- return (AlignType == rhs.AlignType
- && ABIAlign == rhs.ABIAlign
- && PrefAlign == rhs.PrefAlign
- && TypeBitWidth == rhs.TypeBitWidth);
-}
-
-const TargetAlignElem
-TargetData::InvalidAlignmentElem = { (AlignTypeEnum)0xFF, 0, 0, 0 };
-
-//===----------------------------------------------------------------------===//
-// TargetData Class Implementation
-//===----------------------------------------------------------------------===//
-
-/// getInt - Get an integer ignoring errors.
-static int getInt(StringRef R) {
- int Result = 0;
- R.getAsInteger(10, Result);
- return Result;
-}
-
-void TargetData::init() {
- initializeTargetDataPass(*PassRegistry::getPassRegistry());
-
- LayoutMap = 0;
- LittleEndian = false;
- PointerMemSize = 8;
- PointerABIAlign = 8;
- PointerPrefAlign = PointerABIAlign;
- StackNaturalAlign = 0;
-
- // Default alignments
- setAlignment(INTEGER_ALIGN, 1, 1, 1); // i1
- setAlignment(INTEGER_ALIGN, 1, 1, 8); // i8
- setAlignment(INTEGER_ALIGN, 2, 2, 16); // i16
- setAlignment(INTEGER_ALIGN, 4, 4, 32); // i32
- setAlignment(INTEGER_ALIGN, 4, 8, 64); // i64
- setAlignment(FLOAT_ALIGN, 2, 2, 16); // half
- setAlignment(FLOAT_ALIGN, 4, 4, 32); // float
- setAlignment(FLOAT_ALIGN, 8, 8, 64); // double
- setAlignment(FLOAT_ALIGN, 16, 16, 128); // ppcf128, quad, ...
- setAlignment(VECTOR_ALIGN, 8, 8, 64); // v2i32, v1i64, ...
- setAlignment(VECTOR_ALIGN, 16, 16, 128); // v16i8, v8i16, v4i32, ...
- setAlignment(AGGREGATE_ALIGN, 0, 8, 0); // struct
-}
-
-std::string TargetData::parseSpecifier(StringRef Desc, TargetData *td) {
-
- if (td)
- td->init();
-
- while (!Desc.empty()) {
- std::pair<StringRef, StringRef> Split = Desc.split('-');
- StringRef Token = Split.first;
- Desc = Split.second;
-
- if (Token.empty())
- continue;
-
- Split = Token.split(':');
- StringRef Specifier = Split.first;
- Token = Split.second;
-
- assert(!Specifier.empty() && "Can't be empty here");
-
- switch (Specifier[0]) {
- case 'E':
- if (td)
- td->LittleEndian = false;
- break;
- case 'e':
- if (td)
- td->LittleEndian = true;
- break;
- case 'p': {
- // Pointer size.
- Split = Token.split(':');
- int PointerMemSizeBits = getInt(Split.first);
- if (PointerMemSizeBits < 0 || PointerMemSizeBits % 8 != 0)
- return "invalid pointer size, must be a positive 8-bit multiple";
- if (td)
- td->PointerMemSize = PointerMemSizeBits / 8;
-
- // Pointer ABI alignment.
- Split = Split.second.split(':');
- int PointerABIAlignBits = getInt(Split.first);
- if (PointerABIAlignBits < 0 || PointerABIAlignBits % 8 != 0) {
- return "invalid pointer ABI alignment, "
- "must be a positive 8-bit multiple";
- }
- if (td)
- td->PointerABIAlign = PointerABIAlignBits / 8;
-
- // Pointer preferred alignment.
- Split = Split.second.split(':');
- int PointerPrefAlignBits = getInt(Split.first);
- if (PointerPrefAlignBits < 0 || PointerPrefAlignBits % 8 != 0) {
- return "invalid pointer preferred alignment, "
- "must be a positive 8-bit multiple";
- }
- if (td) {
- td->PointerPrefAlign = PointerPrefAlignBits / 8;
- if (td->PointerPrefAlign == 0)
- td->PointerPrefAlign = td->PointerABIAlign;
- }
- break;
- }
- case 'i':
- case 'v':
- case 'f':
- case 'a':
- case 's': {
- AlignTypeEnum AlignType;
- char field = Specifier[0];
- switch (field) {
- default:
- case 'i': AlignType = INTEGER_ALIGN; break;
- case 'v': AlignType = VECTOR_ALIGN; break;
- case 'f': AlignType = FLOAT_ALIGN; break;
- case 'a': AlignType = AGGREGATE_ALIGN; break;
- case 's': AlignType = STACK_ALIGN; break;
- }
- int Size = getInt(Specifier.substr(1));
- if (Size < 0) {
- return std::string("invalid ") + field + "-size field, "
- "must be positive";
- }
-
- Split = Token.split(':');
- int ABIAlignBits = getInt(Split.first);
- if (ABIAlignBits < 0 || ABIAlignBits % 8 != 0) {
- return std::string("invalid ") + field +"-abi-alignment field, "
- "must be a positive 8-bit multiple";
- }
- unsigned ABIAlign = ABIAlignBits / 8;
-
- Split = Split.second.split(':');
-
- int PrefAlignBits = getInt(Split.first);
- if (PrefAlignBits < 0 || PrefAlignBits % 8 != 0) {
- return std::string("invalid ") + field +"-preferred-alignment field, "
- "must be a positive 8-bit multiple";
- }
- unsigned PrefAlign = PrefAlignBits / 8;
- if (PrefAlign == 0)
- PrefAlign = ABIAlign;
-
- if (td)
- td->setAlignment(AlignType, ABIAlign, PrefAlign, Size);
- break;
- }
- case 'n': // Native integer types.
- Specifier = Specifier.substr(1);
- do {
- int Width = getInt(Specifier);
- if (Width <= 0) {
- return std::string("invalid native integer size \'") + Specifier.str() +
- "\', must be a positive integer.";
- }
- if (td && Width != 0)
- td->LegalIntWidths.push_back(Width);
- Split = Token.split(':');
- Specifier = Split.first;
- Token = Split.second;
- } while (!Specifier.empty() || !Token.empty());
- break;
- case 'S': { // Stack natural alignment.
- int StackNaturalAlignBits = getInt(Specifier.substr(1));
- if (StackNaturalAlignBits < 0 || StackNaturalAlignBits % 8 != 0) {
- return "invalid natural stack alignment (S-field), "
- "must be a positive 8-bit multiple";
- }
- if (td)
- td->StackNaturalAlign = StackNaturalAlignBits / 8;
- break;
- }
- default:
- break;
- }
- }
-
- return "";
-}
-
-/// Default ctor.
-///
-/// @note This has to exist, because this is a pass, but it should never be
-/// used.
-TargetData::TargetData() : ImmutablePass(ID) {
- report_fatal_error("Bad TargetData ctor used. "
- "Tool did not specify a TargetData to use?");
-}
-
-TargetData::TargetData(const Module *M)
- : ImmutablePass(ID) {
- std::string errMsg = parseSpecifier(M->getDataLayout(), this);
- assert(errMsg == "" && "Module M has malformed target data layout string.");
- (void)errMsg;
-}
-
-void
-TargetData::setAlignment(AlignTypeEnum align_type, unsigned abi_align,
- unsigned pref_align, uint32_t bit_width) {
- assert(abi_align <= pref_align && "Preferred alignment worse than ABI!");
- assert(pref_align < (1 << 16) && "Alignment doesn't fit in bitfield");
- assert(bit_width < (1 << 24) && "Bit width doesn't fit in bitfield");
- for (unsigned i = 0, e = Alignments.size(); i != e; ++i) {
- if (Alignments[i].AlignType == align_type &&
- Alignments[i].TypeBitWidth == bit_width) {
- // Update the abi, preferred alignments.
- Alignments[i].ABIAlign = abi_align;
- Alignments[i].PrefAlign = pref_align;
- return;
- }
- }
-
- Alignments.push_back(TargetAlignElem::get(align_type, abi_align,
- pref_align, bit_width));
-}
-
-/// getAlignmentInfo - Return the alignment (either ABI if ABIInfo = true or
-/// preferred if ABIInfo = false) the target wants for the specified datatype.
-unsigned TargetData::getAlignmentInfo(AlignTypeEnum AlignType,
- uint32_t BitWidth, bool ABIInfo,
- Type *Ty) const {
- // Check to see if we have an exact match and remember the best match we see.
- int BestMatchIdx = -1;
- int LargestInt = -1;
- for (unsigned i = 0, e = Alignments.size(); i != e; ++i) {
- if (Alignments[i].AlignType == AlignType &&
- Alignments[i].TypeBitWidth == BitWidth)
- return ABIInfo ? Alignments[i].ABIAlign : Alignments[i].PrefAlign;
-
- // The best match so far depends on what we're looking for.
- if (AlignType == INTEGER_ALIGN &&
- Alignments[i].AlignType == INTEGER_ALIGN) {
- // The "best match" for integers is the smallest size that is larger than
- // the BitWidth requested.
- if (Alignments[i].TypeBitWidth > BitWidth && (BestMatchIdx == -1 ||
- Alignments[i].TypeBitWidth < Alignments[BestMatchIdx].TypeBitWidth))
- BestMatchIdx = i;
- // However, if there isn't one that's larger, then we must use the
- // largest one we have (see below)
- if (LargestInt == -1 ||
- Alignments[i].TypeBitWidth > Alignments[LargestInt].TypeBitWidth)
- LargestInt = i;
- }
- }
-
- // Okay, we didn't find an exact solution. Fall back here depending on what
- // is being looked for.
- if (BestMatchIdx == -1) {
- // If we didn't find an integer alignment, fall back on most conservative.
- if (AlignType == INTEGER_ALIGN) {
- BestMatchIdx = LargestInt;
- } else {
- assert(AlignType == VECTOR_ALIGN && "Unknown alignment type!");
-
- // By default, use natural alignment for vector types. This is consistent
- // with what clang and llvm-gcc do.
- unsigned Align = getTypeAllocSize(cast<VectorType>(Ty)->getElementType());
- Align *= cast<VectorType>(Ty)->getNumElements();
- // If the alignment is not a power of 2, round up to the next power of 2.
- // This happens for non-power-of-2 length vectors.
- if (Align & (Align-1))
- Align = NextPowerOf2(Align);
- return Align;
- }
- }
-
- // Since we got a "best match" index, just return it.
- return ABIInfo ? Alignments[BestMatchIdx].ABIAlign
- : Alignments[BestMatchIdx].PrefAlign;
-}
-
-namespace {
-
-class StructLayoutMap {
- typedef DenseMap<StructType*, StructLayout*> LayoutInfoTy;
- LayoutInfoTy LayoutInfo;
-
-public:
- virtual ~StructLayoutMap() {
- // Remove any layouts.
- for (LayoutInfoTy::iterator I = LayoutInfo.begin(), E = LayoutInfo.end();
- I != E; ++I) {
- StructLayout *Value = I->second;
- Value->~StructLayout();
- free(Value);
- }
- }
-
- StructLayout *&operator[](StructType *STy) {
- return LayoutInfo[STy];
- }
-
- // for debugging...
- virtual void dump() const {}
-};
-
-} // end anonymous namespace
-
-TargetData::~TargetData() {
- delete static_cast<StructLayoutMap*>(LayoutMap);
-}
-
-const StructLayout *TargetData::getStructLayout(StructType *Ty) const {
- if (!LayoutMap)
- LayoutMap = new StructLayoutMap();
-
- StructLayoutMap *STM = static_cast<StructLayoutMap*>(LayoutMap);
- StructLayout *&SL = (*STM)[Ty];
- if (SL) return SL;
-
- // Otherwise, create the struct layout. Because it is variable length, we
- // malloc it, then use placement new.
- int NumElts = Ty->getNumElements();
- StructLayout *L =
- (StructLayout *)malloc(sizeof(StructLayout)+(NumElts-1) * sizeof(uint64_t));
-
- // Set SL before calling StructLayout's ctor. The ctor could cause other
- // entries to be added to TheMap, invalidating our reference.
- SL = L;
-
- new (L) StructLayout(Ty, *this);
-
- return L;
-}
-
-std::string TargetData::getStringRepresentation() const {
- std::string Result;
- raw_string_ostream OS(Result);
-
- OS << (LittleEndian ? "e" : "E")
- << "-p:" << PointerMemSize*8 << ':' << PointerABIAlign*8
- << ':' << PointerPrefAlign*8
- << "-S" << StackNaturalAlign*8;
-
- for (unsigned i = 0, e = Alignments.size(); i != e; ++i) {
- const TargetAlignElem &AI = Alignments[i];
- OS << '-' << (char)AI.AlignType << AI.TypeBitWidth << ':'
- << AI.ABIAlign*8 << ':' << AI.PrefAlign*8;
- }
-
- if (!LegalIntWidths.empty()) {
- OS << "-n" << (unsigned)LegalIntWidths[0];
-
- for (unsigned i = 1, e = LegalIntWidths.size(); i != e; ++i)
- OS << ':' << (unsigned)LegalIntWidths[i];
- }
- return OS.str();
-}
-
-
-uint64_t TargetData::getTypeSizeInBits(Type *Ty) const {
- assert(Ty->isSized() && "Cannot getTypeInfo() on a type that is unsized!");
- switch (Ty->getTypeID()) {
- case Type::LabelTyID:
- case Type::PointerTyID:
- return getPointerSizeInBits();
- case Type::ArrayTyID: {
- ArrayType *ATy = cast<ArrayType>(Ty);
- return getTypeAllocSizeInBits(ATy->getElementType())*ATy->getNumElements();
- }
- case Type::StructTyID:
- // Get the layout annotation... which is lazily created on demand.
- return getStructLayout(cast<StructType>(Ty))->getSizeInBits();
- case Type::IntegerTyID:
- return cast<IntegerType>(Ty)->getBitWidth();
- case Type::VoidTyID:
- return 8;
- case Type::HalfTyID:
- return 16;
- case Type::FloatTyID:
- return 32;
- case Type::DoubleTyID:
- case Type::X86_MMXTyID:
- return 64;
- case Type::PPC_FP128TyID:
- case Type::FP128TyID:
- return 128;
- // In memory objects this is always aligned to a higher boundary, but
- // only 80 bits contain information.
- case Type::X86_FP80TyID:
- return 80;
- case Type::VectorTyID:
- return cast<VectorType>(Ty)->getBitWidth();
- default:
- llvm_unreachable("TargetData::getTypeSizeInBits(): Unsupported type");
- }
-}
-
-/*!
- \param abi_or_pref Flag that determines which alignment is returned. true
- returns the ABI alignment, false returns the preferred alignment.
- \param Ty The underlying type for which alignment is determined.
-
- Get the ABI (\a abi_or_pref == true) or preferred alignment (\a abi_or_pref
- == false) for the requested type \a Ty.
- */
-unsigned TargetData::getAlignment(Type *Ty, bool abi_or_pref) const {
- int AlignType = -1;
-
- assert(Ty->isSized() && "Cannot getTypeInfo() on a type that is unsized!");
- switch (Ty->getTypeID()) {
- // Early escape for the non-numeric types.
- case Type::LabelTyID:
- case Type::PointerTyID:
- return (abi_or_pref
- ? getPointerABIAlignment()
- : getPointerPrefAlignment());
- case Type::ArrayTyID:
- return getAlignment(cast<ArrayType>(Ty)->getElementType(), abi_or_pref);
-
- case Type::StructTyID: {
- // Packed structure types always have an ABI alignment of one.
- if (cast<StructType>(Ty)->isPacked() && abi_or_pref)
- return 1;
-
- // Get the layout annotation... which is lazily created on demand.
- const StructLayout *Layout = getStructLayout(cast<StructType>(Ty));
- unsigned Align = getAlignmentInfo(AGGREGATE_ALIGN, 0, abi_or_pref, Ty);
- return std::max(Align, Layout->getAlignment());
- }
- case Type::IntegerTyID:
- case Type::VoidTyID:
- AlignType = INTEGER_ALIGN;
- break;
- case Type::HalfTyID:
- case Type::FloatTyID:
- case Type::DoubleTyID:
- // PPC_FP128TyID and FP128TyID have different data contents, but the
- // same size and alignment, so they look the same here.
- case Type::PPC_FP128TyID:
- case Type::FP128TyID:
- case Type::X86_FP80TyID:
- AlignType = FLOAT_ALIGN;
- break;
- case Type::X86_MMXTyID:
- case Type::VectorTyID:
- AlignType = VECTOR_ALIGN;
- break;
- default:
- llvm_unreachable("Bad type for getAlignment!!!");
- }
-
- return getAlignmentInfo((AlignTypeEnum)AlignType, getTypeSizeInBits(Ty),
- abi_or_pref, Ty);
-}
-
-unsigned TargetData::getABITypeAlignment(Type *Ty) const {
- return getAlignment(Ty, true);
-}
-
-/// getABIIntegerTypeAlignment - Return the minimum ABI-required alignment for
-/// an integer type of the specified bitwidth.
-unsigned TargetData::getABIIntegerTypeAlignment(unsigned BitWidth) const {
- return getAlignmentInfo(INTEGER_ALIGN, BitWidth, true, 0);
-}
-
-
-unsigned TargetData::getCallFrameTypeAlignment(Type *Ty) const {
- for (unsigned i = 0, e = Alignments.size(); i != e; ++i)
- if (Alignments[i].AlignType == STACK_ALIGN)
- return Alignments[i].ABIAlign;
-
- return getABITypeAlignment(Ty);
-}
-
-unsigned TargetData::getPrefTypeAlignment(Type *Ty) const {
- return getAlignment(Ty, false);
-}
-
-unsigned TargetData::getPreferredTypeAlignmentShift(Type *Ty) const {
- unsigned Align = getPrefTypeAlignment(Ty);
- assert(!(Align & (Align-1)) && "Alignment is not a power of two!");
- return Log2_32(Align);
-}
-
-/// getIntPtrType - Return an unsigned integer type that is the same size or
-/// greater to the host pointer size.
-IntegerType *TargetData::getIntPtrType(LLVMContext &C) const {
- return IntegerType::get(C, getPointerSizeInBits());
-}
-
-
-uint64_t TargetData::getIndexedOffset(Type *ptrTy,
- ArrayRef<Value *> Indices) const {
- Type *Ty = ptrTy;
- assert(Ty->isPointerTy() && "Illegal argument for getIndexedOffset()");
- uint64_t Result = 0;
-
- generic_gep_type_iterator<Value* const*>
- TI = gep_type_begin(ptrTy, Indices);
- for (unsigned CurIDX = 0, EndIDX = Indices.size(); CurIDX != EndIDX;
- ++CurIDX, ++TI) {
- if (StructType *STy = dyn_cast<StructType>(*TI)) {
- assert(Indices[CurIDX]->getType() ==
- Type::getInt32Ty(ptrTy->getContext()) &&
- "Illegal struct idx");
- unsigned FieldNo = cast<ConstantInt>(Indices[CurIDX])->getZExtValue();
-
- // Get structure layout information...
- const StructLayout *Layout = getStructLayout(STy);
-
- // Add in the offset, as calculated by the structure layout info...
- Result += Layout->getElementOffset(FieldNo);
-
- // Update Ty to refer to current element
- Ty = STy->getElementType(FieldNo);
- } else {
- // Update Ty to refer to current element
- Ty = cast<SequentialType>(Ty)->getElementType();
-
- // Get the array index and the size of each array element.
- if (int64_t arrayIdx = cast<ConstantInt>(Indices[CurIDX])->getSExtValue())
- Result += (uint64_t)arrayIdx * getTypeAllocSize(Ty);
- }
- }
-
- return Result;
-}
-
-/// getPreferredAlignment - Return the preferred alignment of the specified
-/// global. This includes an explicitly requested alignment (if the global
-/// has one).
-unsigned TargetData::getPreferredAlignment(const GlobalVariable *GV) const {
- Type *ElemType = GV->getType()->getElementType();
- unsigned Alignment = getPrefTypeAlignment(ElemType);
- unsigned GVAlignment = GV->getAlignment();
- if (GVAlignment >= Alignment) {
- Alignment = GVAlignment;
- } else if (GVAlignment != 0) {
- Alignment = std::max(GVAlignment, getABITypeAlignment(ElemType));
- }
-
- if (GV->hasInitializer() && GVAlignment == 0) {
- if (Alignment < 16) {
- // If the global is not external, see if it is large. If so, give it a
- // larger alignment.
- if (getTypeSizeInBits(ElemType) > 128)
- Alignment = 16; // 16-byte alignment.
- }
- }
- return Alignment;
-}
-
-/// getPreferredAlignmentLog - Return the preferred alignment of the
-/// specified global, returned in log form. This includes an explicitly
-/// requested alignment (if the global has one).
-unsigned TargetData::getPreferredAlignmentLog(const GlobalVariable *GV) const {
- return Log2_32(getPreferredAlignment(GV));
-}
Modified: llvm/branches/R600/lib/Target/TargetELFWriterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/TargetELFWriterInfo.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/TargetELFWriterInfo.cpp (original)
+++ llvm/branches/R600/lib/Target/TargetELFWriterInfo.cpp Thu Oct 11 16:28:00 2012
@@ -13,7 +13,7 @@
#include "llvm/Function.h"
#include "llvm/Target/TargetELFWriterInfo.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
Modified: llvm/branches/R600/lib/Target/TargetLoweringObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/TargetLoweringObjectFile.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/TargetLoweringObjectFile.cpp (original)
+++ llvm/branches/R600/lib/Target/TargetLoweringObjectFile.cpp Thu Oct 11 16:28:00 2012
@@ -22,7 +22,7 @@
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/Mangler.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/Dwarf.h"
@@ -184,7 +184,7 @@
// Otherwise, just drop it into a mergable constant section. If we have
// a section for this size, use it, otherwise use the arbitrary sized
// mergable section.
- switch (TM.getTargetData()->getTypeAllocSize(C->getType())) {
+ switch (TM.getDataLayout()->getTypeAllocSize(C->getType())) {
case 4: return SectionKind::getMergeableConst4();
case 8: return SectionKind::getMergeableConst8();
case 16: return SectionKind::getMergeableConst16();
Modified: llvm/branches/R600/lib/Target/TargetMachineC.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/TargetMachineC.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/TargetMachineC.cpp (original)
+++ llvm/branches/R600/lib/Target/TargetMachineC.cpp Thu Oct 11 16:28:00 2012
@@ -14,7 +14,7 @@
#include "llvm-c/Core.h"
#include "llvm-c/Target.h"
#include "llvm-c/TargetMachine.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
@@ -146,7 +146,7 @@
}
LLVMTargetDataRef LLVMGetTargetMachineData(LLVMTargetMachineRef T) {
- return wrap(unwrap(T)->getTargetData());
+ return wrap(unwrap(T)->getDataLayout());
}
LLVMBool LLVMTargetMachineEmitToFile(LLVMTargetMachineRef T, LLVMModuleRef M,
@@ -158,14 +158,14 @@
std::string error;
- const TargetData* td = TM->getTargetData();
+ const DataLayout* td = TM->getDataLayout();
if (!td) {
- error = "No TargetData in TargetMachine";
+ error = "No DataLayout in TargetMachine";
*ErrorMessage = strdup(error.c_str());
return true;
}
- pass.add(new TargetData(*td));
+ pass.add(new DataLayout(*td));
TargetMachine::CodeGenFileType ft;
switch (codegen) {
@@ -184,7 +184,7 @@
}
if (TM->addPassesToEmitFile(pass, destf, ft)) {
- error = "No TargetData in TargetMachine";
+ error = "No DataLayout in TargetMachine";
*ErrorMessage = strdup(error.c_str());
return true;
}
Modified: llvm/branches/R600/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/AsmParser/X86AsmParser.cpp Thu Oct 11 16:28:00 2012
@@ -53,7 +53,7 @@
X86Operand *ParseOperand();
X86Operand *ParseATTOperand();
X86Operand *ParseIntelOperand();
- X86Operand *ParseIntelMemOperand();
+ X86Operand *ParseIntelMemOperand(unsigned SegReg, SMLoc StartLoc);
X86Operand *ParseIntelBracExpression(unsigned SegReg, unsigned Size);
X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
@@ -69,7 +69,7 @@
bool MatchInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out, unsigned &Kind, unsigned &Opcode,
- SmallVectorImpl<std::pair< unsigned, std::string > > &MapAndConstraints,
+ MatchInstMapAndConstraintsImpl &MapAndConstraints,
unsigned &OrigErrorInfo, bool matchingInlineAsm = false);
/// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi)
@@ -729,10 +729,9 @@
}
/// ParseIntelMemOperand - Parse intel style memory operand.
-X86Operand *X86AsmParser::ParseIntelMemOperand() {
+X86Operand *X86AsmParser::ParseIntelMemOperand(unsigned SegReg, SMLoc Start) {
const AsmToken &Tok = Parser.getTok();
- SMLoc Start = Parser.getTok().getLoc(), End;
- unsigned SegReg = 0;
+ SMLoc End;
unsigned Size = getIntelMemOperandSize(Tok.getString());
if (Size) {
@@ -776,12 +775,17 @@
// register
unsigned RegNo = 0;
if (!ParseRegister(RegNo, Start, End)) {
- End = Parser.getTok().getLoc();
- return X86Operand::CreateReg(RegNo, Start, End);
+ // If this is a segment register followed by a ':', then this is the start
+ // of a memory reference, otherwise this is a normal register reference.
+ if (getLexer().isNot(AsmToken::Colon))
+ return X86Operand::CreateReg(RegNo, Start, Parser.getTok().getLoc());
+
+ getParser().Lex(); // Eat the colon.
+ return ParseIntelMemOperand(RegNo, Start);
}
// mem operand
- return ParseIntelMemOperand();
+ return ParseIntelMemOperand(0, Start);
}
X86Operand *X86AsmParser::ParseATTOperand() {
@@ -1522,7 +1526,7 @@
unsigned Kind;
unsigned Opcode;
unsigned ErrorInfo;
- SmallVector<std::pair< unsigned, std::string >, 4> MapAndConstraints;
+ MatchInstMapAndConstraints MapAndConstraints;
bool Error = MatchInstruction(IDLoc, Operands, Out, Kind, Opcode,
MapAndConstraints, ErrorInfo);
return Error;
@@ -1627,7 +1631,7 @@
unsigned Match1, Match2, Match3, Match4;
unsigned tKind;
- SmallVector<std::pair< unsigned, std::string >, 4> tMapAndConstraints[4];
+ MatchInstMapAndConstraints tMapAndConstraints[4];
Match1 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[0],
ErrorInfoIgnore, isParsingIntelSyntax());
if (Match1 == Match_Success) Kind = tKind;
Modified: llvm/branches/R600/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Thu Oct 11 16:28:00 2012
@@ -59,7 +59,8 @@
void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
raw_ostream &O) {
- switch (MI->getOperand(Op).getImm()) {
+ int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
+ switch (Imm) {
default: llvm_unreachable("Invalid ssecc argument!");
case 0: O << "eq"; break;
case 1: O << "lt"; break;
@@ -77,6 +78,30 @@
case 0xd: O << "ge"; break;
case 0xe: O << "gt"; break;
case 0xf: O << "true"; break;
+ }
+}
+
+void X86ATTInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
+ raw_ostream &O) {
+ int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
+ switch (Imm) {
+ default: llvm_unreachable("Invalid avxcc argument!");
+ case 0: O << "eq"; break;
+ case 1: O << "lt"; break;
+ case 2: O << "le"; break;
+ case 3: O << "unord"; break;
+ case 4: O << "neq"; break;
+ case 5: O << "nlt"; break;
+ case 6: O << "nle"; break;
+ case 7: O << "ord"; break;
+ case 8: O << "eq_uq"; break;
+ case 9: O << "nge"; break;
+ case 0xa: O << "ngt"; break;
+ case 0xb: O << "false"; break;
+ case 0xc: O << "neq_oq"; break;
+ case 0xd: O << "ge"; break;
+ case 0xe: O << "gt"; break;
+ case 0xf: O << "true"; break;
case 0x10: O << "eq_os"; break;
case 0x11: O << "lt_oq"; break;
case 0x12: O << "le_oq"; break;
Modified: llvm/branches/R600/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h (original)
+++ llvm/branches/R600/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h Thu Oct 11 16:28:00 2012
@@ -40,6 +40,7 @@
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &OS);
+ void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
Modified: llvm/branches/R600/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-//===-- X86IntelInstPrinter.cpp - AT&T assembly instruction printing ------===//
+//===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
-// This file includes code for rendering MCInst instances as AT&T-style
+// This file includes code for rendering MCInst instances as Intel-style
// assembly.
//
//===----------------------------------------------------------------------===//
@@ -51,7 +51,8 @@
void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
raw_ostream &O) {
- switch (MI->getOperand(Op).getImm()) {
+ int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
+ switch (Imm) {
default: llvm_unreachable("Invalid ssecc argument!");
case 0: O << "eq"; break;
case 1: O << "lt"; break;
@@ -69,6 +70,30 @@
case 0xd: O << "ge"; break;
case 0xe: O << "gt"; break;
case 0xf: O << "true"; break;
+ }
+}
+
+void X86IntelInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
+ raw_ostream &O) {
+ int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
+ switch (Imm) {
+ default: llvm_unreachable("Invalid avxcc argument!");
+ case 0: O << "eq"; break;
+ case 1: O << "lt"; break;
+ case 2: O << "le"; break;
+ case 3: O << "unord"; break;
+ case 4: O << "neq"; break;
+ case 5: O << "nlt"; break;
+ case 6: O << "nle"; break;
+ case 7: O << "ord"; break;
+ case 8: O << "eq_uq"; break;
+ case 9: O << "nge"; break;
+ case 0xa: O << "ngt"; break;
+ case 0xb: O << "false"; break;
+ case 0xc: O << "neq_oq"; break;
+ case 0xd: O << "ge"; break;
+ case 0xe: O << "gt"; break;
+ case 0xf: O << "true"; break;
case 0x10: O << "eq_os"; break;
case 0x11: O << "lt_oq"; break;
case 0x12: O << "le_oq"; break;
@@ -85,7 +110,6 @@
case 0x1d: O << "ge_oq"; break;
case 0x1e: O << "gt_oq"; break;
case 0x1f: O << "true_us"; break;
-
}
}
@@ -160,8 +184,7 @@
printOperand(MI, Op+2, O);
NeedPlus = true;
}
-
-
+
if (!DispSpec.isImm()) {
if (NeedPlus) O << " + ";
assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
Modified: llvm/branches/R600/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h (original)
+++ llvm/branches/R600/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h Thu Oct 11 16:28:00 2012
@@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
-// This class prints an X86 MCInst to intel style .s file syntax.
+// This class prints an X86 MCInst to Intel style .s file syntax.
//
//===----------------------------------------------------------------------===//
@@ -37,6 +37,7 @@
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &O);
+ void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O);
void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
Modified: llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp Thu Oct 11 16:28:00 2012
@@ -453,7 +453,7 @@
if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
return new DarwinX86_32AsmBackend(T, CPU);
- if (TheTriple.isOSWindows())
+ if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
return new WindowsX86AsmBackend(T, false, CPU);
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
@@ -466,7 +466,7 @@
if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
return new DarwinX86_64AsmBackend(T, CPU);
- if (TheTriple.isOSWindows())
+ if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
return new WindowsX86AsmBackend(T, true, CPU);
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
Modified: llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Thu Oct 11 16:28:00 2012
@@ -16,6 +16,7 @@
#include "MCTargetDesc/X86BaseInfo.h"
#include "MCTargetDesc/X86FixupKinds.h"
#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
@@ -51,8 +52,8 @@
return (STI.getFeatureBits() & X86::Mode64Bit) == 0;
}
- static unsigned GetX86RegNum(const MCOperand &MO) {
- return X86_MC::getX86RegNum(MO.getReg());
+ unsigned GetX86RegNum(const MCOperand &MO) const {
+ return Ctx.getRegisterInfo().getEncodingValue(MO.getReg()) & 0x7;
}
// On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
@@ -64,8 +65,8 @@
// VEX.VVVV => XMM9 => ~9
//
// See table 4-35 of Intel AVX Programming Reference for details.
- static unsigned char getVEXRegisterEncoding(const MCInst &MI,
- unsigned OpNum) {
+ unsigned char getVEXRegisterEncoding(const MCInst &MI,
+ unsigned OpNum) const {
unsigned SrcReg = MI.getOperand(OpNum).getReg();
unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
if (X86II::isX86_64ExtendedReg(SrcReg))
Modified: llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp Thu Oct 11 16:28:00 2012
@@ -209,122 +209,10 @@
return DWARFFlavour::X86_32_Generic;
}
-/// getX86RegNum - This function maps LLVM register identifiers to their X86
-/// specific numbering, which is used in various places encoding instructions.
-unsigned X86_MC::getX86RegNum(unsigned RegNo) {
- switch(RegNo) {
- case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
- case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
- case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
- case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
- case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
- return N86::ESP;
- case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
- return N86::EBP;
- case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
- return N86::ESI;
- case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
- return N86::EDI;
-
- case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
- return N86::EAX;
- case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
- return N86::ECX;
- case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
- return N86::EDX;
- case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
- return N86::EBX;
- case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
- return N86::ESP;
- case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
- return N86::EBP;
- case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
- return N86::ESI;
- case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
- return N86::EDI;
-
- case X86::ST0: return 0;
- case X86::ST1: return 1;
- case X86::ST2: return 2;
- case X86::ST3: return 3;
- case X86::ST4: return 4;
- case X86::ST5: return 5;
- case X86::ST6: return 6;
- case X86::ST7: return 7;
-
- case X86::XMM0: case X86::XMM8:
- case X86::YMM0: case X86::YMM8: case X86::MM0:
- return 0;
- case X86::XMM1: case X86::XMM9:
- case X86::YMM1: case X86::YMM9: case X86::MM1:
- return 1;
- case X86::XMM2: case X86::XMM10:
- case X86::YMM2: case X86::YMM10: case X86::MM2:
- return 2;
- case X86::XMM3: case X86::XMM11:
- case X86::YMM3: case X86::YMM11: case X86::MM3:
- return 3;
- case X86::XMM4: case X86::XMM12:
- case X86::YMM4: case X86::YMM12: case X86::MM4:
- return 4;
- case X86::XMM5: case X86::XMM13:
- case X86::YMM5: case X86::YMM13: case X86::MM5:
- return 5;
- case X86::XMM6: case X86::XMM14:
- case X86::YMM6: case X86::YMM14: case X86::MM6:
- return 6;
- case X86::XMM7: case X86::XMM15:
- case X86::YMM7: case X86::YMM15: case X86::MM7:
- return 7;
-
- case X86::ES: return 0;
- case X86::CS: return 1;
- case X86::SS: return 2;
- case X86::DS: return 3;
- case X86::FS: return 4;
- case X86::GS: return 5;
-
- case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
- case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
- case X86::CR2: case X86::CR10: case X86::DR2: return 2;
- case X86::CR3: case X86::CR11: case X86::DR3: return 3;
- case X86::CR4: case X86::CR12: case X86::DR4: return 4;
- case X86::CR5: case X86::CR13: case X86::DR5: return 5;
- case X86::CR6: case X86::CR14: case X86::DR6: return 6;
- case X86::CR7: case X86::CR15: case X86::DR7: return 7;
-
- // Pseudo index registers are equivalent to a "none"
- // scaled index (See Intel Manual 2A, table 2-3)
- case X86::EIZ:
- case X86::RIZ:
- return 4;
-
- default:
- assert((int(RegNo) > 0) && "Unknown physical register!");
- return 0;
- }
-}
-
void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
// FIXME: TableGen these.
for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
- int SEH = X86_MC::getX86RegNum(Reg);
- switch (Reg) {
- case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
- case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
- case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
- case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
- case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
- case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
- case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
- case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
- case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
- case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
- case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
- case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
- SEH += 8;
- break;
- }
+ unsigned SEH = MRI->getEncodingValue(Reg);
MRI->mapLLVMRegToSEHReg(Reg, SEH);
}
}
@@ -384,11 +272,15 @@
MAI = new X86_64MCAsmInfoDarwin(TheTriple);
else
MAI = new X86MCAsmInfoDarwin(TheTriple);
+ } else if (TheTriple.getEnvironment() == Triple::ELF) {
+ // Force the use of an ELF container.
+ MAI = new X86ELFMCAsmInfo(TheTriple);
} else if (TheTriple.getOS() == Triple::Win32) {
MAI = new X86MCAsmInfoMicrosoft(TheTriple);
} else if (TheTriple.getOS() == Triple::MinGW32 || TheTriple.getOS() == Triple::Cygwin) {
MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
} else {
+ // The default is ELF.
MAI = new X86ELFMCAsmInfo(TheTriple);
}
@@ -470,7 +362,7 @@
if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
- if (TheTriple.isOSWindows())
+ if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll);
return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
Modified: llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (original)
+++ llvm/branches/R600/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h Thu Oct 11 16:28:00 2012
@@ -64,8 +64,6 @@
unsigned getDwarfRegFlavour(StringRef TT, bool isEH);
- unsigned getX86RegNum(unsigned RegNo);
-
void InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI);
/// createX86MCSubtargetInfo - Create a X86 MCSubtargetInfo instance.
Modified: llvm/branches/R600/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86.td?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86.td (original)
+++ llvm/branches/R600/lib/Target/X86/X86.td Thu Oct 11 16:28:00 2012
@@ -121,8 +121,8 @@
def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
"Use LEA for adjusting the stack pointer">;
def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
- "HasSlowDivide", "true",
- "Use small divide for positive values less than 256">;
+ "HasSlowDivide", "true",
+ "Use small divide for positive values less than 256">;
//===----------------------------------------------------------------------===//
// X86 processors supported.
Modified: llvm/branches/R600/lib/Target/X86/X86AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86AsmPrinter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86AsmPrinter.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/X86AsmPrinter.cpp Thu Oct 11 16:28:00 2012
@@ -267,46 +267,6 @@
}
}
-void X86AsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op,
- raw_ostream &O) {
- unsigned char value = MI->getOperand(Op).getImm();
- switch (value) {
- default: llvm_unreachable("Invalid ssecc argument!");
- case 0: O << "eq"; break;
- case 1: O << "lt"; break;
- case 2: O << "le"; break;
- case 3: O << "unord"; break;
- case 4: O << "neq"; break;
- case 5: O << "nlt"; break;
- case 6: O << "nle"; break;
- case 7: O << "ord"; break;
- case 8: O << "eq_uq"; break;
- case 9: O << "nge"; break;
- case 0xa: O << "ngt"; break;
- case 0xb: O << "false"; break;
- case 0xc: O << "neq_oq"; break;
- case 0xd: O << "ge"; break;
- case 0xe: O << "gt"; break;
- case 0xf: O << "true"; break;
- case 0x10: O << "eq_os"; break;
- case 0x11: O << "lt_oq"; break;
- case 0x12: O << "le_oq"; break;
- case 0x13: O << "unord_s"; break;
- case 0x14: O << "neq_us"; break;
- case 0x15: O << "nlt_uq"; break;
- case 0x16: O << "nle_uq"; break;
- case 0x17: O << "ord_s"; break;
- case 0x18: O << "eq_us"; break;
- case 0x19: O << "nge_uq"; break;
- case 0x1a: O << "ngt_uq"; break;
- case 0x1b: O << "false_os"; break;
- case 0x1c: O << "neq_os"; break;
- case 0x1d: O << "ge_oq"; break;
- case 0x1e: O << "gt_oq"; break;
- case 0x1f: O << "true_us"; break;
- }
-}
-
void X86AsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op,
raw_ostream &O, const char *Modifier) {
const MachineOperand &BaseReg = MI->getOperand(Op);
@@ -365,10 +325,51 @@
printLeaMemReference(MI, Op, O, Modifier);
}
-void X86AsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op,
- raw_ostream &O) {
- O << *MF->getPICBaseSymbol() << '\n';
- O << *MF->getPICBaseSymbol() << ':';
+void X86AsmPrinter::printIntelMemReference(const MachineInstr *MI, unsigned Op,
+ raw_ostream &O, const char *Modifier,
+ unsigned AsmVariant){
+ const MachineOperand &BaseReg = MI->getOperand(Op);
+ unsigned ScaleVal = MI->getOperand(Op+1).getImm();
+ const MachineOperand &IndexReg = MI->getOperand(Op+2);
+ const MachineOperand &DispSpec = MI->getOperand(Op+3);
+ const MachineOperand &SegReg = MI->getOperand(Op+4);
+
+ // If this has a segment register, print it.
+ if (SegReg.getReg()) {
+ printOperand(MI, Op+4, O, Modifier, AsmVariant);
+ O << ':';
+ }
+
+ O << '[';
+
+ bool NeedPlus = false;
+ if (BaseReg.getReg()) {
+ printOperand(MI, Op, O, Modifier, AsmVariant);
+ NeedPlus = true;
+ }
+
+ if (IndexReg.getReg()) {
+ if (NeedPlus) O << " + ";
+ if (ScaleVal != 1)
+ O << ScaleVal << '*';
+ printOperand(MI, Op+2, O, Modifier, AsmVariant);
+ NeedPlus = true;
+ }
+
+ assert (DispSpec.isImm() && "Displacement is not an immediate!");
+ int64_t DispVal = DispSpec.getImm();
+ if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
+ if (NeedPlus) {
+ if (DispVal > 0)
+ O << " + ";
+ else {
+ O << " - ";
+ DispVal = -DispVal;
+ }
+ }
+ O << DispVal;
+ }
+ O << ']';
}
bool X86AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
@@ -481,6 +482,11 @@
unsigned OpNo, unsigned AsmVariant,
const char *ExtraCode,
raw_ostream &O) {
+ if (AsmVariant) {
+ printIntelMemReference(MI, OpNo, O);
+ return false;
+ }
+
if (ExtraCode && ExtraCode[0]) {
if (ExtraCode[1] != 0) return true; // Unknown modifier.
@@ -682,7 +688,7 @@
MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
if (!Stubs.empty()) {
OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
- const TargetData *TD = TM.getTargetData();
+ const DataLayout *TD = TM.getDataLayout();
for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
OutStreamer.EmitLabel(Stubs[i].first);
Modified: llvm/branches/R600/lib/Target/X86/X86AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86AsmPrinter.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86AsmPrinter.h (original)
+++ llvm/branches/R600/lib/Target/X86/X86AsmPrinter.h Thu Oct 11 16:28:00 2012
@@ -34,17 +34,17 @@
Subtarget = &TM.getSubtarget<X86Subtarget>();
}
- virtual const char *getPassName() const {
+ virtual const char *getPassName() const LLVM_OVERRIDE {
return "X86 AT&T-Style Assembly Printer";
}
const X86Subtarget &getSubtarget() const { return *Subtarget; }
- virtual void EmitStartOfAsmFile(Module &M);
+ virtual void EmitStartOfAsmFile(Module &M) LLVM_OVERRIDE;
- virtual void EmitEndOfAsmFile(Module &M);
+ virtual void EmitEndOfAsmFile(Module &M) LLVM_OVERRIDE;
- virtual void EmitInstruction(const MachineInstr *MI);
+ virtual void EmitInstruction(const MachineInstr *MI) LLVM_OVERRIDE;
void printSymbolOperand(const MachineOperand &MO, raw_ostream &O);
@@ -54,27 +54,28 @@
void printPCRelImm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
- bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant, const char *ExtraCode,
- raw_ostream &OS);
- bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant, const char *ExtraCode,
- raw_ostream &OS);
+ virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
+ unsigned AsmVariant, const char *ExtraCode,
+ raw_ostream &OS) LLVM_OVERRIDE;
+ virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
+ unsigned AsmVariant, const char *ExtraCode,
+ raw_ostream &OS) LLVM_OVERRIDE;
- void printMachineInstruction(const MachineInstr *MI);
- void printSSECC(const MachineInstr *MI, unsigned Op, raw_ostream &O);
void printMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
const char *Modifier=NULL);
void printLeaMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
const char *Modifier=NULL);
- void printPICLabel(const MachineInstr *MI, unsigned Op, raw_ostream &O);
+ void printIntelMemReference(const MachineInstr *MI, unsigned Op,
+ raw_ostream &O, const char *Modifier=NULL,
+ unsigned AsmVariant = 1);
- bool runOnMachineFunction(MachineFunction &F);
+ virtual bool runOnMachineFunction(MachineFunction &F) LLVM_OVERRIDE;
void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
- MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
+ virtual MachineLocation
+ getDebugValueLocation(const MachineInstr *MI) const LLVM_OVERRIDE;
};
} // end namespace llvm
Modified: llvm/branches/R600/lib/Target/X86/X86COFFMachineModuleInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86COFFMachineModuleInfo.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86COFFMachineModuleInfo.h (original)
+++ llvm/branches/R600/lib/Target/X86/X86COFFMachineModuleInfo.h Thu Oct 11 16:28:00 2012
@@ -20,7 +20,7 @@
namespace llvm {
class X86MachineFunctionInfo;
- class TargetData;
+ class DataLayout;
/// X86COFFMachineModuleInfo - This is a MachineModuleInfoImpl implementation
/// for X86 COFF targets.
Modified: llvm/branches/R600/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86CodeEmitter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/X86CodeEmitter.cpp Thu Oct 11 16:28:00 2012
@@ -42,7 +42,7 @@
template<class CodeEmitter>
class Emitter : public MachineFunctionPass {
const X86InstrInfo *II;
- const TargetData *TD;
+ const DataLayout *TD;
X86TargetMachine &TM;
CodeEmitter &MCE;
MachineModuleInfo *MMI;
@@ -56,7 +56,7 @@
MCE(mce), PICBaseOffset(0), Is64BitMode(false),
IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
Emitter(X86TargetMachine &tm, CodeEmitter &mce,
- const X86InstrInfo &ii, const TargetData &td, bool is64)
+ const X86InstrInfo &ii, const DataLayout &td, bool is64)
: MachineFunctionPass(ID), II(&ii), TD(&td), TM(tm),
MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
@@ -109,6 +109,14 @@
void emitMemModRMByte(const MachineInstr &MI,
unsigned Op, unsigned RegOpcodeField,
intptr_t PCAdj = 0);
+
+ unsigned getX86RegNum(unsigned RegNo) const {
+ const TargetRegisterInfo *TRI = TM.getRegisterInfo();
+ return TRI->getEncodingValue(RegNo) & 0x7;
+ }
+
+ unsigned char getVEXRegisterEncoding(const MachineInstr &MI,
+ unsigned OpNum) const;
};
template<class CodeEmitter>
@@ -128,7 +136,7 @@
MCE.setModuleInfo(MMI);
II = TM.getInstrInfo();
- TD = TM.getTargetData();
+ TD = TM.getDataLayout();
Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
IsPIC = TM.getRelocationModel() == Reloc::PIC_;
@@ -363,7 +371,7 @@
template<class CodeEmitter>
void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
unsigned RegOpcodeFld){
- MCE.emitByte(ModRMByte(3, RegOpcodeFld, X86_MC::getX86RegNum(ModRMReg)));
+ MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
}
template<class CodeEmitter>
@@ -501,7 +509,7 @@
// 2-7) and absolute references.
unsigned BaseRegNo = -1U;
if (BaseReg != 0 && BaseReg != X86::RIP)
- BaseRegNo = X86_MC::getX86RegNum(BaseReg);
+ BaseRegNo = getX86RegNum(BaseReg);
if (// The SIB byte must be used if there is an index register.
IndexReg.getReg() == 0 &&
@@ -577,15 +585,15 @@
// Manual 2A, table 2-7. The displacement has already been output.
unsigned IndexRegNo;
if (IndexReg.getReg())
- IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
+ IndexRegNo = getX86RegNum(IndexReg.getReg());
else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
IndexRegNo = 4;
emitSIBByte(SS, IndexRegNo, 5);
} else {
- unsigned BaseRegNo = X86_MC::getX86RegNum(BaseReg);
+ unsigned BaseRegNo = getX86RegNum(BaseReg);
unsigned IndexRegNo;
if (IndexReg.getReg())
- IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
+ IndexRegNo = getX86RegNum(IndexReg.getReg());
else
IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
emitSIBByte(SS, IndexRegNo, BaseRegNo);
@@ -756,10 +764,12 @@
// VEX.VVVV => XMM9 => ~9
//
// See table 4-35 of Intel AVX Programming Reference for details.
-static unsigned char getVEXRegisterEncoding(const MachineInstr &MI,
- unsigned OpNum) {
+template<class CodeEmitter>
+unsigned char
+Emitter<CodeEmitter>::getVEXRegisterEncoding(const MachineInstr &MI,
+ unsigned OpNum) const {
unsigned SrcReg = MI.getOperand(OpNum).getReg();
- unsigned SrcRegNum = X86_MC::getX86RegNum(MI.getOperand(OpNum).getReg());
+ unsigned SrcRegNum = getX86RegNum(MI.getOperand(OpNum).getReg());
if (X86II::isX86_64ExtendedReg(SrcReg))
SrcRegNum |= 8;
@@ -1235,7 +1245,7 @@
case X86II::AddRegFrm: {
MCE.emitByte(BaseOpcode +
- X86_MC::getX86RegNum(MI.getOperand(CurOp++).getReg()));
+ getX86RegNum(MI.getOperand(CurOp++).getReg()));
if (CurOp == NumOps)
break;
@@ -1270,7 +1280,7 @@
case X86II::MRMDestReg: {
MCE.emitByte(BaseOpcode);
emitRegModRMByte(MI.getOperand(CurOp).getReg(),
- X86_MC::getX86RegNum(MI.getOperand(CurOp+1).getReg()));
+ getX86RegNum(MI.getOperand(CurOp+1).getReg()));
CurOp += 2;
break;
}
@@ -1281,7 +1291,7 @@
if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
SrcRegNum++;
emitMemModRMByte(MI, CurOp,
- X86_MC::getX86RegNum(MI.getOperand(SrcRegNum).getReg()));
+ getX86RegNum(MI.getOperand(SrcRegNum).getReg()));
CurOp = SrcRegNum + 1;
break;
}
@@ -1297,7 +1307,7 @@
++SrcRegNum;
emitRegModRMByte(MI.getOperand(SrcRegNum).getReg(),
- X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()));
+ getX86RegNum(MI.getOperand(CurOp).getReg()));
// 2 operands skipped with HasMemOp4, compensate accordingly
CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1;
if (HasVEX_4VOp3)
@@ -1319,7 +1329,7 @@
intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
X86II::getSizeOfImm(Desc->TSFlags) : 0;
emitMemModRMByte(MI, FirstMemOp,
- X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj);
+ getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj);
CurOp += AddrOperands + 1;
if (HasVEX_4VOp3)
++CurOp;
@@ -1409,7 +1419,7 @@
MCE.emitByte(BaseOpcode);
// Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
emitRegModRMByte(MI.getOperand(CurOp).getReg(),
- X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()));
+ getX86RegNum(MI.getOperand(CurOp).getReg()));
++CurOp;
break;
@@ -1442,7 +1452,7 @@
const MachineOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand
: CurOp);
++CurOp;
- unsigned RegNum = X86_MC::getX86RegNum(MO.getReg()) << 4;
+ unsigned RegNum = getX86RegNum(MO.getReg()) << 4;
if (X86II::isX86_64ExtendedReg(MO.getReg()))
RegNum |= 1 << 7;
// If there is an additional 5th operand it must be an immediate, which
Modified: llvm/branches/R600/lib/Target/X86/X86ELFWriterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86ELFWriterInfo.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86ELFWriterInfo.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/X86ELFWriterInfo.cpp Thu Oct 11 16:28:00 2012
@@ -16,7 +16,7 @@
#include "llvm/Function.h"
#include "llvm/Support/ELF.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
Modified: llvm/branches/R600/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86FastISel.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/X86FastISel.cpp Thu Oct 11 16:28:00 2012
@@ -710,6 +710,8 @@
bool X86FastISel::X86SelectRet(const Instruction *I) {
const ReturnInst *Ret = cast<ReturnInst>(I);
const Function &F = *I->getParent()->getParent();
+ const X86MachineFunctionInfo *X86MFInfo =
+ FuncInfo.MF->getInfo<X86MachineFunctionInfo>();
if (!FuncInfo.CanLowerReturn)
return false;
@@ -724,8 +726,7 @@
return false;
// Don't handle popping bytes on return for now.
- if (FuncInfo.MF->getInfo<X86MachineFunctionInfo>()
- ->getBytesToPopOnReturn() != 0)
+ if (X86MFInfo->getBytesToPopOnReturn() != 0)
return 0;
// fastcc with -tailcallopt is intended to provide a guaranteed
@@ -809,6 +810,19 @@
MRI.addLiveOut(VA.getLocReg());
}
+ // The x86-64 ABI for returning structs by value requires that we copy
+ // the sret argument into %rax for the return. We saved the argument into
+ // a virtual register in the entry block, so now we copy the value out
+ // and into %rax.
+ if (Subtarget->is64Bit() && F.hasStructRetAttr()) {
+ unsigned Reg = X86MFInfo->getSRetReturnReg();
+ assert(Reg &&
+ "SRetReturnReg should have been set in LowerFormalArguments()!");
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
+ X86::RAX).addReg(Reg);
+ MRI.addLiveOut(X86::RAX);
+ }
+
// Now emit the RET.
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
return true;
@@ -1527,9 +1541,9 @@
CallingConv::ID CC = CS.getCallingConv();
if (CC == CallingConv::Fast || CC == CallingConv::GHC)
return 0;
- if (!CS.paramHasAttr(1, Attribute::StructRet))
+ if (!CS.paramHasAttr(1, Attributes::StructRet))
return 0;
- if (CS.paramHasAttr(1, Attribute::InReg))
+ if (CS.paramHasAttr(1, Attributes::InReg))
return 0;
return 4;
}
@@ -1608,12 +1622,12 @@
Value *ArgVal = *i;
ISD::ArgFlagsTy Flags;
unsigned AttrInd = i - CS.arg_begin() + 1;
- if (CS.paramHasAttr(AttrInd, Attribute::SExt))
+ if (CS.paramHasAttr(AttrInd, Attributes::SExt))
Flags.setSExt();
- if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
+ if (CS.paramHasAttr(AttrInd, Attributes::ZExt))
Flags.setZExt();
- if (CS.paramHasAttr(AttrInd, Attribute::ByVal)) {
+ if (CS.paramHasAttr(AttrInd, Attributes::ByVal)) {
PointerType *Ty = cast<PointerType>(ArgVal->getType());
Type *ElementTy = Ty->getElementType();
unsigned FrameSize = TD.getTypeAllocSize(ElementTy);
@@ -1627,9 +1641,9 @@
return false;
}
- if (CS.paramHasAttr(AttrInd, Attribute::InReg))
+ if (CS.paramHasAttr(AttrInd, Attributes::InReg))
Flags.setInReg();
- if (CS.paramHasAttr(AttrInd, Attribute::Nest))
+ if (CS.paramHasAttr(AttrInd, Attributes::Nest))
Flags.setNest();
// If this is an i1/i8/i16 argument, promote to i32 to avoid an extra
@@ -1897,11 +1911,11 @@
ISD::InputArg MyFlags;
MyFlags.VT = RegisterVT.getSimpleVT();
MyFlags.Used = !CS.getInstruction()->use_empty();
- if (CS.paramHasAttr(0, Attribute::SExt))
+ if (CS.paramHasAttr(0, Attributes::SExt))
MyFlags.Flags.setSExt();
- if (CS.paramHasAttr(0, Attribute::ZExt))
+ if (CS.paramHasAttr(0, Attributes::ZExt))
MyFlags.Flags.setZExt();
- if (CS.paramHasAttr(0, Attribute::InReg))
+ if (CS.paramHasAttr(0, Attributes::InReg))
MyFlags.Flags.setInReg();
Ins.push_back(MyFlags);
}
Modified: llvm/branches/R600/lib/Target/X86/X86FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86FrameLowering.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86FrameLowering.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/X86FrameLowering.cpp Thu Oct 11 16:28:00 2012
@@ -25,7 +25,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCSymbol.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/ADT/SmallSet.h"
@@ -313,7 +313,7 @@
if (CSI.empty()) return;
std::vector<MachineMove> &Moves = MMI.getFrameMoves();
- const TargetData *TD = TM.getTargetData();
+ const DataLayout *TD = TM.getDataLayout();
bool HasFP = hasFP(MF);
// Calculate amount of bytes used for return address storing.
@@ -674,7 +674,7 @@
// function, and use up to 128 bytes of stack space, don't have a frame
// pointer, calls, or dynamic alloca then we do not need to adjust the
// stack pointer (we fit in the Red Zone).
- if (Is64Bit && !Fn->getFnAttributes().hasNoRedZoneAttr() &&
+ if (Is64Bit && !Fn->getFnAttributes().hasAttribute(Attributes::NoRedZone) &&
!RegInfo->needsStackRealignment(MF) &&
!MFI->hasVarSizedObjects() && // No dynamic alloca.
!MFI->adjustsStack() && // No calls.
@@ -715,7 +715,7 @@
// ELSE => DW_CFA_offset_extended
std::vector<MachineMove> &Moves = MMI.getFrameMoves();
- const TargetData *TD = MF.getTarget().getTargetData();
+ const DataLayout *TD = MF.getTarget().getDataLayout();
uint64_t NumBytes = 0;
int stackGrowth = -TD->getPointerSize();
@@ -836,8 +836,6 @@
MI->getOperand(3).setIsDead();
}
- DL = MBB.findDebugLoc(MBBI);
-
// If there is an SUB32ri of ESP immediately before this instruction, merge
// the two. This can be the case when tail call elimination is enabled and
// the callee has more arguments then the caller.
Modified: llvm/branches/R600/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Oct 11 16:28:00 2012
@@ -362,7 +362,7 @@
/// MoveBelowCallOrigChain - Replace the original chain operand of the call with
/// load's chain operand and move load below the call's chain operand.
static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
- SDValue Call, SDValue OrigChain) {
+ SDValue Call, SDValue OrigChain) {
SmallVector<SDValue, 8> Ops;
SDValue Chain = OrigChain.getOperand(0);
if (Chain.getNode() == Load.getNode())
@@ -386,11 +386,13 @@
CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size());
CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
Load.getOperand(1), Load.getOperand(2));
+
+ unsigned NumOps = Call.getNode()->getNumOperands();
Ops.clear();
Ops.push_back(SDValue(Load.getNode(), 1));
- for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
+ for (unsigned i = 1, e = NumOps; i != e; ++i)
Ops.push_back(Call.getOperand(i));
- CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], Ops.size());
+ CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], NumOps);
}
/// isCalleeLoad - Return true if call address is a load and it can be
@@ -399,6 +401,10 @@
/// In the case of a tail call, there isn't a callseq node between the call
/// chain and the load.
static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
+ // The transformation is somewhat dangerous if the call's chain was glued to
+ // the call. After MoveBelowOrigChain the load is moved between the call and
+ // the chain, this can create a cycle if the load is not folded. So it is
+ // *really* important that we are sure the load will be folded.
if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
return false;
LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
@@ -428,7 +434,8 @@
void X86DAGToDAGISel::PreprocessISelDAG() {
// OptForSize is used in pattern predicates that isel is matching.
- OptForSize = MF->getFunction()->getFnAttributes().hasOptimizeForSizeAttr();
+ OptForSize = MF->getFunction()->getFnAttributes().
+ hasAttribute(Attributes::OptimizeForSize);
for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
E = CurDAG->allnodes_end(); I != E; ) {
@@ -436,7 +443,10 @@
if (OptLevel != CodeGenOpt::None &&
(N->getOpcode() == X86ISD::CALL ||
- N->getOpcode() == X86ISD::TC_RETURN)) {
+ (N->getOpcode() == X86ISD::TC_RETURN &&
+ // Only does this if load can be foled into TC_RETURN.
+ (Subtarget->is64Bit() ||
+ getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
/// Also try moving call address load from outside callseq_start to just
/// before the call to allow it to be folded.
///
Modified: llvm/branches/R600/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86ISelLowering.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/X86ISelLowering.cpp Thu Oct 11 16:28:00 2012
@@ -161,7 +161,7 @@
X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
RegInfo = TM.getRegisterInfo();
- TD = getTargetData();
+ TD = getDataLayout();
// Set up the TargetLowering object.
static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
@@ -184,7 +184,7 @@
// Bypass i32 with i8 on Atom when compiling with O2
if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default)
- addBypassSlowDivType(Type::getInt32Ty(getGlobalContext()), Type::getInt8Ty(getGlobalContext()));
+ addBypassSlowDiv(32, 8);
if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
// Setup Windows compiler runtime calls.
@@ -1342,7 +1342,7 @@
// cases like PR2962. This should be removed when PR2962 is fixed.
const Function *F = MF.getFunction();
if (IsZeroVal &&
- !F->getFnAttributes().hasNoImplicitFloatAttr()) {
+ !F->getFnAttributes().hasAttribute(Attributes::NoImplicitFloat)) {
if (Size >= 16 &&
(Subtarget->isUnalignedMemAccessFast() ||
((DstAlign == 0 || DstAlign >= 16) &&
@@ -2010,7 +2010,8 @@
unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
TotalNumIntRegs);
- bool NoImplicitFloatOps = Fn->getFnAttributes().hasNoImplicitFloatAttr();
+ bool NoImplicitFloatOps = Fn->getFnAttributes().
+ hasAttribute(Attributes::NoImplicitFloat);
assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
"SSE register cannot be used when SSE is disabled!");
assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
@@ -2486,7 +2487,8 @@
OpFlags = X86II::MO_DARWIN_STUB;
} else if (Subtarget->isPICStyleRIPRel() &&
isa<Function>(GV) &&
- cast<Function>(GV)->getFnAttributes().hasNonLazyBindAttr()) {
+ cast<Function>(GV)->getFnAttributes().
+ hasAttribute(Attributes::NonLazyBind)) {
// If the function is marked as non-lazy, generate an indirect call
// which loads from the GOT directly. This avoids runtime overhead
// at the cost of eager binding (and one extra byte of encoding).
@@ -3541,7 +3543,7 @@
if (!MatchEvenMask && !MatchOddMask)
return SDValue();
-
+
SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
SDValue Op0 = SVOp->getOperand(0);
@@ -6053,7 +6055,7 @@
bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
- // VPSHUFB may be generated if
+ // VPSHUFB may be generated if
// (1) one of input vector is undefined or zeroinitializer.
// The mask value 0x80 puts 0 in the corresponding slot of the vector.
// And (2) the mask indexes don't cross the 128-bit lane.
@@ -6629,7 +6631,8 @@
bool HasAVX = Subtarget->hasAVX();
bool HasAVX2 = Subtarget->hasAVX2();
MachineFunction &MF = DAG.getMachineFunction();
- bool OptForSize = MF.getFunction()->getFnAttributes().hasOptimizeForSizeAttr();
+ bool OptForSize = MF.getFunction()->getFnAttributes().
+ hasAttribute(Attributes::OptimizeForSize);
assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
@@ -9649,7 +9652,7 @@
EVT ArgVT = Op.getNode()->getValueType(0);
Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
- uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
+ uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
uint8_t ArgMode;
// Decide which area this value should be read from.
@@ -9669,7 +9672,8 @@
// Sanity Check: Make sure using fp_offset makes sense.
assert(!getTargetMachine().Options.UseSoftFloat &&
!(DAG.getMachineFunction()
- .getFunction()->getFnAttributes().hasNoImplicitFloatAttr()) &&
+ .getFunction()->getFnAttributes()
+ .hasAttribute(Attributes::NoImplicitFloat)) &&
Subtarget->hasSSE1());
}
@@ -10412,6 +10416,7 @@
DebugLoc dl = Op.getDebugLoc();
const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
+ const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
if (Subtarget->is64Bit()) {
SDValue OutChains[6];
@@ -10420,8 +10425,8 @@
const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
- const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
- const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
+ const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
+ const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
@@ -10494,7 +10499,7 @@
for (FunctionType::param_iterator I = FTy->param_begin(),
E = FTy->param_end(); I != E; ++I, ++Idx)
- if (Attrs.paramHasAttr(Idx, Attribute::InReg))
+ if (Attrs.getParamAttributes(Idx).hasAttribute(Attributes::InReg))
// FIXME: should only count parameters that are lowered to integers.
InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
@@ -10523,7 +10528,7 @@
// This is storing the opcode for MOV32ri.
const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
- const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
+ const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
OutChains[0] = DAG.getStore(Root, dl,
DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
Trmp, MachinePointerInfo(TrmpAddr),
@@ -12384,9 +12389,12 @@
// Hi
MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EDX);
for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
- if (i == X86::AddrDisp)
+ if (i == X86::AddrDisp) {
MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
- else
+ // Don't forget to transfer the target flag.
+ MachineOperand &MO = MIB->getOperand(MIB->getNumOperands()-1);
+ MO.setTargetFlags(MI->getOperand(MemOpndSlot + i).getTargetFlags());
+ } else
MIB.addOperand(MI->getOperand(MemOpndSlot + i));
}
MIB.setMemRefs(MMOBegin, MMOEnd);
@@ -13910,7 +13918,7 @@
// alignment is valid.
unsigned Align = LN0->getAlignment();
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- unsigned NewAlign = TLI.getTargetData()->
+ unsigned NewAlign = TLI.getDataLayout()->
getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
@@ -15438,7 +15446,8 @@
return SDValue();
const Function *F = DAG.getMachineFunction().getFunction();
- bool NoImplicitFloatOps = F->getFnAttributes().hasNoImplicitFloatAttr();
+ bool NoImplicitFloatOps = F->getFnAttributes().
+ hasAttribute(Attributes::NoImplicitFloat);
bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
&& Subtarget->hasSSE2();
if ((VT.isVector() ||
Modified: llvm/branches/R600/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86ISelLowering.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/branches/R600/lib/Target/X86/X86ISelLowering.h Thu Oct 11 16:28:00 2012
@@ -701,7 +701,7 @@
/// make the right decision when generating code for different targets.
const X86Subtarget *Subtarget;
const X86RegisterInfo *RegInfo;
- const TargetData *TD;
+ const DataLayout *TD;
/// X86StackPtr - X86 physical register used as stack ptr.
unsigned X86StackPtr;
Modified: llvm/branches/R600/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86InstrCompiler.td?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/branches/R600/lib/Target/X86/X86InstrCompiler.td Thu Oct 11 16:28:00 2012
@@ -230,25 +230,18 @@
IIC_ALU_NONMEM>;
// Use sbb to materialize carry bit.
-let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in {
+let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1 in {
// FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
// However, Pat<> can't replicate the destination reg into the inputs of the
// result.
-// FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
-// X86CodeEmitter.
-def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
- [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
- IIC_ALU_NONMEM>;
-def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
- [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
- IIC_ALU_NONMEM>,
- OpSize;
-def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
- [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
- IIC_ALU_NONMEM>;
-def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
- [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
- IIC_ALU_NONMEM>;
+def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
+ [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
+def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
+ [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
+def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
+ [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
+def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
+ [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
} // isCodeGenOnly
@@ -453,6 +446,11 @@
"#CMOV_GR16* PSEUDO!",
[(set GR16:$dst,
(X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
+} // Predicates = [NoCMov]
+
+// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
+// SSE1.
+let Predicates = [FPStackf32] in
def CMOV_RFP32 : I<0, Pseudo,
(outs RFP32:$dst),
(ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
@@ -460,6 +458,9 @@
[(set RFP32:$dst,
(X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
EFLAGS))]>;
+// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
+// SSE2.
+let Predicates = [FPStackf64] in
def CMOV_RFP64 : I<0, Pseudo,
(outs RFP64:$dst),
(ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
@@ -474,7 +475,6 @@
[(set RFP80:$dst,
(X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
EFLAGS))]>;
-} // Predicates = [NoCMov]
} // UsesCustomInserter = 1, Uses = [EFLAGS]
Modified: llvm/branches/R600/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86InstrInfo.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/X86InstrInfo.cpp Thu Oct 11 16:28:00 2012
@@ -3509,6 +3509,14 @@
bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
switch (MI->getOpcode()) {
+ case X86::SETB_C8r:
+ return Expand2AddrUndef(MI, get(X86::SBB8rr));
+ case X86::SETB_C16r:
+ return Expand2AddrUndef(MI, get(X86::SBB16rr));
+ case X86::SETB_C32r:
+ return Expand2AddrUndef(MI, get(X86::SBB32rr));
+ case X86::SETB_C64r:
+ return Expand2AddrUndef(MI, get(X86::SBB64rr));
case X86::V_SET0:
case X86::FsFLD0SS:
case X86::FsFLD0SD:
@@ -3820,7 +3828,8 @@
// Unless optimizing for size, don't fold to avoid partial
// register update stalls
- if (!MF.getFunction()->getFnAttributes().hasOptimizeForSizeAttr() &&
+ if (!MF.getFunction()->getFnAttributes().
+ hasAttribute(Attributes::OptimizeForSize) &&
hasPartialRegUpdate(MI->getOpcode()))
return 0;
@@ -3861,7 +3870,8 @@
// Unless optimizing for size, don't fold to avoid partial
// register update stalls
- if (!MF.getFunction()->getFnAttributes().hasOptimizeForSizeAttr() &&
+ if (!MF.getFunction()->getFnAttributes().
+ hasAttribute(Attributes::OptimizeForSize) &&
hasPartialRegUpdate(MI->getOpcode()))
return 0;
Modified: llvm/branches/R600/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86InstrInfo.td?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/branches/R600/lib/Target/X86/X86InstrInfo.td Thu Oct 11 16:28:00 2012
@@ -418,7 +418,7 @@
}
def AVXCC : Operand<i8> {
- let PrintMethod = "printSSECC";
+ let PrintMethod = "printAVXCC";
let OperandType = "OPERAND_IMMEDIATE";
}
Modified: llvm/branches/R600/lib/Target/X86/X86MCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86MCInstLower.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86MCInstLower.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/X86MCInstLower.cpp Thu Oct 11 16:28:00 2012
@@ -371,10 +371,6 @@
case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
- case X86::SETB_C8r: LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break;
- case X86::SETB_C16r: LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break;
- case X86::SETB_C32r: LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break;
- case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break;
case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
Modified: llvm/branches/R600/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86RegisterInfo.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/X86RegisterInfo.cpp Thu Oct 11 16:28:00 2012
@@ -106,23 +106,7 @@
int
X86RegisterInfo::getSEHRegNum(unsigned i) const {
- int reg = X86_MC::getX86RegNum(i);
- switch (i) {
- case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
- case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
- case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
- case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
- case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
- case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
- case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
- case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
- case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
- case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
- case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
- case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
- reg += 8;
- }
- return reg;
+ return getEncodingValue(i);
}
const TargetRegisterClass *
@@ -398,8 +382,9 @@
const MachineFrameInfo *MFI = MF.getFrameInfo();
const Function *F = MF.getFunction();
unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
- bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
- F->getFnAttributes().hasStackAlignmentAttr());
+ bool requiresRealignment =
+ ((MFI->getMaxAlignment() > StackAlign) ||
+ F->getFnAttributes().hasAttribute(Attributes::StackAlignment));
// If we've requested that we force align the stack do so now.
if (ForceStackAlign)
Modified: llvm/branches/R600/lib/Target/X86/X86RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86RegisterInfo.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86RegisterInfo.h (original)
+++ llvm/branches/R600/lib/Target/X86/X86RegisterInfo.h Thu Oct 11 16:28:00 2012
@@ -58,10 +58,6 @@
public:
X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
- /// getX86RegNum - Returns the native X86 register number for the given LLVM
- /// register identifier.
- static unsigned getX86RegNum(unsigned RegNo);
-
// FIXME: This should be tablegen'd like getDwarfRegNum is
int getSEHRegNum(unsigned i) const;
Modified: llvm/branches/R600/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86RegisterInfo.td?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/branches/R600/lib/Target/X86/X86RegisterInfo.td Thu Oct 11 16:28:00 2012
@@ -13,258 +13,264 @@
//
//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// Register definitions...
-//
-let Namespace = "X86" in {
+class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> {
+ let Namespace = "X86";
+ let HWEncoding = Enc;
+ let SubRegs = subregs;
+}
- // Subregister indices.
+// Subregister indices.
+let Namespace = "X86" in {
def sub_8bit : SubRegIndex;
def sub_8bit_hi : SubRegIndex;
def sub_16bit : SubRegIndex;
def sub_32bit : SubRegIndex;
- def sub_xmm : SubRegIndex;
+ def sub_xmm : SubRegIndex;
+}
+
+//===----------------------------------------------------------------------===//
+// Register definitions...
+//
+
+// In the register alias definitions below, we define which registers alias
+// which others. We only specify which registers the small registers alias,
+// because the register file generator is smart enough to figure out that
+// AL aliases AX if we tell it that AX aliased AL (for example).
+
+// Dwarf numbering is different for 32-bit and 64-bit, and there are
+// variations by target as well. Currently the first entry is for X86-64,
+// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
+// and debug information on X86-32/Darwin)
+
+// 8-bit registers
+// Low registers
+def AL : X86Reg<"al", 0>;
+def DL : X86Reg<"dl", 2>;
+def CL : X86Reg<"cl", 1>;
+def BL : X86Reg<"bl", 3>;
+
+// High registers. On x86-64, these cannot be used in any instruction
+// with a REX prefix.
+def AH : X86Reg<"ah", 4>;
+def DH : X86Reg<"dh", 6>;
+def CH : X86Reg<"ch", 5>;
+def BH : X86Reg<"bh", 7>;
+
+// X86-64 only, requires REX.
+let CostPerUse = 1 in {
+def SIL : X86Reg<"sil", 6>;
+def DIL : X86Reg<"dil", 7>;
+def BPL : X86Reg<"bpl", 5>;
+def SPL : X86Reg<"spl", 4>;
+def R8B : X86Reg<"r8b", 8>;
+def R9B : X86Reg<"r9b", 9>;
+def R10B : X86Reg<"r10b", 10>;
+def R11B : X86Reg<"r11b", 11>;
+def R12B : X86Reg<"r12b", 12>;
+def R13B : X86Reg<"r13b", 13>;
+def R14B : X86Reg<"r14b", 14>;
+def R15B : X86Reg<"r15b", 15>;
+}
+
+// 16-bit registers
+let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
+def AX : X86Reg<"ax", 0, [AL,AH]>;
+def DX : X86Reg<"dx", 2, [DL,DH]>;
+def CX : X86Reg<"cx", 1, [CL,CH]>;
+def BX : X86Reg<"bx", 3, [BL,BH]>;
+}
+let SubRegIndices = [sub_8bit] in {
+def SI : X86Reg<"si", 6, [SIL]>;
+def DI : X86Reg<"di", 7, [DIL]>;
+def BP : X86Reg<"bp", 5, [BPL]>;
+def SP : X86Reg<"sp", 4, [SPL]>;
+}
+def IP : X86Reg<"ip", 0>;
+// X86-64 only, requires REX.
+let SubRegIndices = [sub_8bit], CostPerUse = 1 in {
+def R8W : X86Reg<"r8w", 8, [R8B]>;
+def R9W : X86Reg<"r9w", 9, [R9B]>;
+def R10W : X86Reg<"r10w", 10, [R10B]>;
+def R11W : X86Reg<"r11w", 11, [R11B]>;
+def R12W : X86Reg<"r12w", 12, [R12B]>;
+def R13W : X86Reg<"r13w", 13, [R13B]>;
+def R14W : X86Reg<"r14w", 14, [R14B]>;
+def R15W : X86Reg<"r15w", 15, [R15B]>;
+}
- // In the register alias definitions below, we define which registers alias
- // which others. We only specify which registers the small registers alias,
- // because the register file generator is smart enough to figure out that
- // AL aliases AX if we tell it that AX aliased AL (for example).
-
- // Dwarf numbering is different for 32-bit and 64-bit, and there are
- // variations by target as well. Currently the first entry is for X86-64,
- // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
- // and debug information on X86-32/Darwin)
-
- // 8-bit registers
- // Low registers
- def AL : Register<"al">;
- def DL : Register<"dl">;
- def CL : Register<"cl">;
- def BL : Register<"bl">;
-
- // X86-64 only, requires REX.
- let CostPerUse = 1 in {
- def SIL : Register<"sil">;
- def DIL : Register<"dil">;
- def BPL : Register<"bpl">;
- def SPL : Register<"spl">;
- def R8B : Register<"r8b">;
- def R9B : Register<"r9b">;
- def R10B : Register<"r10b">;
- def R11B : Register<"r11b">;
- def R12B : Register<"r12b">;
- def R13B : Register<"r13b">;
- def R14B : Register<"r14b">;
- def R15B : Register<"r15b">;
- }
-
- // High registers. On x86-64, these cannot be used in any instruction
- // with a REX prefix.
- def AH : Register<"ah">;
- def DH : Register<"dh">;
- def CH : Register<"ch">;
- def BH : Register<"bh">;
-
- // 16-bit registers
- let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in {
- def AX : RegisterWithSubRegs<"ax", [AL,AH]>;
- def DX : RegisterWithSubRegs<"dx", [DL,DH]>;
- def CX : RegisterWithSubRegs<"cx", [CL,CH]>;
- def BX : RegisterWithSubRegs<"bx", [BL,BH]>;
- }
- let SubRegIndices = [sub_8bit] in {
- def SI : RegisterWithSubRegs<"si", [SIL]>;
- def DI : RegisterWithSubRegs<"di", [DIL]>;
- def BP : RegisterWithSubRegs<"bp", [BPL]>;
- def SP : RegisterWithSubRegs<"sp", [SPL]>;
- }
- def IP : Register<"ip">;
-
- // X86-64 only, requires REX.
- let SubRegIndices = [sub_8bit], CostPerUse = 1 in {
- def R8W : RegisterWithSubRegs<"r8w", [R8B]>;
- def R9W : RegisterWithSubRegs<"r9w", [R9B]>;
- def R10W : RegisterWithSubRegs<"r10w", [R10B]>;
- def R11W : RegisterWithSubRegs<"r11w", [R11B]>;
- def R12W : RegisterWithSubRegs<"r12w", [R12B]>;
- def R13W : RegisterWithSubRegs<"r13w", [R13B]>;
- def R14W : RegisterWithSubRegs<"r14w", [R14B]>;
- def R15W : RegisterWithSubRegs<"r15w", [R15B]>;
- }
- // 32-bit registers
- let SubRegIndices = [sub_16bit] in {
- def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[-2, 0, 0]>;
- def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[-2, 2, 2]>;
- def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[-2, 1, 1]>;
- def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[-2, 3, 3]>;
- def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[-2, 6, 6]>;
- def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[-2, 7, 7]>;
- def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[-2, 4, 5]>;
- def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[-2, 5, 4]>;
- def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[-2, 8, 8]>;
-
- // X86-64 only, requires REX
- let CostPerUse = 1 in {
- def R8D : RegisterWithSubRegs<"r8d", [R8W]>;
- def R9D : RegisterWithSubRegs<"r9d", [R9W]>;
- def R10D : RegisterWithSubRegs<"r10d", [R10W]>;
- def R11D : RegisterWithSubRegs<"r11d", [R11W]>;
- def R12D : RegisterWithSubRegs<"r12d", [R12W]>;
- def R13D : RegisterWithSubRegs<"r13d", [R13W]>;
- def R14D : RegisterWithSubRegs<"r14d", [R14W]>;
- def R15D : RegisterWithSubRegs<"r15d", [R15W]>;
- }}
-
- // 64-bit registers, X86-64 only
- let SubRegIndices = [sub_32bit] in {
- def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
- def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
- def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
- def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
- def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
- def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>;
- def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
- def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
-
- // These also require REX.
- let CostPerUse = 1 in {
- def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
- def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
- def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
- def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
- def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
- def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
- def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
- def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
- def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
- }}
-
- // MMX Registers. These are actually aliased to ST0 .. ST7
- def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
- def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
- def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>;
- def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
- def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
- def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
- def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
- def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
-
- // Pseudo Floating Point registers
- def FP0 : Register<"fp0">;
- def FP1 : Register<"fp1">;
- def FP2 : Register<"fp2">;
- def FP3 : Register<"fp3">;
- def FP4 : Register<"fp4">;
- def FP5 : Register<"fp5">;
- def FP6 : Register<"fp6">;
-
- // XMM Registers, used by the various SSE instruction set extensions.
- def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
- def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
- def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
- def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>;
- def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>;
- def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>;
- def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>;
- def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
-
- // X86-64 only
- let CostPerUse = 1 in {
- def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
- def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
- def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
- def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>;
- def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>;
- def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
- def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
- def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
- } // CostPerUse
-
- // YMM Registers, used by AVX instructions
- let SubRegIndices = [sub_xmm] in {
- def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegAlias<XMM0>;
- def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegAlias<XMM1>;
- def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegAlias<XMM2>;
- def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegAlias<XMM3>;
- def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegAlias<XMM4>;
- def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegAlias<XMM5>;
- def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegAlias<XMM6>;
- def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegAlias<XMM7>;
- def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegAlias<XMM8>;
- def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegAlias<XMM9>;
- def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegAlias<XMM10>;
- def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegAlias<XMM11>;
- def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegAlias<XMM12>;
- def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegAlias<XMM13>;
- def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegAlias<XMM14>;
- def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegAlias<XMM15>;
- }
-
- class STRegister<string Name, list<Register> A> : Register<Name> {
- let Aliases = A;
- }
-
- // Floating point stack registers. These don't map one-to-one to the FP
- // pseudo registers, but we still mark them as aliasing FP registers. That
- // way both kinds can be live without exceeding the stack depth. ST registers
- // are only live around inline assembly.
- def ST0 : STRegister<"st(0)", []>, DwarfRegNum<[33, 12, 11]>;
- def ST1 : STRegister<"st(1)", [FP6]>, DwarfRegNum<[34, 13, 12]>;
- def ST2 : STRegister<"st(2)", [FP5]>, DwarfRegNum<[35, 14, 13]>;
- def ST3 : STRegister<"st(3)", [FP4]>, DwarfRegNum<[36, 15, 14]>;
- def ST4 : STRegister<"st(4)", [FP3]>, DwarfRegNum<[37, 16, 15]>;
- def ST5 : STRegister<"st(5)", [FP2]>, DwarfRegNum<[38, 17, 16]>;
- def ST6 : STRegister<"st(6)", [FP1]>, DwarfRegNum<[39, 18, 17]>;
- def ST7 : STRegister<"st(7)", [FP0]>, DwarfRegNum<[40, 19, 18]>;
-
- // Floating-point status word
- def FPSW : Register<"fpsw">;
-
- // Status flags register
- def EFLAGS : Register<"flags">;
-
- // Segment registers
- def CS : Register<"cs">;
- def DS : Register<"ds">;
- def SS : Register<"ss">;
- def ES : Register<"es">;
- def FS : Register<"fs">;
- def GS : Register<"gs">;
-
- // Debug registers
- def DR0 : Register<"dr0">;
- def DR1 : Register<"dr1">;
- def DR2 : Register<"dr2">;
- def DR3 : Register<"dr3">;
- def DR4 : Register<"dr4">;
- def DR5 : Register<"dr5">;
- def DR6 : Register<"dr6">;
- def DR7 : Register<"dr7">;
-
- // Control registers
- def CR0 : Register<"cr0">;
- def CR1 : Register<"cr1">;
- def CR2 : Register<"cr2">;
- def CR3 : Register<"cr3">;
- def CR4 : Register<"cr4">;
- def CR5 : Register<"cr5">;
- def CR6 : Register<"cr6">;
- def CR7 : Register<"cr7">;
- def CR8 : Register<"cr8">;
- def CR9 : Register<"cr9">;
- def CR10 : Register<"cr10">;
- def CR11 : Register<"cr11">;
- def CR12 : Register<"cr12">;
- def CR13 : Register<"cr13">;
- def CR14 : Register<"cr14">;
- def CR15 : Register<"cr15">;
-
- // Pseudo index registers
- def EIZ : Register<"eiz">;
- def RIZ : Register<"riz">;
+// 32-bit registers
+let SubRegIndices = [sub_16bit] in {
+def EAX : X86Reg<"eax", 0, [AX]>, DwarfRegNum<[-2, 0, 0]>;
+def EDX : X86Reg<"edx", 2, [DX]>, DwarfRegNum<[-2, 2, 2]>;
+def ECX : X86Reg<"ecx", 1, [CX]>, DwarfRegNum<[-2, 1, 1]>;
+def EBX : X86Reg<"ebx", 3, [BX]>, DwarfRegNum<[-2, 3, 3]>;
+def ESI : X86Reg<"esi", 6, [SI]>, DwarfRegNum<[-2, 6, 6]>;
+def EDI : X86Reg<"edi", 7, [DI]>, DwarfRegNum<[-2, 7, 7]>;
+def EBP : X86Reg<"ebp", 5, [BP]>, DwarfRegNum<[-2, 4, 5]>;
+def ESP : X86Reg<"esp", 4, [SP]>, DwarfRegNum<[-2, 5, 4]>;
+def EIP : X86Reg<"eip", 0, [IP]>, DwarfRegNum<[-2, 8, 8]>;
+
+// X86-64 only, requires REX
+let CostPerUse = 1 in {
+def R8D : X86Reg<"r8d", 8, [R8W]>;
+def R9D : X86Reg<"r9d", 9, [R9W]>;
+def R10D : X86Reg<"r10d", 10, [R10W]>;
+def R11D : X86Reg<"r11d", 11, [R11W]>;
+def R12D : X86Reg<"r12d", 12, [R12W]>;
+def R13D : X86Reg<"r13d", 13, [R13W]>;
+def R14D : X86Reg<"r14d", 14, [R14W]>;
+def R15D : X86Reg<"r15d", 15, [R15W]>;
+}}
+
+// 64-bit registers, X86-64 only
+let SubRegIndices = [sub_32bit] in {
+def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
+def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>;
+def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>;
+def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>;
+def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>;
+def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>;
+def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>;
+def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
+
+// These also require REX.
+let CostPerUse = 1 in {
+def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>;
+def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>;
+def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>;
+def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>;
+def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>;
+def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>;
+def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>;
+def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>;
+def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>;
+}}
+
+// MMX Registers. These are actually aliased to ST0 .. ST7
+def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>;
+def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>;
+def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>;
+def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>;
+def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>;
+def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>;
+def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>;
+def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;
+
+// Pseudo Floating Point registers
+def FP0 : X86Reg<"fp0", 0>;
+def FP1 : X86Reg<"fp1", 0>;
+def FP2 : X86Reg<"fp2", 0>;
+def FP3 : X86Reg<"fp3", 0>;
+def FP4 : X86Reg<"fp4", 0>;
+def FP5 : X86Reg<"fp5", 0>;
+def FP6 : X86Reg<"fp6", 0>;
+
+// XMM Registers, used by the various SSE instruction set extensions.
+def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>;
+def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>;
+def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>;
+def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>;
+def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>;
+def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>;
+def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>;
+def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>;
+
+// X86-64 only
+let CostPerUse = 1 in {
+def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>;
+def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>;
+def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>;
+def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>;
+def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>;
+def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>;
+def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>;
+def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>;
+} // CostPerUse
+
+// YMM Registers, used by AVX instructions
+let SubRegIndices = [sub_xmm] in {
+def YMM0: X86Reg<"ymm0", 0, [XMM0]>, DwarfRegAlias<XMM0>;
+def YMM1: X86Reg<"ymm1", 1, [XMM1]>, DwarfRegAlias<XMM1>;
+def YMM2: X86Reg<"ymm2", 2, [XMM2]>, DwarfRegAlias<XMM2>;
+def YMM3: X86Reg<"ymm3", 3, [XMM3]>, DwarfRegAlias<XMM3>;
+def YMM4: X86Reg<"ymm4", 4, [XMM4]>, DwarfRegAlias<XMM4>;
+def YMM5: X86Reg<"ymm5", 5, [XMM5]>, DwarfRegAlias<XMM5>;
+def YMM6: X86Reg<"ymm6", 6, [XMM6]>, DwarfRegAlias<XMM6>;
+def YMM7: X86Reg<"ymm7", 7, [XMM7]>, DwarfRegAlias<XMM7>;
+def YMM8: X86Reg<"ymm8", 8, [XMM8]>, DwarfRegAlias<XMM8>;
+def YMM9: X86Reg<"ymm9", 9, [XMM9]>, DwarfRegAlias<XMM9>;
+def YMM10: X86Reg<"ymm10", 10, [XMM10]>, DwarfRegAlias<XMM10>;
+def YMM11: X86Reg<"ymm11", 11, [XMM11]>, DwarfRegAlias<XMM11>;
+def YMM12: X86Reg<"ymm12", 12, [XMM12]>, DwarfRegAlias<XMM12>;
+def YMM13: X86Reg<"ymm13", 13, [XMM13]>, DwarfRegAlias<XMM13>;
+def YMM14: X86Reg<"ymm14", 14, [XMM14]>, DwarfRegAlias<XMM14>;
+def YMM15: X86Reg<"ymm15", 15, [XMM15]>, DwarfRegAlias<XMM15>;
}
+class STRegister<string n, bits<16> Enc, list<Register> A> : X86Reg<n, Enc> {
+ let Aliases = A;
+}
+
+// Floating point stack registers. These don't map one-to-one to the FP
+// pseudo registers, but we still mark them as aliasing FP registers. That
+// way both kinds can be live without exceeding the stack depth. ST registers
+// are only live around inline assembly.
+def ST0 : STRegister<"st(0)", 0, []>, DwarfRegNum<[33, 12, 11]>;
+def ST1 : STRegister<"st(1)", 1, [FP6]>, DwarfRegNum<[34, 13, 12]>;
+def ST2 : STRegister<"st(2)", 2, [FP5]>, DwarfRegNum<[35, 14, 13]>;
+def ST3 : STRegister<"st(3)", 3, [FP4]>, DwarfRegNum<[36, 15, 14]>;
+def ST4 : STRegister<"st(4)", 4, [FP3]>, DwarfRegNum<[37, 16, 15]>;
+def ST5 : STRegister<"st(5)", 5, [FP2]>, DwarfRegNum<[38, 17, 16]>;
+def ST6 : STRegister<"st(6)", 6, [FP1]>, DwarfRegNum<[39, 18, 17]>;
+def ST7 : STRegister<"st(7)", 7, [FP0]>, DwarfRegNum<[40, 19, 18]>;
+
+// Floating-point status word
+def FPSW : X86Reg<"fpsw", 0>;
+
+// Status flags register
+def EFLAGS : X86Reg<"flags", 0>;
+
+// Segment registers
+def CS : X86Reg<"cs", 1>;
+def DS : X86Reg<"ds", 3>;
+def SS : X86Reg<"ss", 2>;
+def ES : X86Reg<"es", 0>;
+def FS : X86Reg<"fs", 4>;
+def GS : X86Reg<"gs", 5>;
+
+// Debug registers
+def DR0 : X86Reg<"dr0", 0>;
+def DR1 : X86Reg<"dr1", 1>;
+def DR2 : X86Reg<"dr2", 2>;
+def DR3 : X86Reg<"dr3", 3>;
+def DR4 : X86Reg<"dr4", 4>;
+def DR5 : X86Reg<"dr5", 5>;
+def DR6 : X86Reg<"dr6", 6>;
+def DR7 : X86Reg<"dr7", 7>;
+
+// Control registers
+def CR0 : X86Reg<"cr0", 0>;
+def CR1 : X86Reg<"cr1", 1>;
+def CR2 : X86Reg<"cr2", 2>;
+def CR3 : X86Reg<"cr3", 3>;
+def CR4 : X86Reg<"cr4", 4>;
+def CR5 : X86Reg<"cr5", 5>;
+def CR6 : X86Reg<"cr6", 6>;
+def CR7 : X86Reg<"cr7", 7>;
+def CR8 : X86Reg<"cr8", 8>;
+def CR9 : X86Reg<"cr9", 9>;
+def CR10 : X86Reg<"cr10", 10>;
+def CR11 : X86Reg<"cr11", 11>;
+def CR12 : X86Reg<"cr12", 12>;
+def CR13 : X86Reg<"cr13", 13>;
+def CR14 : X86Reg<"cr14", 14>;
+def CR15 : X86Reg<"cr15", 15>;
+
+// Pseudo index registers
+def EIZ : X86Reg<"eiz", 4>;
+def RIZ : X86Reg<"riz", 4>;
+
//===----------------------------------------------------------------------===//
// Register Class Definitions... now that we have all of the pieces, define the
Modified: llvm/branches/R600/lib/Target/X86/X86SelectionDAGInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86SelectionDAGInfo.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86SelectionDAGInfo.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/X86SelectionDAGInfo.cpp Thu Oct 11 16:28:00 2012
@@ -54,7 +54,7 @@
if (const char *bzeroEntry = V &&
V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
EVT IntPtr = TLI.getPointerTy();
- Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
+ Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
Entry.Node = Dst;
Modified: llvm/branches/R600/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86Subtarget.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/X86Subtarget.cpp Thu Oct 11 16:28:00 2012
@@ -163,17 +163,6 @@
return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
}
-/// getSpecialAddressLatency - For targets where it is beneficial to
-/// backschedule instructions that compute addresses, return a value
-/// indicating the number of scheduling cycles of backscheduling that
-/// should be attempted.
-unsigned X86Subtarget::getSpecialAddressLatency() const {
- // For x86 out-of-order targets, back-schedule address computations so
- // that loads and stores aren't blocked.
- // This value was chosen arbitrarily.
- return 200;
-}
-
void X86Subtarget::AutoDetectSubtargetFeatures() {
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
unsigned MaxLevel;
@@ -401,6 +390,10 @@
}
}
+ // CPUName may have been set by the CPU detection code. Make sure the
+ // new MCSchedModel is used.
+ InitMCProcessorInfo(CPUName, FS);
+
if (X86ProcFamily == IntelAtom)
PostRAScheduler = true;
Modified: llvm/branches/R600/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86Subtarget.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/branches/R600/lib/Target/X86/X86Subtarget.h Thu Oct 11 16:28:00 2012
@@ -237,10 +237,10 @@
bool isTargetSolaris() const {
return TargetTriple.getOS() == Triple::Solaris;
}
-
- // ELF is a reasonably sane default and the only other X86 targets we
- // support are Darwin and Windows. Just use "not those".
- bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
+ bool isTargetELF() const {
+ return (TargetTriple.getEnvironment() == Triple::ELF ||
+ TargetTriple.isOSBinFormatELF());
+ }
bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
bool isTargetNaCl() const {
return TargetTriple.getOS() == Triple::NativeClient;
@@ -251,7 +251,10 @@
bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
- bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
+ bool isTargetCOFF() const {
+ return (TargetTriple.getEnvironment() != Triple::ELF &&
+ TargetTriple.isOSBinFormatCOFF());
+ }
bool isTargetEnvMacho() const { return TargetTriple.isEnvironmentMachO(); }
bool isTargetWin64() const {
@@ -302,12 +305,6 @@
/// returns null.
const char *getBZeroEntry() const;
- /// getSpecialAddressLatency - For targets where it is beneficial to
- /// backschedule instructions that compute addresses, return a value
- /// indicating the number of scheduling cycles of backscheduling that
- /// should be attempted.
- unsigned getSpecialAddressLatency() const;
-
/// enablePostRAScheduler - run for Atom optimization.
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtargetInfo::AntiDepBreakMode& Mode,
Modified: llvm/branches/R600/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86TargetMachine.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/branches/R600/lib/Target/X86/X86TargetMachine.cpp Thu Oct 11 16:28:00 2012
@@ -36,7 +36,7 @@
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
- DataLayout(getSubtargetImpl()->isTargetDarwin() ?
+ DL(getSubtargetImpl()->isTargetDarwin() ?
"e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
"n8:16:32-S128" :
(getSubtargetImpl()->isTargetCygMing() ||
@@ -59,7 +59,7 @@
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL)
: X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
- DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
+ DL("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
"n8:16:32:64-S128"),
InstrInfo(*this),
TSInfo(*this),
@@ -113,6 +113,12 @@
cl::desc("Minimize AVX to SSE transition penalty"),
cl::init(true));
+// Temporary option to control early if-conversion for x86 while adding machine
+// models.
+static cl::opt<bool>
+X86EarlyIfConv("x86-early-ifcvt",
+ cl::desc("Enable early if-conversion on X86"));
+
//===----------------------------------------------------------------------===//
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
@@ -142,7 +148,7 @@
TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
X86PassConfig *PC = new X86PassConfig(this, PM);
- if (Subtarget.hasCMov())
+ if (X86EarlyIfConv && Subtarget.hasCMov())
PC->enablePass(&EarlyIfConverterID);
return PC;
Modified: llvm/branches/R600/lib/Target/X86/X86TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/X86/X86TargetMachine.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/X86/X86TargetMachine.h (original)
+++ llvm/branches/R600/lib/Target/X86/X86TargetMachine.h Thu Oct 11 16:28:00 2012
@@ -23,7 +23,7 @@
#include "X86SelectionDAGInfo.h"
#include "X86Subtarget.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetFrameLowering.h"
namespace llvm {
@@ -80,7 +80,7 @@
///
class X86_32TargetMachine : public X86TargetMachine {
virtual void anchor();
- const TargetData DataLayout; // Calculates type size & alignment
+ const DataLayout DL; // Calculates type size & alignment
X86InstrInfo InstrInfo;
X86SelectionDAGInfo TSInfo;
X86TargetLowering TLInfo;
@@ -90,7 +90,7 @@
StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
- virtual const TargetData *getTargetData() const { return &DataLayout; }
+ virtual const DataLayout *getDataLayout() const { return &DL; }
virtual const X86TargetLowering *getTargetLowering() const {
return &TLInfo;
}
@@ -109,7 +109,7 @@
///
class X86_64TargetMachine : public X86TargetMachine {
virtual void anchor();
- const TargetData DataLayout; // Calculates type size & alignment
+ const DataLayout DL; // Calculates type size & alignment
X86InstrInfo InstrInfo;
X86SelectionDAGInfo TSInfo;
X86TargetLowering TLInfo;
@@ -119,7 +119,7 @@
StringRef CPU, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
- virtual const TargetData *getTargetData() const { return &DataLayout; }
+ virtual const DataLayout *getDataLayout() const { return &DL; }
virtual const X86TargetLowering *getTargetLowering() const {
return &TLInfo;
}
Modified: llvm/branches/R600/lib/Target/XCore/XCoreAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/XCore/XCoreAsmPrinter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/XCore/XCoreAsmPrinter.cpp (original)
+++ llvm/branches/R600/lib/Target/XCore/XCoreAsmPrinter.cpp Thu Oct 11 16:28:00 2012
@@ -31,7 +31,7 @@
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/Mangler.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringExtras.h"
@@ -112,7 +112,7 @@
EmitSpecialLLVMGlobal(GV))
return;
- const TargetData *TD = TM.getTargetData();
+ const DataLayout *TD = TM.getDataLayout();
OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(GV, Mang,TM));
Modified: llvm/branches/R600/lib/Target/XCore/XCoreFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/XCore/XCoreFrameLowering.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/XCore/XCoreFrameLowering.cpp (original)
+++ llvm/branches/R600/lib/Target/XCore/XCoreFrameLowering.cpp Thu Oct 11 16:28:00 2012
@@ -23,7 +23,7 @@
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/ErrorHandling.h"
@@ -98,12 +98,13 @@
DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
bool FP = hasFP(MF);
- bool Nested = MF.getFunction()->
- getAttributes().hasAttrSomewhere(Attribute::Nest);
+ const AttrListPtr &PAL = MF.getFunction()->getAttributes();
- if (Nested) {
- loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII);
- }
+ for (unsigned I = 0, E = PAL.getNumAttrs(); I != E; ++I)
+ if (PAL.getAttributesAtIndex(I).hasAttribute(Attributes::Nest)) {
+ loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII);
+ break;
+ }
// Work out frame sizes.
int FrameSize = MFI->getStackSize();
Modified: llvm/branches/R600/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/XCore/XCoreISelLowering.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/branches/R600/lib/Target/XCore/XCoreISelLowering.cpp Thu Oct 11 16:28:00 2012
@@ -285,7 +285,7 @@
llvm_unreachable(0);
}
SDValue base = getGlobalAddressWrapper(GA, GV, DAG);
- const TargetData *TD = TM.getTargetData();
+ const DataLayout *TD = TM.getDataLayout();
unsigned Size = TD->getTypeAllocSize(Ty);
SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl),
DAG.getConstant(Size, MVT::i32));
@@ -405,7 +405,7 @@
if (allowsUnalignedMemoryAccesses(LD->getMemoryVT()))
return SDValue();
- unsigned ABIAlignment = getTargetData()->
+ unsigned ABIAlignment = getDataLayout()->
getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
// Leave aligned load alone.
if (LD->getAlignment() >= ABIAlignment)
@@ -477,7 +477,7 @@
}
// Lower to a call to __misaligned_load(BasePtr).
- Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
+ Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
@@ -507,7 +507,7 @@
if (allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
return SDValue();
}
- unsigned ABIAlignment = getTargetData()->
+ unsigned ABIAlignment = getDataLayout()->
getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
// Leave aligned store alone.
if (ST->getAlignment() >= ABIAlignment) {
@@ -536,7 +536,7 @@
}
// Lower to a call to __misaligned_store(BasePtr, Value).
- Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
+ Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
@@ -1499,7 +1499,7 @@
if (StoreBits % 8) {
break;
}
- unsigned ABIAlignment = getTargetData()->getABITypeAlignment(
+ unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(
ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext()));
unsigned Alignment = ST->getAlignment();
if (Alignment >= ABIAlignment) {
@@ -1570,7 +1570,7 @@
if (Ty->getTypeID() == Type::VoidTyID)
return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
- const TargetData *TD = TM.getTargetData();
+ const DataLayout *TD = TM.getDataLayout();
unsigned Size = TD->getTypeAllocSize(Ty);
if (AM.BaseGV) {
return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
Modified: llvm/branches/R600/lib/Target/XCore/XCoreTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/XCore/XCoreTargetMachine.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/XCore/XCoreTargetMachine.cpp (original)
+++ llvm/branches/R600/lib/Target/XCore/XCoreTargetMachine.cpp Thu Oct 11 16:28:00 2012
@@ -27,7 +27,7 @@
CodeGenOpt::Level OL)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS),
- DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
+ DL("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-"
"i16:16:32-i32:32:32-i64:32:32-n32"),
InstrInfo(),
FrameLowering(Subtarget),
Modified: llvm/branches/R600/lib/Target/XCore/XCoreTargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/XCore/XCoreTargetMachine.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/XCore/XCoreTargetMachine.h (original)
+++ llvm/branches/R600/lib/Target/XCore/XCoreTargetMachine.h Thu Oct 11 16:28:00 2012
@@ -20,13 +20,13 @@
#include "XCoreISelLowering.h"
#include "XCoreSelectionDAGInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
namespace llvm {
class XCoreTargetMachine : public LLVMTargetMachine {
XCoreSubtarget Subtarget;
- const TargetData DataLayout; // Calculates type size & alignment
+ const DataLayout DL; // Calculates type size & alignment
XCoreInstrInfo InstrInfo;
XCoreFrameLowering FrameLowering;
XCoreTargetLowering TLInfo;
@@ -53,7 +53,7 @@
virtual const TargetRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
- virtual const TargetData *getTargetData() const { return &DataLayout; }
+ virtual const DataLayout *getDataLayout() const { return &DL; }
// Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
Modified: llvm/branches/R600/lib/Transforms/IPO/ArgumentPromotion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/IPO/ArgumentPromotion.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/IPO/ArgumentPromotion.cpp (original)
+++ llvm/branches/R600/lib/Transforms/IPO/ArgumentPromotion.cpp Thu Oct 11 16:28:00 2012
@@ -153,7 +153,8 @@
SmallPtrSet<Argument*, 8> ArgsToPromote;
SmallPtrSet<Argument*, 8> ByValArgsToTransform;
for (unsigned i = 0; i != PointerArgs.size(); ++i) {
- bool isByVal = F->paramHasAttr(PointerArgs[i].second+1, Attribute::ByVal);
+ bool isByVal=F->getParamAttributes(PointerArgs[i].second+1).
+ hasAttribute(Attributes::ByVal);
Argument *PtrArg = PointerArgs[i].first;
Type *AgTy = cast<PointerType>(PtrArg->getType())->getElementType();
Modified: llvm/branches/R600/lib/Transforms/IPO/ConstantMerge.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/IPO/ConstantMerge.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/IPO/ConstantMerge.cpp (original)
+++ llvm/branches/R600/lib/Transforms/IPO/ConstantMerge.cpp Thu Oct 11 16:28:00 2012
@@ -23,7 +23,7 @@
#include "llvm/DerivedTypes.h"
#include "llvm/Module.h"
#include "llvm/Pass.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/PointerIntPair.h"
#include "llvm/ADT/SmallPtrSet.h"
@@ -50,7 +50,7 @@
// alignment to a concrete value.
unsigned getAlignment(GlobalVariable *GV) const;
- const TargetData *TD;
+ const DataLayout *TD;
};
}
@@ -98,7 +98,7 @@
}
bool ConstantMerge::runOnModule(Module &M) {
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
// Find all the globals that are marked "used". These cannot be merged.
SmallPtrSet<const GlobalValue*, 8> UsedGlobals;
@@ -107,7 +107,7 @@
// Map unique <constants, has-unknown-alignment> pairs to globals. We don't
// want to merge globals of unknown alignment with those of explicit
- // alignment. If we have TargetData, we always know the alignment.
+ // alignment. If we have DataLayout, we always know the alignment.
DenseMap<PointerIntPair<Constant*, 1, bool>, GlobalVariable*> CMap;
// Replacements - This vector contains a list of replacements to perform.
Modified: llvm/branches/R600/lib/Transforms/IPO/DeadArgumentElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/IPO/DeadArgumentElimination.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/IPO/DeadArgumentElimination.cpp (original)
+++ llvm/branches/R600/lib/Transforms/IPO/DeadArgumentElimination.cpp Thu Oct 11 16:28:00 2012
@@ -21,7 +21,9 @@
#include "llvm/Transforms/IPO.h"
#include "llvm/CallingConv.h"
#include "llvm/Constant.h"
+#include "llvm/DebugInfo.h"
#include "llvm/DerivedTypes.h"
+#include "llvm/DIBuilder.h"
#include "llvm/Instructions.h"
#include "llvm/IntrinsicInst.h"
#include "llvm/LLVMContext.h"
@@ -30,6 +32,7 @@
#include "llvm/Support/CallSite.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
@@ -121,6 +124,15 @@
typedef SmallVector<RetOrArg, 5> UseVector;
+ // Map each LLVM function to corresponding metadata with debug info. If
+ // the function is replaced with another one, we should patch the pointer
+ // to LLVM function in metadata.
+ // As the code generation for module is finished (and DIBuilder is
+ // finalized) we assume that subprogram descriptors won't be changed, and
+ // they are stored in map for short duration anyway.
+ typedef DenseMap<Function*, DISubprogram> FunctionDIMap;
+ FunctionDIMap FunctionDIs;
+
protected:
// DAH uses this to specify a different ID.
explicit DAE(char &ID) : ModulePass(ID) {}
@@ -141,6 +153,7 @@
unsigned RetValNum = 0);
Liveness SurveyUses(const Value *V, UseVector &MaybeLiveUses);
+ void CollectFunctionDIs(Module &M);
void SurveyFunction(const Function &F);
void MarkValue(const RetOrArg &RA, Liveness L,
const UseVector &MaybeLiveUses);
@@ -180,6 +193,33 @@
ModulePass *llvm::createDeadArgEliminationPass() { return new DAE(); }
ModulePass *llvm::createDeadArgHackingPass() { return new DAH(); }
+/// CollectFunctionDIs - Map each function in the module to its debug info
+/// descriptor.
+void DAE::CollectFunctionDIs(Module &M) {
+ FunctionDIs.clear();
+
+ for (Module::named_metadata_iterator I = M.named_metadata_begin(),
+ E = M.named_metadata_end(); I != E; ++I) {
+ NamedMDNode &NMD = *I;
+ for (unsigned MDIndex = 0, MDNum = NMD.getNumOperands();
+ MDIndex < MDNum; ++MDIndex) {
+ MDNode *Node = NMD.getOperand(MDIndex);
+ if (!DIDescriptor(Node).isCompileUnit())
+ continue;
+ DICompileUnit CU(Node);
+ const DIArray &SPs = CU.getSubprograms();
+ for (unsigned SPIndex = 0, SPNum = SPs.getNumElements();
+ SPIndex < SPNum; ++SPIndex) {
+ DISubprogram SP(SPs.getElement(SPIndex));
+ if (!SP.Verify())
+ continue;
+ if (Function *F = SP.getFunction())
+ FunctionDIs[F] = SP;
+ }
+ }
+ }
+}
+
/// DeleteDeadVarargs - If this is an function that takes a ... list, and if
/// llvm.vastart is never called, the varargs list is dead for the function.
bool DAE::DeleteDeadVarargs(Function &Fn) {
@@ -284,6 +324,11 @@
I2->takeName(I);
}
+ // Patch the pointer to LLVM function in debug info descriptor.
+ FunctionDIMap::iterator DI = FunctionDIs.find(&Fn);
+ if (DI != FunctionDIs.end())
+ DI->second.replaceFunction(NF);
+
// Finally, nuke the old function.
Fn.eraseFromParent();
return true;
@@ -749,7 +794,7 @@
}
}
- if (FnAttrs != Attribute::None)
+ if (FnAttrs.hasAttributes())
AttributesVec.push_back(AttributeWithIndex::get(~0, FnAttrs));
// Reconstruct the AttributesList based on the vector we constructed.
@@ -811,7 +856,7 @@
AttributesVec.push_back(AttributeWithIndex::get(Args.size(), Attrs));
}
- if (FnAttrs != Attribute::None)
+ if (FnAttrs.hasAttributes())
AttributesVec.push_back(AttributeWithIndex::get(~0, FnAttrs));
// Reconstruct the AttributesList based on the vector we constructed.
@@ -952,6 +997,11 @@
BB->getInstList().erase(RI);
}
+ // Patch the pointer to LLVM function in debug info descriptor.
+ FunctionDIMap::iterator DI = FunctionDIs.find(F);
+ if (DI != FunctionDIs.end())
+ DI->second.replaceFunction(NF);
+
// Now that the old function is dead, delete it.
F->eraseFromParent();
@@ -961,6 +1011,9 @@
bool DAE::runOnModule(Module &M) {
bool Changed = false;
+ // Collect debug info descriptors for functions.
+ CollectFunctionDIs(M);
+
// First pass: Do a simple check to see if any functions can have their "..."
// removed. We can do this if they never call va_start. This loop cannot be
// fused with the next loop, because deleting a function invalidates
Modified: llvm/branches/R600/lib/Transforms/IPO/FunctionAttrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/IPO/FunctionAttrs.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/IPO/FunctionAttrs.cpp (original)
+++ llvm/branches/R600/lib/Transforms/IPO/FunctionAttrs.cpp Thu Oct 11 16:28:00 2012
@@ -212,10 +212,15 @@
MadeChange = true;
// Clear out any existing attributes.
- F->removeAttribute(~0, Attribute::ReadOnly | Attribute::ReadNone);
+ Attributes::Builder B;
+ B.addAttribute(Attributes::ReadOnly)
+ .addAttribute(Attributes::ReadNone);
+ F->removeAttribute(~0, Attributes::get(B));
// Add in the new attribute.
- F->addAttribute(~0, ReadsMemory? Attribute::ReadOnly : Attribute::ReadNone);
+ B.clear();
+ B.addAttribute(ReadsMemory ? Attributes::ReadOnly : Attributes::ReadNone);
+ F->addAttribute(~0, Attributes::get(B));
if (ReadsMemory)
++NumReadOnly;
@@ -276,8 +281,6 @@
void tooManyUses() { Captured = true; }
- bool shouldExplore(Use *U) { return true; }
-
bool captured(Use *U) {
CallSite CS(U->getUser());
if (!CS.getInstruction()) { Captured = true; return true; }
@@ -352,6 +355,9 @@
ArgumentGraph AG;
+ Attributes::Builder B;
+ B.addAttribute(Attributes::NoCapture);
+
// Check each function in turn, determining which pointer arguments are not
// captured.
for (CallGraphSCC::iterator I = SCC.begin(), E = SCC.end(); I != E; ++I) {
@@ -373,7 +379,7 @@
for (Function::arg_iterator A = F->arg_begin(), E = F->arg_end();
A != E; ++A) {
if (A->getType()->isPointerTy() && !A->hasNoCaptureAttr()) {
- A->addAttr(Attribute::NoCapture);
+ A->addAttr(Attributes::get(B));
++NumNoCapture;
Changed = true;
}
@@ -388,7 +394,7 @@
if (!Tracker.Captured) {
if (Tracker.Uses.empty()) {
// If it's trivially not captured, mark it nocapture now.
- A->addAttr(Attribute::NoCapture);
+ A->addAttr(Attributes::get(B));
++NumNoCapture;
Changed = true;
} else {
@@ -421,7 +427,7 @@
// eg. "void f(int* x) { if (...) f(x); }"
if (ArgumentSCC[0]->Uses.size() == 1 &&
ArgumentSCC[0]->Uses[0] == ArgumentSCC[0]) {
- ArgumentSCC[0]->Definition->addAttr(Attribute::NoCapture);
+ ArgumentSCC[0]->Definition->addAttr(Attributes::get(B));
++NumNoCapture;
Changed = true;
}
@@ -463,7 +469,7 @@
for (unsigned i = 0, e = ArgumentSCC.size(); i != e; ++i) {
Argument *A = ArgumentSCC[i]->Definition;
- A->addAttr(Attribute::NoCapture);
+ A->addAttr(Attributes::get(B));
++NumNoCapture;
Changed = true;
}
@@ -520,7 +526,7 @@
case Instruction::Call:
case Instruction::Invoke: {
CallSite CS(RVI);
- if (CS.paramHasAttr(0, Attribute::NoAlias))
+ if (CS.paramHasAttr(0, Attributes::NoAlias))
break;
if (CS.getCalledFunction() &&
SCCNodes.count(CS.getCalledFunction()))
Modified: llvm/branches/R600/lib/Transforms/IPO/GlobalOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/IPO/GlobalOpt.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/IPO/GlobalOpt.cpp (original)
+++ llvm/branches/R600/lib/Transforms/IPO/GlobalOpt.cpp Thu Oct 11 16:28:00 2012
@@ -25,7 +25,7 @@
#include "llvm/Pass.h"
#include "llvm/Analysis/ConstantFolding.h"
#include "llvm/Analysis/MemoryBuiltins.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Support/CallSite.h"
#include "llvm/Support/Debug.h"
@@ -83,7 +83,7 @@
const GlobalStatus &GS);
bool OptimizeEmptyGlobalCXXDtors(Function *CXAAtExitFn);
- TargetData *TD;
+ DataLayout *TD;
TargetLibraryInfo *TLI;
};
}
@@ -464,7 +464,7 @@
/// quick scan over the use list to clean up the easy and obvious cruft. This
/// returns true if it made a change.
static bool CleanupConstantGlobalUsers(Value *V, Constant *Init,
- TargetData *TD, TargetLibraryInfo *TLI) {
+ DataLayout *TD, TargetLibraryInfo *TLI) {
bool Changed = false;
for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;) {
User *U = *UI++;
@@ -656,7 +656,7 @@
/// behavior of the program in a more fine-grained way. We have determined that
/// this transformation is safe already. We return the first global variable we
/// insert so that the caller can reprocess it.
-static GlobalVariable *SRAGlobal(GlobalVariable *GV, const TargetData &TD) {
+static GlobalVariable *SRAGlobal(GlobalVariable *GV, const DataLayout &TD) {
// Make sure this global only has simple uses that we can SRA.
if (!GlobalUsersSafeToSRA(GV))
return 0;
@@ -932,7 +932,7 @@
/// if the loaded value is dynamically null, then we know that they cannot be
/// reachable with a null optimize away the load.
static bool OptimizeAwayTrappingUsesOfLoads(GlobalVariable *GV, Constant *LV,
- TargetData *TD,
+ DataLayout *TD,
TargetLibraryInfo *TLI) {
bool Changed = false;
@@ -996,7 +996,7 @@
/// ConstantPropUsersOf - Walk the use list of V, constant folding all of the
/// instructions that are foldable.
static void ConstantPropUsersOf(Value *V,
- TargetData *TD, TargetLibraryInfo *TLI) {
+ DataLayout *TD, TargetLibraryInfo *TLI) {
for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E; )
if (Instruction *I = dyn_cast<Instruction>(*UI++))
if (Constant *NewC = ConstantFoldInstruction(I, TD, TLI)) {
@@ -1019,7 +1019,7 @@
CallInst *CI,
Type *AllocTy,
ConstantInt *NElements,
- TargetData *TD,
+ DataLayout *TD,
TargetLibraryInfo *TLI) {
DEBUG(errs() << "PROMOTING GLOBAL: " << *GV << " CALL = " << *CI << '\n');
@@ -1468,7 +1468,7 @@
/// PerformHeapAllocSRoA - CI is an allocation of an array of structures. Break
/// it up into multiple allocations of arrays of the fields.
static GlobalVariable *PerformHeapAllocSRoA(GlobalVariable *GV, CallInst *CI,
- Value *NElems, TargetData *TD,
+ Value *NElems, DataLayout *TD,
const TargetLibraryInfo *TLI) {
DEBUG(dbgs() << "SROA HEAP ALLOC: " << *GV << " MALLOC = " << *CI << '\n');
Type *MAT = getMallocAllocatedType(CI, TLI);
@@ -1660,7 +1660,7 @@
Type *AllocTy,
AtomicOrdering Ordering,
Module::global_iterator &GVI,
- TargetData *TD,
+ DataLayout *TD,
TargetLibraryInfo *TLI) {
if (!TD)
return false;
@@ -1759,7 +1759,7 @@
static bool OptimizeOnceStoredGlobal(GlobalVariable *GV, Value *StoredOnceVal,
AtomicOrdering Ordering,
Module::global_iterator &GVI,
- TargetData *TD, TargetLibraryInfo *TLI) {
+ DataLayout *TD, TargetLibraryInfo *TLI) {
// Ignore no-op GEPs and bitcasts.
StoredOnceVal = StoredOnceVal->stripPointerCasts();
@@ -2002,7 +2002,7 @@
++NumMarked;
return true;
} else if (!GV->getInitializer()->getType()->isSingleValueType()) {
- if (TargetData *TD = getAnalysisIfAvailable<TargetData>())
+ if (DataLayout *TD = getAnalysisIfAvailable<DataLayout>())
if (GlobalVariable *FirstNewGV = SRAGlobal(GV, *TD)) {
GVI = FirstNewGV; // Don't skip the newly produced globals!
return true;
@@ -2062,12 +2062,15 @@
}
static AttrListPtr StripNest(const AttrListPtr &Attrs) {
+ Attributes::Builder B;
+ B.addAttribute(Attributes::Nest);
+
for (unsigned i = 0, e = Attrs.getNumSlots(); i != e; ++i) {
- if ((Attrs.getSlot(i).Attrs & Attribute::Nest) == 0)
+ if (!Attrs.getSlot(i).Attrs.hasAttribute(Attributes::Nest))
continue;
// There can be only one.
- return Attrs.removeAttr(Attrs.getSlot(i).Index, Attribute::Nest);
+ return Attrs.removeAttr(Attrs.getSlot(i).Index, Attributes::get(B));
}
return Attrs;
@@ -2108,7 +2111,7 @@
Changed = true;
}
- if (F->getAttributes().hasAttrSomewhere(Attribute::Nest) &&
+ if (F->getAttributes().hasAttrSomewhere(Attributes::Nest) &&
!F->hasAddressTaken()) {
// The function is not used by a trampoline intrinsic, so it is safe
// to remove the 'nest' attribute.
@@ -2256,7 +2259,7 @@
static inline bool
isSimpleEnoughValueToCommit(Constant *C,
SmallPtrSet<Constant*, 8> &SimpleConstants,
- const TargetData *TD);
+ const DataLayout *TD);
/// isSimpleEnoughValueToCommit - Return true if the specified constant can be
@@ -2269,7 +2272,7 @@
/// time.
static bool isSimpleEnoughValueToCommitHelper(Constant *C,
SmallPtrSet<Constant*, 8> &SimpleConstants,
- const TargetData *TD) {
+ const DataLayout *TD) {
// Simple integer, undef, constant aggregate zero, global addresses, etc are
// all supported.
if (C->getNumOperands() == 0 || isa<BlockAddress>(C) ||
@@ -2324,7 +2327,7 @@
static inline bool
isSimpleEnoughValueToCommit(Constant *C,
SmallPtrSet<Constant*, 8> &SimpleConstants,
- const TargetData *TD) {
+ const DataLayout *TD) {
// If we already checked this constant, we win.
if (!SimpleConstants.insert(C)) return true;
// Check the constant.
@@ -2455,7 +2458,7 @@
/// Once an evaluation call fails, the evaluation object should not be reused.
class Evaluator {
public:
- Evaluator(const TargetData *TD, const TargetLibraryInfo *TLI)
+ Evaluator(const DataLayout *TD, const TargetLibraryInfo *TLI)
: TD(TD), TLI(TLI) {
ValueStack.push_back(new DenseMap<Value*, Constant*>);
}
@@ -2536,7 +2539,7 @@
/// simple enough to live in a static initializer of a global.
SmallPtrSet<Constant*, 8> SimpleConstants;
- const TargetData *TD;
+ const DataLayout *TD;
const TargetLibraryInfo *TLI;
};
@@ -2874,7 +2877,7 @@
/// EvaluateStaticConstructor - Evaluate static constructors in the function, if
/// we can. Return true if we can, false otherwise.
-static bool EvaluateStaticConstructor(Function *F, const TargetData *TD,
+static bool EvaluateStaticConstructor(Function *F, const DataLayout *TD,
const TargetLibraryInfo *TLI) {
// Call the function.
Evaluator Eval(TD, TLI);
@@ -3115,7 +3118,7 @@
bool GlobalOpt::runOnModule(Module &M) {
bool Changed = false;
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
TLI = &getAnalysis<TargetLibraryInfo>();
// Try to find the llvm.globalctors list.
Modified: llvm/branches/R600/lib/Transforms/IPO/InlineAlways.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/IPO/InlineAlways.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/IPO/InlineAlways.cpp (original)
+++ llvm/branches/R600/lib/Transforms/IPO/InlineAlways.cpp Thu Oct 11 16:28:00 2012
@@ -23,7 +23,7 @@
#include "llvm/Support/CallSite.h"
#include "llvm/Transforms/IPO.h"
#include "llvm/Transforms/IPO/InlinerPass.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/ADT/SmallPtrSet.h"
using namespace llvm;
@@ -65,7 +65,7 @@
/// \brief Minimal filter to detect invalid constructs for inlining.
static bool isInlineViable(Function &F) {
- bool ReturnsTwice = F.getFnAttributes().hasReturnsTwiceAttr();
+ bool ReturnsTwice =F.getFnAttributes().hasAttribute(Attributes::ReturnsTwice);
for (Function::iterator BI = F.begin(), BE = F.end(); BI != BE; ++BI) {
// Disallow inlining of functions which contain an indirect branch.
if (isa<IndirectBrInst>(BI->getTerminator()))
@@ -114,7 +114,7 @@
if (Callee->isDeclaration()) return InlineCost::getNever();
// Return never for anything not marked as always inline.
- if (!Callee->getFnAttributes().hasAlwaysInlineAttr())
+ if (!Callee->getFnAttributes().hasAttribute(Attributes::AlwaysInline))
return InlineCost::getNever();
// Do some minimal analysis to preclude non-viable functions.
Modified: llvm/branches/R600/lib/Transforms/IPO/InlineSimple.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/IPO/InlineSimple.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/IPO/InlineSimple.cpp (original)
+++ llvm/branches/R600/lib/Transforms/IPO/InlineSimple.cpp Thu Oct 11 16:28:00 2012
@@ -22,7 +22,7 @@
#include "llvm/Support/CallSite.h"
#include "llvm/Transforms/IPO.h"
#include "llvm/Transforms/IPO/InlinerPass.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
using namespace llvm;
@@ -62,7 +62,7 @@
// doInitialization - Initializes the vector of functions that have been
// annotated with the noinline attribute.
bool SimpleInliner::doInitialization(CallGraph &CG) {
- CA.setTargetData(getAnalysisIfAvailable<TargetData>());
+ CA.setDataLayout(getAnalysisIfAvailable<DataLayout>());
return false;
}
Modified: llvm/branches/R600/lib/Transforms/IPO/Inliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/IPO/Inliner.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/IPO/Inliner.cpp (original)
+++ llvm/branches/R600/lib/Transforms/IPO/Inliner.cpp Thu Oct 11 16:28:00 2012
@@ -19,7 +19,7 @@
#include "llvm/IntrinsicInst.h"
#include "llvm/Analysis/CallGraph.h"
#include "llvm/Analysis/InlineCost.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Transforms/IPO/InlinerPass.h"
#include "llvm/Transforms/Utils/Cloning.h"
@@ -93,11 +93,11 @@
// If the inlined function had a higher stack protection level than the
// calling function, then bump up the caller's stack protection level.
- if (Callee->getFnAttributes().hasStackProtectReqAttr())
- Caller->addFnAttr(Attribute::StackProtectReq);
- else if (Callee->getFnAttributes().hasStackProtectAttr() &&
- !Caller->getFnAttributes().hasStackProtectReqAttr())
- Caller->addFnAttr(Attribute::StackProtect);
+ if (Callee->getFnAttributes().hasAttribute(Attributes::StackProtectReq))
+ Caller->addFnAttr(Attributes::StackProtectReq);
+ else if (Callee->getFnAttributes().hasAttribute(Attributes::StackProtect) &&
+ !Caller->getFnAttributes().hasAttribute(Attributes::StackProtectReq))
+ Caller->addFnAttr(Attributes::StackProtect);
// Look at all of the allocas that we inlined through this call site. If we
// have already inlined other allocas through other calls into this function,
@@ -209,7 +209,7 @@
// would decrease the threshold.
Function *Caller = CS.getCaller();
bool OptSize = Caller && !Caller->isDeclaration() &&
- Caller->getFnAttributes().hasOptimizeForSizeAttr();
+ Caller->getFnAttributes().hasAttribute(Attributes::OptimizeForSize);
if (!(InlineLimit.getNumOccurrences() > 0) && OptSize &&
OptSizeThreshold < thres)
thres = OptSizeThreshold;
@@ -217,7 +217,7 @@
// Listen to the inlinehint attribute when it would increase the threshold.
Function *Callee = CS.getCalledFunction();
bool InlineHint = Callee && !Callee->isDeclaration() &&
- Callee->getFnAttributes().hasInlineHintAttr();
+ Callee->getFnAttributes().hasAttribute(Attributes::InlineHint);
if (InlineHint && HintThreshold > thres)
thres = HintThreshold;
@@ -340,7 +340,7 @@
bool Inliner::runOnSCC(CallGraphSCC &SCC) {
CallGraph &CG = getAnalysis<CallGraph>();
- const TargetData *TD = getAnalysisIfAvailable<TargetData>();
+ const DataLayout *TD = getAnalysisIfAvailable<DataLayout>();
const TargetLibraryInfo *TLI = getAnalysisIfAvailable<TargetLibraryInfo>();
SmallPtrSet<Function*, 8> SCCFunctions;
@@ -533,7 +533,8 @@
// Handle the case when this function is called and we only want to care
// about always-inline functions. This is a bit of a hack to share code
// between here and the InlineAlways pass.
- if (AlwaysInlineOnly && !F->getFnAttributes().hasAlwaysInlineAttr())
+ if (AlwaysInlineOnly &&
+ !F->getFnAttributes().hasAttribute(Attributes::AlwaysInline))
continue;
// If the only remaining users of the function are dead constants, remove
Modified: llvm/branches/R600/lib/Transforms/IPO/MergeFunctions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/IPO/MergeFunctions.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/IPO/MergeFunctions.cpp (original)
+++ llvm/branches/R600/lib/Transforms/IPO/MergeFunctions.cpp Thu Oct 11 16:28:00 2012
@@ -63,7 +63,7 @@
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/ValueHandle.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include <vector>
using namespace llvm;
@@ -92,19 +92,19 @@
namespace {
/// ComparableFunction - A struct that pairs together functions with a
-/// TargetData so that we can keep them together as elements in the DenseSet.
+/// DataLayout so that we can keep them together as elements in the DenseSet.
class ComparableFunction {
public:
static const ComparableFunction EmptyKey;
static const ComparableFunction TombstoneKey;
- static TargetData * const LookupOnly;
+ static DataLayout * const LookupOnly;
- ComparableFunction(Function *Func, TargetData *TD)
+ ComparableFunction(Function *Func, DataLayout *TD)
: Func(Func), Hash(profileFunction(Func)), TD(TD) {}
Function *getFunc() const { return Func; }
unsigned getHash() const { return Hash; }
- TargetData *getTD() const { return TD; }
+ DataLayout *getTD() const { return TD; }
// Drops AssertingVH reference to the function. Outside of debug mode, this
// does nothing.
@@ -120,13 +120,13 @@
AssertingVH<Function> Func;
unsigned Hash;
- TargetData *TD;
+ DataLayout *TD;
};
const ComparableFunction ComparableFunction::EmptyKey = ComparableFunction(0);
const ComparableFunction ComparableFunction::TombstoneKey =
ComparableFunction(1);
-TargetData *const ComparableFunction::LookupOnly = (TargetData*)(-1);
+DataLayout *const ComparableFunction::LookupOnly = (DataLayout*)(-1);
}
@@ -150,12 +150,12 @@
namespace {
/// FunctionComparator - Compares two functions to determine whether or not
-/// they will generate machine code with the same behaviour. TargetData is
+/// they will generate machine code with the same behaviour. DataLayout is
/// used if available. The comparator always fails conservatively (erring on the
/// side of claiming that two functions are different).
class FunctionComparator {
public:
- FunctionComparator(const TargetData *TD, const Function *F1,
+ FunctionComparator(const DataLayout *TD, const Function *F1,
const Function *F2)
: F1(F1), F2(F2), TD(TD) {}
@@ -190,7 +190,7 @@
// The two functions undergoing comparison.
const Function *F1, *F2;
- const TargetData *TD;
+ const DataLayout *TD;
DenseMap<const Value *, const Value *> id_map;
DenseSet<const Value *> seen_values;
@@ -591,8 +591,8 @@
/// to modify it.
FnSetType FnSet;
- /// TargetData for more accurate GEP comparisons. May be NULL.
- TargetData *TD;
+ /// DataLayout for more accurate GEP comparisons. May be NULL.
+ DataLayout *TD;
/// Whether or not the target supports global aliases.
bool HasGlobalAliases;
@@ -609,7 +609,7 @@
bool MergeFunctions::runOnModule(Module &M) {
bool Changed = false;
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) {
if (!I->isDeclaration() && !I->hasAvailableExternallyLinkage())
Modified: llvm/branches/R600/lib/Transforms/IPO/PruneEH.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/IPO/PruneEH.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/IPO/PruneEH.cpp (original)
+++ llvm/branches/R600/lib/Transforms/IPO/PruneEH.cpp Thu Oct 11 16:28:00 2012
@@ -137,16 +137,16 @@
// If the SCC doesn't unwind or doesn't throw, note this fact.
if (!SCCMightUnwind || !SCCMightReturn)
for (CallGraphSCC::iterator I = SCC.begin(), E = SCC.end(); I != E; ++I) {
- Attributes NewAttributes = Attribute::None;
+ Attributes::Builder NewAttributes;
if (!SCCMightUnwind)
- NewAttributes |= Attribute::NoUnwind;
+ NewAttributes.addAttribute(Attributes::NoUnwind);
if (!SCCMightReturn)
- NewAttributes |= Attribute::NoReturn;
+ NewAttributes.addAttribute(Attributes::NoReturn);
Function *F = (*I)->getFunction();
const AttrListPtr &PAL = F->getAttributes();
- const AttrListPtr &NPAL = PAL.addAttr(~0, NewAttributes);
+ const AttrListPtr &NPAL = PAL.addAttr(~0, Attributes::get(NewAttributes));
if (PAL != NPAL) {
MadeChange = true;
F->setAttributes(NPAL);
Modified: llvm/branches/R600/lib/Transforms/InstCombine/InstCombine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/InstCombine/InstCombine.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/InstCombine/InstCombine.h (original)
+++ llvm/branches/R600/lib/Transforms/InstCombine/InstCombine.h Thu Oct 11 16:28:00 2012
@@ -21,7 +21,7 @@
namespace llvm {
class CallSite;
- class TargetData;
+ class DataLayout;
class TargetLibraryInfo;
class DbgDeclareInst;
class MemIntrinsic;
@@ -71,7 +71,7 @@
class LLVM_LIBRARY_VISIBILITY InstCombiner
: public FunctionPass,
public InstVisitor<InstCombiner, Instruction*> {
- TargetData *TD;
+ DataLayout *TD;
TargetLibraryInfo *TLI;
bool MadeIRChange;
public:
@@ -95,7 +95,7 @@
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
- TargetData *getTargetData() const { return TD; }
+ DataLayout *getDataLayout() const { return TD; }
TargetLibraryInfo *getTargetLibraryInfo() const { return TLI; }
@@ -218,7 +218,7 @@
Type *Ty);
Instruction *visitCallSite(CallSite CS);
- Instruction *tryOptimizeCall(CallInst *CI, const TargetData *TD);
+ Instruction *tryOptimizeCall(CallInst *CI, const DataLayout *TD);
bool transformConstExprCastCall(CallSite CS);
Instruction *transformCallThroughTrampoline(CallSite CS,
IntrinsicInst *Tramp);
Modified: llvm/branches/R600/lib/Transforms/InstCombine/InstCombineAddSub.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/InstCombine/InstCombineAddSub.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/InstCombine/InstCombineAddSub.cpp (original)
+++ llvm/branches/R600/lib/Transforms/InstCombine/InstCombineAddSub.cpp Thu Oct 11 16:28:00 2012
@@ -13,7 +13,7 @@
#include "InstCombine.h"
#include "llvm/Analysis/InstructionSimplify.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Support/GetElementPtrTypeIterator.h"
#include "llvm/Support/PatternMatch.h"
using namespace llvm;
Modified: llvm/branches/R600/lib/Transforms/InstCombine/InstCombineCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/InstCombine/InstCombineCalls.cpp (original)
+++ llvm/branches/R600/lib/Transforms/InstCombine/InstCombineCalls.cpp Thu Oct 11 16:28:00 2012
@@ -13,7 +13,7 @@
#include "InstCombine.h"
#include "llvm/Support/CallSite.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Analysis/MemoryBuiltins.h"
#include "llvm/Transforms/Utils/BuildLibCalls.h"
#include "llvm/Transforms/Utils/Local.h"
@@ -754,7 +754,7 @@
/// passed through the varargs area, we can eliminate the use of the cast.
static bool isSafeToEliminateVarargsCast(const CallSite CS,
const CastInst * const CI,
- const TargetData * const TD,
+ const DataLayout * const TD,
const int ix) {
if (!CI->isLosslessCast())
return false;
@@ -812,7 +812,7 @@
// Currently we're only working with the checking functions, memcpy_chk,
// mempcpy_chk, memmove_chk, memset_chk, strcpy_chk, stpcpy_chk, strncpy_chk,
// strcat_chk and strncat_chk.
-Instruction *InstCombiner::tryOptimizeCall(CallInst *CI, const TargetData *TD) {
+Instruction *InstCombiner::tryOptimizeCall(CallInst *CI, const DataLayout *TD) {
if (CI->getCalledFunction() == 0) return 0;
InstCombineFortifiedLibCalls Simplifier(this);
@@ -984,7 +984,7 @@
Changed = true;
}
- // Try to optimize the call if possible, we require TargetData for most of
+ // Try to optimize the call if possible, we require DataLayout for most of
// this. None of these calls are seen as possibly dead so go ahead and
// delete the instruction now.
if (CallInst *CI = dyn_cast<CallInst>(CS.getInstruction())) {
@@ -1036,8 +1036,8 @@
return false; // Cannot transform this return value.
if (!CallerPAL.isEmpty() && !Caller->use_empty()) {
- Attributes RAttrs = CallerPAL.getRetAttributes();
- if (RAttrs & Attributes::typeIncompatible(NewRetTy))
+ Attributes::Builder RAttrs = CallerPAL.getRetAttributes();
+ if (RAttrs.hasAttributes(Attributes::typeIncompatible(NewRetTy)))
return false; // Attribute not compatible with transformed value.
}
@@ -1072,7 +1072,7 @@
// If the parameter is passed as a byval argument, then we have to have a
// sized type and the sized type has to have the same size as the old type.
- if (ParamTy != ActTy && (Attrs & Attribute::ByVal)) {
+ if (ParamTy != ActTy && Attrs.hasAttribute(Attributes::ByVal)) {
PointerType *ParamPTy = dyn_cast<PointerType>(ParamTy);
if (ParamPTy == 0 || !ParamPTy->getElementType()->isSized() || TD == 0)
return false;
@@ -1124,7 +1124,7 @@
if (CallerPAL.getSlot(i - 1).Index <= FT->getNumParams())
break;
Attributes PAttrs = CallerPAL.getSlot(i - 1).Attrs;
- if (PAttrs & Attribute::VarArgsIncompatible)
+ if (PAttrs.hasIncompatibleWithVarArgsAttrs())
return false;
}
@@ -1137,15 +1137,15 @@
attrVec.reserve(NumCommonArgs);
// Get any return attributes.
- Attributes RAttrs = CallerPAL.getRetAttributes();
+ Attributes::Builder RAttrs = CallerPAL.getRetAttributes();
// If the return value is not being used, the type may not be compatible
// with the existing attributes. Wipe out any problematic attributes.
- RAttrs &= ~Attributes::typeIncompatible(NewRetTy);
+ RAttrs.removeAttributes(Attributes::typeIncompatible(NewRetTy));
// Add the new return attributes.
- if (RAttrs)
- attrVec.push_back(AttributeWithIndex::get(0, RAttrs));
+ if (RAttrs.hasAttributes())
+ attrVec.push_back(AttributeWithIndex::get(0, Attributes::get(RAttrs)));
AI = CS.arg_begin();
for (unsigned i = 0; i != NumCommonArgs; ++i, ++AI) {
@@ -1263,8 +1263,9 @@
// If the call already has the 'nest' attribute somewhere then give up -
// otherwise 'nest' would occur twice after splicing in the chain.
- if (Attrs.hasAttrSomewhere(Attribute::Nest))
- return 0;
+ for (unsigned I = 0, E = Attrs.getNumAttrs(); I != E; ++I)
+ if (Attrs.getAttributesAtIndex(I).hasAttribute(Attributes::Nest))
+ return 0;
assert(Tramp &&
"transformCallThroughTrampoline called with incorrect CallSite.");
@@ -1277,12 +1278,12 @@
if (!NestAttrs.isEmpty()) {
unsigned NestIdx = 1;
Type *NestTy = 0;
- Attributes NestAttr = Attribute::None;
+ Attributes NestAttr;
// Look for a parameter marked with the 'nest' attribute.
for (FunctionType::param_iterator I = NestFTy->param_begin(),
E = NestFTy->param_end(); I != E; ++NestIdx, ++I)
- if (NestAttrs.paramHasAttr(NestIdx, Attribute::Nest)) {
+ if (NestAttrs.getParamAttributes(NestIdx).hasAttribute(Attributes::Nest)){
// Record the parameter type and any other attributes.
NestTy = *I;
NestAttr = NestAttrs.getParamAttributes(NestIdx);
Modified: llvm/branches/R600/lib/Transforms/InstCombine/InstCombineCasts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/InstCombine/InstCombineCasts.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/InstCombine/InstCombineCasts.cpp (original)
+++ llvm/branches/R600/lib/Transforms/InstCombine/InstCombineCasts.cpp Thu Oct 11 16:28:00 2012
@@ -13,7 +13,7 @@
#include "InstCombine.h"
#include "llvm/Analysis/ConstantFolding.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Support/PatternMatch.h"
using namespace llvm;
@@ -78,7 +78,7 @@
/// try to eliminate the cast by moving the type information into the alloc.
Instruction *InstCombiner::PromoteCastOfAllocation(BitCastInst &CI,
AllocaInst &AI) {
- // This requires TargetData to get the alloca alignment and size information.
+ // This requires DataLayout to get the alloca alignment and size information.
if (!TD) return 0;
PointerType *PTy = cast<PointerType>(CI.getType());
@@ -229,7 +229,7 @@
const CastInst *CI, ///< The first cast instruction
unsigned opcode, ///< The opcode of the second cast instruction
Type *DstTy, ///< The target type for the second cast instruction
- TargetData *TD ///< The target data for pointer size
+ DataLayout *TD ///< The target data for pointer size
) {
Type *SrcTy = CI->getOperand(0)->getType(); // A from above
Modified: llvm/branches/R600/lib/Transforms/InstCombine/InstCombineCompares.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/InstCombine/InstCombineCompares.cpp (original)
+++ llvm/branches/R600/lib/Transforms/InstCombine/InstCombineCompares.cpp Thu Oct 11 16:28:00 2012
@@ -16,7 +16,7 @@
#include "llvm/Analysis/ConstantFolding.h"
#include "llvm/Analysis/InstructionSimplify.h"
#include "llvm/Analysis/MemoryBuiltins.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Support/ConstantRange.h"
#include "llvm/Support/GetElementPtrTypeIterator.h"
@@ -474,7 +474,7 @@
/// If we can't emit an optimized form for this expression, this returns null.
///
static Value *EvaluateGEPOffsetExpression(User *GEP, InstCombiner &IC) {
- TargetData &TD = *IC.getTargetData();
+ DataLayout &TD = *IC.getDataLayout();
gep_type_iterator GTI = gep_type_begin(GEP);
// Check to see if this gep only has a single variable index. If so, and if
Modified: llvm/branches/R600/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp (original)
+++ llvm/branches/R600/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Thu Oct 11 16:28:00 2012
@@ -14,7 +14,7 @@
#include "InstCombine.h"
#include "llvm/IntrinsicInst.h"
#include "llvm/Analysis/Loads.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/ADT/Statistic.h"
@@ -152,7 +152,7 @@
/// getPointeeAlignment - Compute the minimum alignment of the value pointed
/// to by the given pointer.
-static unsigned getPointeeAlignment(Value *V, const TargetData &TD) {
+static unsigned getPointeeAlignment(Value *V, const DataLayout &TD) {
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V))
if (CE->getOpcode() == Instruction::BitCast ||
(CE->getOpcode() == Instruction::GetElementPtr &&
@@ -297,7 +297,7 @@
/// InstCombineLoadCast - Fold 'load (cast P)' -> cast (load P)' when possible.
static Instruction *InstCombineLoadCast(InstCombiner &IC, LoadInst &LI,
- const TargetData *TD) {
+ const DataLayout *TD) {
User *CI = cast<User>(LI.getOperand(0));
Value *CastOp = CI->getOperand(0);
@@ -327,14 +327,14 @@
SrcPTy = SrcTy->getElementType();
}
- if (IC.getTargetData() &&
+ if (IC.getDataLayout() &&
(SrcPTy->isIntegerTy() || SrcPTy->isPointerTy() ||
SrcPTy->isVectorTy()) &&
// Do not allow turning this into a load of an integer, which is then
// casted to a pointer, this pessimizes pointer analysis a lot.
(SrcPTy->isPointerTy() == LI.getType()->isPointerTy()) &&
- IC.getTargetData()->getTypeSizeInBits(SrcPTy) ==
- IC.getTargetData()->getTypeSizeInBits(DestPTy)) {
+ IC.getDataLayout()->getTypeSizeInBits(SrcPTy) ==
+ IC.getDataLayout()->getTypeSizeInBits(DestPTy)) {
// Okay, we are casting from one integer or pointer type to another of
// the same size. Instead of casting the pointer before the load, cast
@@ -512,11 +512,11 @@
// If the pointers point into different address spaces or if they point to
// values with different sizes, we can't do the transformation.
- if (!IC.getTargetData() ||
+ if (!IC.getDataLayout() ||
SrcTy->getAddressSpace() !=
cast<PointerType>(CI->getType())->getAddressSpace() ||
- IC.getTargetData()->getTypeSizeInBits(SrcPTy) !=
- IC.getTargetData()->getTypeSizeInBits(DestPTy))
+ IC.getDataLayout()->getTypeSizeInBits(SrcPTy) !=
+ IC.getDataLayout()->getTypeSizeInBits(DestPTy))
return 0;
// Okay, we are casting from one integer or pointer type to another of
Modified: llvm/branches/R600/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (original)
+++ llvm/branches/R600/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp Thu Oct 11 16:28:00 2012
@@ -37,7 +37,7 @@
if (match(V, m_LShr(m_OneUse(m_Shl(m_Value(PowerOf2), m_Value(A))),
m_Value(B))) &&
// The "1" can be any value known to be a power of 2.
- isPowerOfTwo(PowerOf2, IC.getTargetData())) {
+ isPowerOfTwo(PowerOf2, IC.getDataLayout())) {
A = IC.Builder->CreateSub(A, B);
return IC.Builder->CreateShl(PowerOf2, A);
}
@@ -46,7 +46,7 @@
// inexact. Similarly for <<.
if (BinaryOperator *I = dyn_cast<BinaryOperator>(V))
if (I->isLogicalShift() &&
- isPowerOfTwo(I->getOperand(0), IC.getTargetData())) {
+ isPowerOfTwo(I->getOperand(0), IC.getDataLayout())) {
// We know that this is an exact/nuw shift and that the input is a
// non-zero context as well.
if (Value *V2 = simplifyValueKnownNonZero(I->getOperand(0), IC)) {
Modified: llvm/branches/R600/lib/Transforms/InstCombine/InstCombinePHI.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/InstCombine/InstCombinePHI.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/InstCombine/InstCombinePHI.cpp (original)
+++ llvm/branches/R600/lib/Transforms/InstCombine/InstCombinePHI.cpp Thu Oct 11 16:28:00 2012
@@ -13,7 +13,7 @@
#include "InstCombine.h"
#include "llvm/Analysis/InstructionSimplify.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
Modified: llvm/branches/R600/lib/Transforms/InstCombine/InstCombineSelect.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/InstCombine/InstCombineSelect.cpp (original)
+++ llvm/branches/R600/lib/Transforms/InstCombine/InstCombineSelect.cpp Thu Oct 11 16:28:00 2012
@@ -287,7 +287,7 @@
/// SimplifyWithOpReplaced - See if V simplifies when its operand Op is
/// replaced with RepOp.
static Value *SimplifyWithOpReplaced(Value *V, Value *Op, Value *RepOp,
- const TargetData *TD,
+ const DataLayout *TD,
const TargetLibraryInfo *TLI) {
// Trivial replacement.
if (V == Op)
Modified: llvm/branches/R600/lib/Transforms/InstCombine/InstCombineShifts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/InstCombine/InstCombineShifts.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/InstCombine/InstCombineShifts.cpp (original)
+++ llvm/branches/R600/lib/Transforms/InstCombine/InstCombineShifts.cpp Thu Oct 11 16:28:00 2012
@@ -190,7 +190,7 @@
V = IC.Builder->CreateLShr(C, NumBits);
// If we got a constantexpr back, try to simplify it with TD info.
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V))
- V = ConstantFoldConstantExpression(CE, IC.getTargetData(),
+ V = ConstantFoldConstantExpression(CE, IC.getDataLayout(),
IC.getTargetLibraryInfo());
return V;
}
Modified: llvm/branches/R600/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (original)
+++ llvm/branches/R600/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Thu Oct 11 16:28:00 2012
@@ -14,7 +14,7 @@
#include "InstCombine.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/IntrinsicInst.h"
using namespace llvm;
Modified: llvm/branches/R600/lib/Transforms/InstCombine/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/InstCombine/InstructionCombining.cpp (original)
+++ llvm/branches/R600/lib/Transforms/InstCombine/InstructionCombining.cpp Thu Oct 11 16:28:00 2012
@@ -40,7 +40,7 @@
#include "llvm/Analysis/ConstantFolding.h"
#include "llvm/Analysis/InstructionSimplify.h"
#include "llvm/Analysis/MemoryBuiltins.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Support/CFG.h"
@@ -88,7 +88,7 @@
Value *InstCombiner::EmitGEPOffset(User *GEP) {
- return llvm::EmitGEPOffset(Builder, *getTargetData(), GEP);
+ return llvm::EmitGEPOffset(Builder, *getDataLayout(), GEP);
}
/// ShouldChangeType - Return true if it is desirable to convert a computation
@@ -1854,7 +1854,7 @@
static bool AddReachableCodeToWorklist(BasicBlock *BB,
SmallPtrSet<BasicBlock*, 64> &Visited,
InstCombiner &IC,
- const TargetData *TD,
+ const DataLayout *TD,
const TargetLibraryInfo *TLI) {
bool MadeIRChange = false;
SmallVector<BasicBlock*, 256> Worklist;
@@ -2120,7 +2120,7 @@
bool InstCombiner::runOnFunction(Function &F) {
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
TLI = &getAnalysis<TargetLibraryInfo>();
/// Builder - This is an IRBuilder that automatically inserts new
Modified: llvm/branches/R600/lib/Transforms/Instrumentation/AddressSanitizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Instrumentation/AddressSanitizer.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Instrumentation/AddressSanitizer.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Instrumentation/AddressSanitizer.cpp Thu Oct 11 16:28:00 2012
@@ -35,7 +35,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/system_error.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Transforms/Instrumentation.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
@@ -207,7 +207,7 @@
bool HasDynamicInitializer(GlobalVariable *G);
LLVMContext *C;
- TargetData *TD;
+ DataLayout *TD;
uint64_t MappingOffset;
int MappingScale;
size_t RedzoneSize;
@@ -736,7 +736,7 @@
// virtual
bool AddressSanitizer::runOnModule(Module &M) {
// Initialize the private fields. No one has accessed them before.
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
if (!TD)
return false;
BL.reset(new BlackList(ClBlackListFile));
@@ -854,12 +854,14 @@
// If needed, insert __asan_init before checking for AddressSafety attr.
maybeInsertAsanInitAtFunctionEntry(F);
- if (!F.getFnAttributes().hasAddressSafetyAttr()) return false;
+ if (!F.getFnAttributes().hasAttribute(Attributes::AddressSafety))
+ return false;
if (!ClDebugFunc.empty() && ClDebugFunc != F.getName())
return false;
- // We want to instrument every address only once per basic block
- // (unless there are calls between uses).
+
+ // We want to instrument every address only once per basic block (unless there
+ // are calls between uses).
SmallSet<Value*, 16> TempsToInstrument;
SmallVector<Instruction*, 16> ToInstrument;
SmallVector<Instruction*, 8> NoReturnCalls;
Modified: llvm/branches/R600/lib/Transforms/Instrumentation/BoundsChecking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Instrumentation/BoundsChecking.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Instrumentation/BoundsChecking.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Instrumentation/BoundsChecking.cpp Thu Oct 11 16:28:00 2012
@@ -23,7 +23,7 @@
#include "llvm/Support/InstIterator.h"
#include "llvm/Support/TargetFolder.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Transforms/Instrumentation.h"
using namespace llvm;
@@ -48,12 +48,12 @@
virtual bool runOnFunction(Function &F);
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
- AU.addRequired<TargetData>();
+ AU.addRequired<DataLayout>();
AU.addRequired<TargetLibraryInfo>();
}
private:
- const TargetData *TD;
+ const DataLayout *TD;
const TargetLibraryInfo *TLI;
ObjectSizeOffsetEvaluator *ObjSizeEval;
BuilderTy *Builder;
@@ -168,7 +168,7 @@
}
bool BoundsChecking::runOnFunction(Function &F) {
- TD = &getAnalysis<TargetData>();
+ TD = &getAnalysis<DataLayout>();
TLI = &getAnalysis<TargetLibraryInfo>();
TrapBB = 0;
Modified: llvm/branches/R600/lib/Transforms/Instrumentation/GCOVProfiling.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Instrumentation/GCOVProfiling.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Instrumentation/GCOVProfiling.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Instrumentation/GCOVProfiling.cpp Thu Oct 11 16:28:00 2012
@@ -682,7 +682,7 @@
"__llvm_gcov_init", M);
F->setUnnamedAddr(true);
F->setLinkage(GlobalValue::InternalLinkage);
- F->addFnAttr(Attribute::NoInline);
+ F->addFnAttr(Attributes::NoInline);
BB = BasicBlock::Create(*Ctx, "entry", F);
Builder.SetInsertPoint(BB);
@@ -701,7 +701,7 @@
cast<Function>(GCOVProfiler::getIncrementIndirectCounterFunc());
Fn->setUnnamedAddr(true);
Fn->setLinkage(GlobalValue::InternalLinkage);
- Fn->addFnAttr(Attribute::NoInline);
+ Fn->addFnAttr(Attributes::NoInline);
Type *Int32Ty = Type::getInt32Ty(*Ctx);
Type *Int64Ty = Type::getInt64Ty(*Ctx);
Modified: llvm/branches/R600/lib/Transforms/Instrumentation/ThreadSanitizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Instrumentation/ThreadSanitizer.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Instrumentation/ThreadSanitizer.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Instrumentation/ThreadSanitizer.cpp Thu Oct 11 16:28:00 2012
@@ -38,7 +38,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Transforms/Instrumentation.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/ModuleUtils.h"
@@ -47,6 +47,15 @@
static cl::opt<std::string> ClBlackListFile("tsan-blacklist",
cl::desc("Blacklist file"), cl::Hidden);
+static cl::opt<bool> ClInstrumentMemoryAccesses(
+ "tsan-instrument-memory-accesses", cl::init(true),
+ cl::desc("Instrument memory accesses"), cl::Hidden);
+static cl::opt<bool> ClInstrumentFuncEntryExit(
+ "tsan-instrument-func-entry-exit", cl::init(true),
+ cl::desc("Instrument function entry and exit"), cl::Hidden);
+static cl::opt<bool> ClInstrumentAtomics(
+ "tsan-instrument-atomics", cl::init(true),
+ cl::desc("Instrument atomics"), cl::Hidden);
STATISTIC(NumInstrumentedReads, "Number of instrumented reads");
STATISTIC(NumInstrumentedWrites, "Number of instrumented writes");
@@ -76,7 +85,7 @@
bool addrPointsToConstantData(Value *Addr);
int getMemoryAccessFuncIndex(Value *Addr);
- TargetData *TD;
+ DataLayout *TD;
OwningPtr<BlackList> BL;
IntegerType *OrdTy;
// Callbacks to run-time library are computed in doInitialization.
@@ -118,7 +127,7 @@
}
bool ThreadSanitizer::doInitialization(Module &M) {
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
if (!TD)
return false;
BL.reset(new BlackList(ClBlackListFile));
@@ -284,17 +293,19 @@
// (e.g. variables that do not escape, etc).
// Instrument memory accesses.
- for (size_t i = 0, n = AllLoadsAndStores.size(); i < n; ++i) {
- Res |= instrumentLoadOrStore(AllLoadsAndStores[i]);
- }
+ if (ClInstrumentMemoryAccesses)
+ for (size_t i = 0, n = AllLoadsAndStores.size(); i < n; ++i) {
+ Res |= instrumentLoadOrStore(AllLoadsAndStores[i]);
+ }
// Instrument atomic memory accesses.
- for (size_t i = 0, n = AtomicAccesses.size(); i < n; ++i) {
- Res |= instrumentAtomic(AtomicAccesses[i]);
- }
+ if (ClInstrumentAtomics)
+ for (size_t i = 0, n = AtomicAccesses.size(); i < n; ++i) {
+ Res |= instrumentAtomic(AtomicAccesses[i]);
+ }
// Instrument function entry/exit points if there were instrumented accesses.
- if (Res || HasCalls) {
+ if ((Res || HasCalls) && ClInstrumentFuncEntryExit) {
IRBuilder<> IRB(F.getEntryBlock().getFirstNonPHI());
Value *ReturnAddress = IRB.CreateCall(
Intrinsic::getDeclaration(F.getParent(), Intrinsic::returnaddress),
@@ -350,7 +361,8 @@
case AcquireRelease: v = 1 << 4; break;
case SequentiallyConsistent: v = 1 << 5; break;
}
- return IRB->getInt32(v);
+ // +100500 is temporal to migrate to new enum values.
+ return IRB->getInt32(v + 100500);
}
bool ThreadSanitizer::instrumentAtomic(Instruction *I) {
Modified: llvm/branches/R600/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/CodeGenPrepare.cpp Thu Oct 11 16:28:00 2012
@@ -38,7 +38,7 @@
#include "llvm/Support/PatternMatch.h"
#include "llvm/Support/ValueHandle.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Transforms/Utils/AddrModeMatcher.h"
@@ -149,14 +149,15 @@
TLInfo = &getAnalysis<TargetLibraryInfo>();
DT = getAnalysisIfAvailable<DominatorTree>();
PFI = getAnalysisIfAvailable<ProfileInfo>();
- OptSize = F.getFnAttributes().hasOptimizeForSizeAttr();
+ OptSize = F.getFnAttributes().hasAttribute(Attributes::OptimizeForSize);
/// This optimization identifies DIV instructions that can be
/// profitably bypassed and carried out with a shorter, faster divide.
if (TLI && TLI->isSlowDivBypassed()) {
- const DenseMap<Type*, Type*> &BypassTypeMap = TLI->getBypassSlowDivTypes();
+ const DenseMap<unsigned int, unsigned int> &BypassWidths =
+ TLI->getBypassSlowDivWidths();
for (Function::iterator I = F.begin(); I != F.end(); I++)
- EverMadeChange |= bypassSlowDivision(F, I, BypassTypeMap);
+ EverMadeChange |= bypassSlowDivision(F, I, BypassWidths);
}
// Eliminate blocks that contain only PHI nodes and an
@@ -622,7 +623,7 @@
// happens.
WeakVH IterHandle(CurInstIterator);
- replaceAndRecursivelySimplify(CI, RetVal, TLI ? TLI->getTargetData() : 0,
+ replaceAndRecursivelySimplify(CI, RetVal, TLI ? TLI->getDataLayout() : 0,
TLInfo, ModifiedDT ? 0 : DT);
// If the iterator instruction was recursively deleted, start over at the
@@ -646,8 +647,8 @@
// From here on out we're working with named functions.
if (CI->getCalledFunction() == 0) return false;
- // We'll need TargetData from here on out.
- const TargetData *TD = TLI ? TLI->getTargetData() : 0;
+ // We'll need DataLayout from here on out.
+ const DataLayout *TD = TLI ? TLI->getDataLayout() : 0;
if (!TD) return false;
// Lower all default uses of _chk calls. This is very similar
@@ -714,7 +715,8 @@
// See llvm::isInTailCallPosition().
const Function *F = BB->getParent();
Attributes CallerRetAttr = F->getAttributes().getRetAttributes();
- if ((CallerRetAttr & Attribute::ZExt) || (CallerRetAttr & Attribute::SExt))
+ if (CallerRetAttr.hasAttribute(Attributes::ZExt) ||
+ CallerRetAttr.hasAttribute(Attributes::SExt))
return false;
// Make sure there are no instructions between the PHI and return, or that the
@@ -772,7 +774,8 @@
// Conservatively require the attributes of the call to match those of the
// return. Ignore noalias because it doesn't affect the call sequence.
Attributes CalleeRetAttr = CS.getAttributes().getRetAttributes();
- if ((CalleeRetAttr ^ CallerRetAttr) & ~Attribute::NoAlias)
+ if (Attributes::Builder(CalleeRetAttr ^ CallerRetAttr)
+ .removeAttribute(Attributes::NoAlias).hasAttributes())
continue;
// Make sure the call instruction is followed by an unconditional branch to
@@ -929,7 +932,7 @@
DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode << " for "
<< *MemoryInst);
Type *IntPtrTy =
- TLI->getTargetData()->getIntPtrType(AccessTy->getContext());
+ TLI->getDataLayout()->getIntPtrType(AccessTy->getContext());
Value *Result = 0;
Modified: llvm/branches/R600/lib/Transforms/Scalar/ConstantProp.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/ConstantProp.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/ConstantProp.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/ConstantProp.cpp Thu Oct 11 16:28:00 2012
@@ -24,7 +24,7 @@
#include "llvm/Constant.h"
#include "llvm/Instruction.h"
#include "llvm/Pass.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Support/InstIterator.h"
#include "llvm/ADT/Statistic.h"
@@ -67,7 +67,7 @@
WorkList.insert(&*i);
}
bool Changed = false;
- TargetData *TD = getAnalysisIfAvailable<TargetData>();
+ DataLayout *TD = getAnalysisIfAvailable<DataLayout>();
TargetLibraryInfo *TLI = &getAnalysis<TargetLibraryInfo>();
while (!WorkList.empty()) {
Modified: llvm/branches/R600/lib/Transforms/Scalar/DeadStoreElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/DeadStoreElimination.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/DeadStoreElimination.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/DeadStoreElimination.cpp Thu Oct 11 16:28:00 2012
@@ -29,7 +29,7 @@
#include "llvm/Analysis/MemoryBuiltins.h"
#include "llvm/Analysis/MemoryDependenceAnalysis.h"
#include "llvm/Analysis/ValueTracking.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Support/Debug.h"
@@ -199,7 +199,7 @@
// If we don't have target data around, an unknown size in Location means
// that we should use the size of the pointee type. This isn't valid for
// memset/memcpy, which writes more than an i8.
- if (Loc.Size == AliasAnalysis::UnknownSize && AA.getTargetData() == 0)
+ if (Loc.Size == AliasAnalysis::UnknownSize && AA.getDataLayout() == 0)
return AliasAnalysis::Location();
return Loc;
}
@@ -213,7 +213,7 @@
// If we don't have target data around, an unknown size in Location means
// that we should use the size of the pointee type. This isn't valid for
// init.trampoline, which writes more than an i8.
- if (AA.getTargetData() == 0) return AliasAnalysis::Location();
+ if (AA.getDataLayout() == 0) return AliasAnalysis::Location();
// FIXME: We don't know the size of the trampoline, so we can't really
// handle it here.
@@ -318,7 +318,7 @@
static uint64_t getPointerSize(const Value *V, AliasAnalysis &AA) {
uint64_t Size;
- if (getObjectSize(V, Size, AA.getTargetData(), AA.getTargetLibraryInfo()))
+ if (getObjectSize(V, Size, AA.getDataLayout(), AA.getTargetLibraryInfo()))
return Size;
return AliasAnalysis::UnknownSize;
}
@@ -351,10 +351,10 @@
// comparison.
if (Later.Size == AliasAnalysis::UnknownSize ||
Earlier.Size == AliasAnalysis::UnknownSize) {
- // If we have no TargetData information around, then the size of the store
+ // If we have no DataLayout information around, then the size of the store
// is inferrable from the pointee type. If they are the same type, then
// we know that the store is safe.
- if (AA.getTargetData() == 0 &&
+ if (AA.getDataLayout() == 0 &&
Later.Ptr->getType() == Earlier.Ptr->getType())
return OverwriteComplete;
@@ -370,13 +370,13 @@
// larger than the earlier one.
if (Later.Size == AliasAnalysis::UnknownSize ||
Earlier.Size == AliasAnalysis::UnknownSize ||
- AA.getTargetData() == 0)
+ AA.getDataLayout() == 0)
return OverwriteUnknown;
// Check to see if the later store is to the entire object (either a global,
// an alloca, or a byval argument). If so, then it clearly overwrites any
// other store to the same object.
- const TargetData &TD = *AA.getTargetData();
+ const DataLayout &TD = *AA.getDataLayout();
const Value *UO1 = GetUnderlyingObject(P1, &TD),
*UO2 = GetUnderlyingObject(P2, &TD);
Modified: llvm/branches/R600/lib/Transforms/Scalar/EarlyCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/EarlyCSE.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/EarlyCSE.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/EarlyCSE.cpp Thu Oct 11 16:28:00 2012
@@ -18,11 +18,12 @@
#include "llvm/Pass.h"
#include "llvm/Analysis/Dominators.h"
#include "llvm/Analysis/InstructionSimplify.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/RecyclingAllocator.h"
+#include "llvm/ADT/Hashing.h"
#include "llvm/ADT/ScopedHashTable.h"
#include "llvm/ADT/Statistic.h"
#include <deque>
@@ -90,35 +91,56 @@
unsigned DenseMapInfo<SimpleValue>::getHashValue(SimpleValue Val) {
Instruction *Inst = Val.Inst;
-
// Hash in all of the operands as pointers.
- unsigned Res = 0;
- for (unsigned i = 0, e = Inst->getNumOperands(); i != e; ++i)
- Res ^= getHash(Inst->getOperand(i)) << (i & 0xF);
+ if (BinaryOperator* BinOp = dyn_cast<BinaryOperator>(Inst)) {
+ Value *LHS = BinOp->getOperand(0);
+ Value *RHS = BinOp->getOperand(1);
+ if (BinOp->isCommutative() && BinOp->getOperand(0) > BinOp->getOperand(1))
+ std::swap(LHS, RHS);
+
+ if (isa<OverflowingBinaryOperator>(BinOp)) {
+ // Hash the overflow behavior
+ unsigned Overflow =
+ BinOp->hasNoSignedWrap() * OverflowingBinaryOperator::NoSignedWrap |
+ BinOp->hasNoUnsignedWrap() * OverflowingBinaryOperator::NoUnsignedWrap;
+ return hash_combine(BinOp->getOpcode(), Overflow, LHS, RHS);
+ }
- if (CastInst *CI = dyn_cast<CastInst>(Inst))
- Res ^= getHash(CI->getType());
- else if (CmpInst *CI = dyn_cast<CmpInst>(Inst))
- Res ^= CI->getPredicate();
- else if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(Inst)) {
- for (ExtractValueInst::idx_iterator I = EVI->idx_begin(),
- E = EVI->idx_end(); I != E; ++I)
- Res ^= *I;
- } else if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(Inst)) {
- for (InsertValueInst::idx_iterator I = IVI->idx_begin(),
- E = IVI->idx_end(); I != E; ++I)
- Res ^= *I;
- } else {
- // nothing extra to hash in.
- assert((isa<CallInst>(Inst) ||
- isa<BinaryOperator>(Inst) || isa<GetElementPtrInst>(Inst) ||
- isa<SelectInst>(Inst) || isa<ExtractElementInst>(Inst) ||
- isa<InsertElementInst>(Inst) || isa<ShuffleVectorInst>(Inst)) &&
- "Invalid/unknown instruction");
+ return hash_combine(BinOp->getOpcode(), LHS, RHS);
}
+ if (CmpInst *CI = dyn_cast<CmpInst>(Inst)) {
+ Value *LHS = CI->getOperand(0);
+ Value *RHS = CI->getOperand(1);
+ CmpInst::Predicate Pred = CI->getPredicate();
+ if (Inst->getOperand(0) > Inst->getOperand(1)) {
+ std::swap(LHS, RHS);
+ Pred = CI->getSwappedPredicate();
+ }
+ return hash_combine(Inst->getOpcode(), Pred, LHS, RHS);
+ }
+
+ if (CastInst *CI = dyn_cast<CastInst>(Inst))
+ return hash_combine(CI->getOpcode(), CI->getType(), CI->getOperand(0));
+
+ if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(Inst))
+ return hash_combine(EVI->getOpcode(), EVI->getOperand(0),
+ hash_combine_range(EVI->idx_begin(), EVI->idx_end()));
+
+ if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(Inst))
+ return hash_combine(IVI->getOpcode(), IVI->getOperand(0),
+ IVI->getOperand(1),
+ hash_combine_range(IVI->idx_begin(), IVI->idx_end()));
+
+ assert((isa<CallInst>(Inst) || isa<BinaryOperator>(Inst) ||
+ isa<GetElementPtrInst>(Inst) || isa<SelectInst>(Inst) ||
+ isa<ExtractElementInst>(Inst) || isa<InsertElementInst>(Inst) ||
+ isa<ShuffleVectorInst>(Inst)) && "Invalid/unknown instruction");
+
// Mix in the opcode.
- return (Res << 1) ^ Inst->getOpcode();
+ return hash_combine(Inst->getOpcode(),
+ hash_combine_range(Inst->value_op_begin(),
+ Inst->value_op_end()));
}
bool DenseMapInfo<SimpleValue>::isEqual(SimpleValue LHS, SimpleValue RHS) {
@@ -128,7 +150,41 @@
return LHSI == RHSI;
if (LHSI->getOpcode() != RHSI->getOpcode()) return false;
- return LHSI->isIdenticalTo(RHSI);
+ if (LHSI->isIdenticalTo(RHSI)) return true;
+
+ // If we're not strictly identical, we still might be a commutable instruction
+ if (BinaryOperator *LHSBinOp = dyn_cast<BinaryOperator>(LHSI)) {
+ if (!LHSBinOp->isCommutative())
+ return false;
+
+ assert(isa<BinaryOperator>(RHSI)
+ && "same opcode, but different instruction type?");
+ BinaryOperator *RHSBinOp = cast<BinaryOperator>(RHSI);
+
+ // Check overflow attributes
+ if (isa<OverflowingBinaryOperator>(LHSBinOp)) {
+ assert(isa<OverflowingBinaryOperator>(RHSBinOp)
+ && "same opcode, but different operator type?");
+ if (LHSBinOp->hasNoUnsignedWrap() != RHSBinOp->hasNoUnsignedWrap() ||
+ LHSBinOp->hasNoSignedWrap() != RHSBinOp->hasNoSignedWrap())
+ return false;
+ }
+
+ // Commuted equality
+ return LHSBinOp->getOperand(0) == RHSBinOp->getOperand(1) &&
+ LHSBinOp->getOperand(1) == RHSBinOp->getOperand(0);
+ }
+ if (CmpInst *LHSCmp = dyn_cast<CmpInst>(LHSI)) {
+ assert(isa<CmpInst>(RHSI)
+ && "same opcode, but different instruction type?");
+ CmpInst *RHSCmp = cast<CmpInst>(RHSI);
+ // Commuted equality
+ return LHSCmp->getOperand(0) == RHSCmp->getOperand(1) &&
+ LHSCmp->getOperand(1) == RHSCmp->getOperand(0) &&
+ LHSCmp->getSwappedPredicate() == RHSCmp->getPredicate();
+ }
+
+ return false;
}
//===----------------------------------------------------------------------===//
@@ -216,7 +272,7 @@
/// cases.
class EarlyCSE : public FunctionPass {
public:
- const TargetData *TD;
+ const DataLayout *TD;
const TargetLibraryInfo *TLI;
DominatorTree *DT;
typedef RecyclingAllocator<BumpPtrAllocator,
@@ -508,7 +564,7 @@
bool EarlyCSE::runOnFunction(Function &F) {
std::deque<StackNode *> nodesToProcess;
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
TLI = &getAnalysis<TargetLibraryInfo>();
DT = &getAnalysis<DominatorTree>();
Modified: llvm/branches/R600/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/GVN.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/GVN.cpp Thu Oct 11 16:28:00 2012
@@ -41,7 +41,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/PatternMatch.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/SSAUpdater.h"
@@ -503,7 +503,7 @@
bool NoLoads;
MemoryDependenceAnalysis *MD;
DominatorTree *DT;
- const TargetData *TD;
+ const DataLayout *TD;
const TargetLibraryInfo *TLI;
ValueTable VN;
@@ -535,7 +535,7 @@
InstrsToErase.push_back(I);
}
- const TargetData *getTargetData() const { return TD; }
+ const DataLayout *getDataLayout() const { return TD; }
DominatorTree &getDominatorTree() const { return *DT; }
AliasAnalysis *getAliasAnalysis() const { return VN.getAliasAnalysis(); }
MemoryDependenceAnalysis &getMemDep() const { return *MD; }
@@ -730,7 +730,7 @@
/// CoerceAvailableValueToLoadType will succeed.
static bool CanCoerceMustAliasedValueToLoad(Value *StoredVal,
Type *LoadTy,
- const TargetData &TD) {
+ const DataLayout &TD) {
// If the loaded or stored value is an first class array or struct, don't try
// to transform them. We need to be able to bitcast to integer.
if (LoadTy->isStructTy() || LoadTy->isArrayTy() ||
@@ -756,7 +756,7 @@
static Value *CoerceAvailableValueToLoadType(Value *StoredVal,
Type *LoadedTy,
Instruction *InsertPt,
- const TargetData &TD) {
+ const DataLayout &TD) {
if (!CanCoerceMustAliasedValueToLoad(StoredVal, LoadedTy, TD))
return 0;
@@ -842,7 +842,7 @@
static int AnalyzeLoadFromClobberingWrite(Type *LoadTy, Value *LoadPtr,
Value *WritePtr,
uint64_t WriteSizeInBits,
- const TargetData &TD) {
+ const DataLayout &TD) {
// If the loaded or stored value is a first class array or struct, don't try
// to transform them. We need to be able to bitcast to integer.
if (LoadTy->isStructTy() || LoadTy->isArrayTy())
@@ -915,7 +915,7 @@
/// memdep query of a load that ends up being a clobbering store.
static int AnalyzeLoadFromClobberingStore(Type *LoadTy, Value *LoadPtr,
StoreInst *DepSI,
- const TargetData &TD) {
+ const DataLayout &TD) {
// Cannot handle reading from store of first-class aggregate yet.
if (DepSI->getValueOperand()->getType()->isStructTy() ||
DepSI->getValueOperand()->getType()->isArrayTy())
@@ -931,7 +931,7 @@
/// memdep query of a load that ends up being clobbered by another load. See if
/// the other load can feed into the second load.
static int AnalyzeLoadFromClobberingLoad(Type *LoadTy, Value *LoadPtr,
- LoadInst *DepLI, const TargetData &TD){
+ LoadInst *DepLI, const DataLayout &TD){
// Cannot handle reading from store of first-class aggregate yet.
if (DepLI->getType()->isStructTy() || DepLI->getType()->isArrayTy())
return -1;
@@ -959,7 +959,7 @@
static int AnalyzeLoadFromClobberingMemInst(Type *LoadTy, Value *LoadPtr,
MemIntrinsic *MI,
- const TargetData &TD) {
+ const DataLayout &TD) {
// If the mem operation is a non-constant size, we can't handle it.
ConstantInt *SizeCst = dyn_cast<ConstantInt>(MI->getLength());
if (SizeCst == 0) return -1;
@@ -1009,7 +1009,7 @@
/// before we give up.
static Value *GetStoreValueForLoad(Value *SrcVal, unsigned Offset,
Type *LoadTy,
- Instruction *InsertPt, const TargetData &TD){
+ Instruction *InsertPt, const DataLayout &TD){
LLVMContext &Ctx = SrcVal->getType()->getContext();
uint64_t StoreSize = (TD.getTypeSizeInBits(SrcVal->getType()) + 7) / 8;
@@ -1048,7 +1048,7 @@
static Value *GetLoadValueForLoad(LoadInst *SrcVal, unsigned Offset,
Type *LoadTy, Instruction *InsertPt,
GVN &gvn) {
- const TargetData &TD = *gvn.getTargetData();
+ const DataLayout &TD = *gvn.getDataLayout();
// If Offset+LoadTy exceeds the size of SrcVal, then we must be wanting to
// widen SrcVal out to a larger load.
unsigned SrcValSize = TD.getTypeStoreSize(SrcVal->getType());
@@ -1107,7 +1107,7 @@
/// memdep query of a load that ends up being a clobbering mem intrinsic.
static Value *GetMemInstValueForLoad(MemIntrinsic *SrcInst, unsigned Offset,
Type *LoadTy, Instruction *InsertPt,
- const TargetData &TD){
+ const DataLayout &TD){
LLVMContext &Ctx = LoadTy->getContext();
uint64_t LoadSize = TD.getTypeSizeInBits(LoadTy)/8;
@@ -1231,7 +1231,7 @@
if (isSimpleValue()) {
Res = getSimpleValue();
if (Res->getType() != LoadTy) {
- const TargetData *TD = gvn.getTargetData();
+ const DataLayout *TD = gvn.getDataLayout();
assert(TD && "Need target data to handle type mismatch case");
Res = GetStoreValueForLoad(Res, Offset, LoadTy, BB->getTerminator(),
*TD);
@@ -1253,7 +1253,7 @@
<< *Res << '\n' << "\n\n\n");
}
} else {
- const TargetData *TD = gvn.getTargetData();
+ const DataLayout *TD = gvn.getDataLayout();
assert(TD && "Need target data to handle type mismatch case");
Res = GetMemInstValueForLoad(getMemIntrinValue(), Offset,
LoadTy, BB->getTerminator(), *TD);
@@ -2295,7 +2295,7 @@
if (!NoLoads)
MD = &getAnalysis<MemoryDependenceAnalysis>();
DT = &getAnalysis<DominatorTree>();
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
TLI = &getAnalysis<TargetLibraryInfo>();
VN.setAliasAnalysis(&getAnalysis<AliasAnalysis>());
VN.setMemDep(MD);
Modified: llvm/branches/R600/lib/Transforms/Scalar/GlobalMerge.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/GlobalMerge.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/GlobalMerge.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/GlobalMerge.cpp Thu Oct 11 16:28:00 2012
@@ -62,7 +62,7 @@
#include "llvm/Intrinsics.h"
#include "llvm/Module.h"
#include "llvm/Pass.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/ADT/Statistic.h"
@@ -98,9 +98,9 @@
}
struct GlobalCmp {
- const TargetData *TD;
+ const DataLayout *TD;
- GlobalCmp(const TargetData *td) : TD(td) { }
+ GlobalCmp(const DataLayout *td) : TD(td) { }
bool operator()(const GlobalVariable *GV1, const GlobalVariable *GV2) {
Type *Ty1 = cast<PointerType>(GV1->getType())->getElementType();
@@ -119,7 +119,7 @@
bool GlobalMerge::doMerge(SmallVectorImpl<GlobalVariable*> &Globals,
Module &M, bool isConst) const {
- const TargetData *TD = TLI->getTargetData();
+ const DataLayout *TD = TLI->getDataLayout();
// FIXME: Infer the maximum possible offset depending on the actual users
// (these max offsets are different for the users inside Thumb or ARM
@@ -170,7 +170,7 @@
bool GlobalMerge::doInitialization(Module &M) {
SmallVector<GlobalVariable*, 16> Globals, ConstGlobals, BSSGlobals;
- const TargetData *TD = TLI->getTargetData();
+ const DataLayout *TD = TLI->getDataLayout();
unsigned MaxOffset = TLI->getMaximalGlobalOffset();
bool Changed = false;
Modified: llvm/branches/R600/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/IndVarSimplify.cpp Thu Oct 11 16:28:00 2012
@@ -43,7 +43,7 @@
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/SimplifyIndVar.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
@@ -68,7 +68,7 @@
LoopInfo *LI;
ScalarEvolution *SE;
DominatorTree *DT;
- TargetData *TD;
+ DataLayout *TD;
TargetLibraryInfo *TLI;
SmallVector<WeakVH, 16> DeadInsts;
@@ -597,13 +597,13 @@
class WideIVVisitor : public IVVisitor {
ScalarEvolution *SE;
- const TargetData *TD;
+ const DataLayout *TD;
public:
WideIVInfo WI;
WideIVVisitor(PHINode *NarrowIV, ScalarEvolution *SCEV,
- const TargetData *TData) :
+ const DataLayout *TData) :
SE(SCEV), TD(TData) { WI.NarrowIV = NarrowIV; }
// Implement the interface used by simplifyUsersOfIV.
@@ -1261,8 +1261,13 @@
if (!Phi)
return true;
+ // Do LFTR if PHI node is defined in the loop, but is *not* a counter.
+ int Idx = Phi->getBasicBlockIndex(L->getLoopLatch());
+ if (Idx < 0)
+ return true;
+
// Do LFTR if the exit condition's IV is *not* a simple counter.
- Value *IncV = Phi->getIncomingValueForBlock(L->getLoopLatch());
+ Value *IncV = Phi->getIncomingValue(Idx);
return Phi != getLoopPhiForCounter(IncV, L, DT);
}
@@ -1341,7 +1346,7 @@
/// could at least handle constant BECounts.
static PHINode *
FindLoopCounter(Loop *L, const SCEV *BECount,
- ScalarEvolution *SE, DominatorTree *DT, const TargetData *TD) {
+ ScalarEvolution *SE, DominatorTree *DT, const DataLayout *TD) {
uint64_t BCWidth = SE->getTypeSizeInBits(BECount->getType());
Value *Cond =
@@ -1698,7 +1703,7 @@
LI = &getAnalysis<LoopInfo>();
SE = &getAnalysis<ScalarEvolution>();
DT = &getAnalysis<DominatorTree>();
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
TLI = getAnalysisIfAvailable<TargetLibraryInfo>();
DeadInsts.clear();
Modified: llvm/branches/R600/lib/Transforms/Scalar/JumpThreading.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/JumpThreading.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/JumpThreading.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/JumpThreading.cpp Thu Oct 11 16:28:00 2012
@@ -23,7 +23,7 @@
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Transforms/Utils/SSAUpdater.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/DenseSet.h"
@@ -75,7 +75,7 @@
/// revectored to the false side of the second if.
///
class JumpThreading : public FunctionPass {
- TargetData *TD;
+ DataLayout *TD;
TargetLibraryInfo *TLI;
LazyValueInfo *LVI;
#ifdef NDEBUG
@@ -147,7 +147,7 @@
///
bool JumpThreading::runOnFunction(Function &F) {
DEBUG(dbgs() << "Jump threading on function '" << F.getName() << "'\n");
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
TLI = &getAnalysis<TargetLibraryInfo>();
LVI = &getAnalysis<LazyValueInfo>();
Modified: llvm/branches/R600/lib/Transforms/Scalar/LICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/LICM.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/LICM.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/LICM.cpp Thu Oct 11 16:28:00 2012
@@ -46,7 +46,7 @@
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Transforms/Utils/SSAUpdater.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Support/CFG.h"
#include "llvm/Support/CommandLine.h"
@@ -100,7 +100,7 @@
LoopInfo *LI; // Current LoopInfo
DominatorTree *DT; // Dominator Tree for the current Loop.
- TargetData *TD; // TargetData for constant folding.
+ DataLayout *TD; // DataLayout for constant folding.
TargetLibraryInfo *TLI; // TargetLibraryInfo for constant folding.
// State that is updated as we process loops.
@@ -207,7 +207,7 @@
AA = &getAnalysis<AliasAnalysis>();
DT = &getAnalysis<DominatorTree>();
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
TLI = &getAnalysis<TargetLibraryInfo>();
CurAST = new AliasSetTracker(*AA);
Modified: llvm/branches/R600/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/LoopIdiomRecognize.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/LoopIdiomRecognize.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/LoopIdiomRecognize.cpp Thu Oct 11 16:28:00 2012
@@ -54,7 +54,7 @@
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Transforms/Utils/Local.h"
using namespace llvm;
@@ -65,7 +65,7 @@
namespace {
class LoopIdiomRecognize : public LoopPass {
Loop *CurLoop;
- const TargetData *TD;
+ const DataLayout *TD;
DominatorTree *DT;
ScalarEvolution *SE;
TargetLibraryInfo *TLI;
@@ -199,7 +199,7 @@
return false;
// We require target data for now.
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
if (TD == 0) return false;
DT = &getAnalysis<DominatorTree>();
@@ -408,7 +408,7 @@
///
/// Note that we don't ever attempt to use memset_pattern8 or 4, because these
/// just replicate their input array and then pass on to memset_pattern16.
-static Constant *getMemSetPatternValue(Value *V, const TargetData &TD) {
+static Constant *getMemSetPatternValue(Value *V, const DataLayout &TD) {
// If the value isn't a constant, we can't promote it to being in a constant
// array. We could theoretically do a store to an alloca or something, but
// that doesn't seem worthwhile.
Modified: llvm/branches/R600/lib/Transforms/Scalar/LoopInstSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/LoopInstSimplify.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/LoopInstSimplify.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/LoopInstSimplify.cpp Thu Oct 11 16:28:00 2012
@@ -18,7 +18,7 @@
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/LoopPass.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/Utils/Local.h"
@@ -66,7 +66,7 @@
bool LoopInstSimplify::runOnLoop(Loop *L, LPPassManager &LPM) {
DominatorTree *DT = getAnalysisIfAvailable<DominatorTree>();
LoopInfo *LI = &getAnalysis<LoopInfo>();
- const TargetData *TD = getAnalysisIfAvailable<TargetData>();
+ const DataLayout *TD = getAnalysisIfAvailable<DataLayout>();
const TargetLibraryInfo *TLI = &getAnalysis<TargetLibraryInfo>();
SmallVector<BasicBlock*, 8> ExitBlocks;
Modified: llvm/branches/R600/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/LoopStrengthReduce.cpp Thu Oct 11 16:28:00 2012
@@ -54,7 +54,7 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "loop-reduce"
-#include "llvm/Transforms/Scalar.h"
+#include "llvm/AddressingMode.h"
#include "llvm/Constants.h"
#include "llvm/Instructions.h"
#include "llvm/IntrinsicInst.h"
@@ -64,6 +64,7 @@
#include "llvm/Analysis/LoopPass.h"
#include "llvm/Analysis/ScalarEvolutionExpander.h"
#include "llvm/Assembly/Writer.h"
+#include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/ADT/SmallBitVector.h"
@@ -225,7 +226,7 @@
struct Formula {
/// AM - This is used to represent complex addressing, as well as other kinds
/// of interesting uses.
- TargetLowering::AddrMode AM;
+ AddrMode AM;
/// BaseRegs - The list of "base" registers for this use. When this is
/// non-empty, AM.HasBaseReg should be set to true.
@@ -1269,7 +1270,7 @@
/// isLegalUse - Test whether the use described by AM is "legal", meaning it can
/// be completely folded into the user instruction at isel time. This includes
/// address-mode folding and special icmp tricks.
-static bool isLegalUse(const TargetLowering::AddrMode &AM,
+static bool isLegalUse(const AddrMode &AM,
LSRUse::KindType Kind, Type *AccessTy,
const TargetLowering *TLI) {
switch (Kind) {
@@ -1326,7 +1327,7 @@
llvm_unreachable("Invalid LSRUse Kind!");
}
-static bool isLegalUse(TargetLowering::AddrMode AM,
+static bool isLegalUse(AddrMode AM,
int64_t MinOffset, int64_t MaxOffset,
LSRUse::KindType Kind, Type *AccessTy,
const TargetLowering *TLI) {
@@ -1357,7 +1358,7 @@
// Conservatively, create an address with an immediate and a
// base and a scale.
- TargetLowering::AddrMode AM;
+ AddrMode AM;
AM.BaseOffs = BaseOffs;
AM.BaseGV = BaseGV;
AM.HasBaseReg = HasBaseReg;
@@ -1395,7 +1396,7 @@
// Conservatively, create an address with an immediate and a
// base and a scale.
- TargetLowering::AddrMode AM;
+ AddrMode AM;
AM.BaseOffs = BaseOffs;
AM.BaseGV = BaseGV;
AM.HasBaseReg = HasBaseReg;
@@ -2020,7 +2021,7 @@
goto decline_post_inc;
// Check for possible scaled-address reuse.
Type *AccessTy = getAccessType(UI->getUser());
- TargetLowering::AddrMode AM;
+ AddrMode AM;
AM.Scale = C->getSExtValue();
if (TLI->isLegalAddressingMode(AM, AccessTy))
goto decline_post_inc;
Modified: llvm/branches/R600/lib/Transforms/Scalar/LoopUnrollPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/LoopUnrollPass.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/LoopUnrollPass.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/LoopUnrollPass.cpp Thu Oct 11 16:28:00 2012
@@ -22,7 +22,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Transforms/Utils/UnrollLoop.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include <climits>
using namespace llvm;
@@ -113,7 +113,7 @@
/// ApproximateLoopSize - Approximate the size of the loop.
static unsigned ApproximateLoopSize(const Loop *L, unsigned &NumCalls,
- const TargetData *TD) {
+ const DataLayout *TD) {
CodeMetrics Metrics;
for (Loop::block_iterator I = L->block_begin(), E = L->block_end();
I != E; ++I)
@@ -145,7 +145,8 @@
// not user specified.
unsigned Threshold = CurrentThreshold;
if (!UserThreshold &&
- Header->getParent()->getFnAttributes().hasOptimizeForSizeAttr())
+ Header->getParent()->getFnAttributes().
+ hasAttribute(Attributes::OptimizeForSize))
Threshold = OptSizeUnrollThreshold;
// Find trip count and trip multiple if count is not available
@@ -178,7 +179,7 @@
// Enforce the threshold.
if (Threshold != NoThreshold) {
- const TargetData *TD = getAnalysisIfAvailable<TargetData>();
+ const DataLayout *TD = getAnalysisIfAvailable<DataLayout>();
unsigned NumInlineCandidates;
unsigned LoopSize = ApproximateLoopSize(L, NumInlineCandidates, TD);
DEBUG(dbgs() << " Loop Size = " << LoopSize << "\n");
Modified: llvm/branches/R600/lib/Transforms/Scalar/LoopUnswitch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/LoopUnswitch.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/LoopUnswitch.cpp Thu Oct 11 16:28:00 2012
@@ -638,7 +638,8 @@
// Check to see if it would be profitable to unswitch current loop.
// Do not do non-trivial unswitch while optimizing for size.
- if (OptimizeForSize || F->getFnAttributes().hasOptimizeForSizeAttr())
+ if (OptimizeForSize ||
+ F->getFnAttributes().hasAttribute(Attributes::OptimizeForSize))
return false;
UnswitchNontrivialCondition(LoopCond, Val, currentLoop);
Modified: llvm/branches/R600/lib/Transforms/Scalar/MemCpyOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/MemCpyOptimizer.cpp Thu Oct 11 16:28:00 2012
@@ -27,7 +27,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/GetElementPtrTypeIterator.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Transforms/Utils/Local.h"
#include <list>
@@ -39,7 +39,7 @@
STATISTIC(NumCpyToSet, "Number of memcpys converted to memset");
static int64_t GetOffsetFromIndex(const GEPOperator *GEP, unsigned Idx,
- bool &VariableIdxFound, const TargetData &TD){
+ bool &VariableIdxFound, const DataLayout &TD){
// Skip over the first indices.
gep_type_iterator GTI = gep_type_begin(GEP);
for (unsigned i = 1; i != Idx; ++i, ++GTI)
@@ -72,7 +72,7 @@
/// constant offset, and return that constant offset. For example, Ptr1 might
/// be &A[42], and Ptr2 might be &A[40]. In this case offset would be -8.
static bool IsPointerOffset(Value *Ptr1, Value *Ptr2, int64_t &Offset,
- const TargetData &TD) {
+ const DataLayout &TD) {
Ptr1 = Ptr1->stripPointerCasts();
Ptr2 = Ptr2->stripPointerCasts();
GEPOperator *GEP1 = dyn_cast<GEPOperator>(Ptr1);
@@ -141,12 +141,12 @@
/// TheStores - The actual stores that make up this range.
SmallVector<Instruction*, 16> TheStores;
- bool isProfitableToUseMemset(const TargetData &TD) const;
+ bool isProfitableToUseMemset(const DataLayout &TD) const;
};
} // end anon namespace
-bool MemsetRange::isProfitableToUseMemset(const TargetData &TD) const {
+bool MemsetRange::isProfitableToUseMemset(const DataLayout &TD) const {
// If we found more than 4 stores to merge or 16 bytes, use memset.
if (TheStores.size() >= 4 || End-Start >= 16) return true;
@@ -192,9 +192,9 @@
/// because each element is relatively large and expensive to copy.
std::list<MemsetRange> Ranges;
typedef std::list<MemsetRange>::iterator range_iterator;
- const TargetData &TD;
+ const DataLayout &TD;
public:
- MemsetRanges(const TargetData &td) : TD(td) {}
+ MemsetRanges(const DataLayout &td) : TD(td) {}
typedef std::list<MemsetRange>::const_iterator const_iterator;
const_iterator begin() const { return Ranges.begin(); }
@@ -302,7 +302,7 @@
class MemCpyOpt : public FunctionPass {
MemoryDependenceAnalysis *MD;
TargetLibraryInfo *TLI;
- const TargetData *TD;
+ const DataLayout *TD;
public:
static char ID; // Pass identification, replacement for typeid
MemCpyOpt() : FunctionPass(ID) {
@@ -332,7 +332,7 @@
bool processMemCpy(MemCpyInst *M);
bool processMemMove(MemMoveInst *M);
bool performCallSlotOptzn(Instruction *cpy, Value *cpyDst, Value *cpySrc,
- uint64_t cpyLen, CallInst *C);
+ uint64_t cpyLen, unsigned cpyAlign, CallInst *C);
bool processMemCpyMemCpyDependence(MemCpyInst *M, MemCpyInst *MDep,
uint64_t MSize);
bool processByValArgument(CallSite CS, unsigned ArgNo);
@@ -509,10 +509,18 @@
}
if (C) {
+ unsigned storeAlign = SI->getAlignment();
+ if (!storeAlign)
+ storeAlign = TD->getABITypeAlignment(SI->getOperand(0)->getType());
+ unsigned loadAlign = LI->getAlignment();
+ if (!loadAlign)
+ loadAlign = TD->getABITypeAlignment(LI->getType());
+
bool changed = performCallSlotOptzn(LI,
SI->getPointerOperand()->stripPointerCasts(),
LI->getPointerOperand()->stripPointerCasts(),
- TD->getTypeStoreSize(SI->getOperand(0)->getType()), C);
+ TD->getTypeStoreSize(SI->getOperand(0)->getType()),
+ std::min(storeAlign, loadAlign), C);
if (changed) {
MD->removeInstruction(SI);
SI->eraseFromParent();
@@ -559,7 +567,8 @@
/// the call write its result directly into the destination of the memcpy.
bool MemCpyOpt::performCallSlotOptzn(Instruction *cpy,
Value *cpyDest, Value *cpySrc,
- uint64_t cpyLen, CallInst *C) {
+ uint64_t cpyLen, unsigned cpyAlign,
+ CallInst *C) {
// The general transformation to keep in mind is
//
// call @func(..., src, ...)
@@ -625,6 +634,16 @@
return false;
}
+ // Check that dest points to memory that is at least as aligned as src.
+ unsigned srcAlign = srcAlloca->getAlignment();
+ if (!srcAlign)
+ srcAlign = TD->getABITypeAlignment(srcAlloca->getAllocatedType());
+ bool isDestSufficientlyAligned = srcAlign <= cpyAlign;
+ // If dest is not aligned enough and we can't increase its alignment then
+ // bail out.
+ if (!isDestSufficientlyAligned && !isa<AllocaInst>(cpyDest))
+ return false;
+
// Check that src is not accessed except via the call and the memcpy. This
// guarantees that it holds only undefined values when passed in (so the final
// memcpy can be dropped), that it is not read or written between the call and
@@ -673,20 +692,26 @@
bool changedArgument = false;
for (unsigned i = 0; i < CS.arg_size(); ++i)
if (CS.getArgument(i)->stripPointerCasts() == cpySrc) {
- if (cpySrc->getType() != cpyDest->getType())
- cpyDest = CastInst::CreatePointerCast(cpyDest, cpySrc->getType(),
- cpyDest->getName(), C);
+ Value *Dest = cpySrc->getType() == cpyDest->getType() ? cpyDest
+ : CastInst::CreatePointerCast(cpyDest, cpySrc->getType(),
+ cpyDest->getName(), C);
changedArgument = true;
- if (CS.getArgument(i)->getType() == cpyDest->getType())
- CS.setArgument(i, cpyDest);
+ if (CS.getArgument(i)->getType() == Dest->getType())
+ CS.setArgument(i, Dest);
else
- CS.setArgument(i, CastInst::CreatePointerCast(cpyDest,
- CS.getArgument(i)->getType(), cpyDest->getName(), C));
+ CS.setArgument(i, CastInst::CreatePointerCast(Dest,
+ CS.getArgument(i)->getType(), Dest->getName(), C));
}
if (!changedArgument)
return false;
+ // If the destination wasn't sufficiently aligned then increase its alignment.
+ if (!isDestSufficientlyAligned) {
+ assert(isa<AllocaInst>(cpyDest) && "Can only increase alloca alignment!");
+ cast<AllocaInst>(cpyDest)->setAlignment(srcAlign);
+ }
+
// Drop any cached information about the call, because we may have changed
// its dependence information by changing its parameter.
MD->removeInstruction(C);
@@ -813,7 +838,8 @@
if (DepInfo.isClobber()) {
if (CallInst *C = dyn_cast<CallInst>(DepInfo.getInst())) {
if (performCallSlotOptzn(M, M->getDest(), M->getSource(),
- CopySize->getZExtValue(), C)) {
+ CopySize->getZExtValue(), M->getAlignment(),
+ C)) {
MD->removeInstruction(M);
M->eraseFromParent();
return true;
@@ -974,7 +1000,7 @@
bool MemCpyOpt::runOnFunction(Function &F) {
bool MadeChange = false;
MD = &getAnalysis<MemoryDependenceAnalysis>();
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
TLI = &getAnalysis<TargetLibraryInfo>();
// If we don't have at least memset and memcpy, there is little point of doing
Modified: llvm/branches/R600/lib/Transforms/Scalar/ObjCARC.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/ObjCARC.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/ObjCARC.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/ObjCARC.cpp Thu Oct 11 16:28:00 2012
@@ -1788,7 +1788,9 @@
Type *I8X = PointerType::getUnqual(Type::getInt8Ty(C));
Type *Params[] = { I8X };
FunctionType *FTy = FunctionType::get(I8X, Params, /*isVarArg=*/false);
- AttrListPtr Attributes = AttrListPtr().addAttr(~0u, Attribute::NoUnwind);
+ Attributes::Builder B;
+ B.addAttribute(Attributes::NoUnwind);
+ AttrListPtr Attributes = AttrListPtr().addAttr(~0u, Attributes::get(B));
RetainRVCallee =
M->getOrInsertFunction("objc_retainAutoreleasedReturnValue", FTy,
Attributes);
@@ -1802,7 +1804,9 @@
Type *I8X = PointerType::getUnqual(Type::getInt8Ty(C));
Type *Params[] = { I8X };
FunctionType *FTy = FunctionType::get(I8X, Params, /*isVarArg=*/false);
- AttrListPtr Attributes = AttrListPtr().addAttr(~0u, Attribute::NoUnwind);
+ Attributes::Builder B;
+ B.addAttribute(Attributes::NoUnwind);
+ AttrListPtr Attributes = AttrListPtr().addAttr(~0u, Attributes::get(B));
AutoreleaseRVCallee =
M->getOrInsertFunction("objc_autoreleaseReturnValue", FTy,
Attributes);
@@ -1814,7 +1818,9 @@
if (!ReleaseCallee) {
LLVMContext &C = M->getContext();
Type *Params[] = { PointerType::getUnqual(Type::getInt8Ty(C)) };
- AttrListPtr Attributes = AttrListPtr().addAttr(~0u, Attribute::NoUnwind);
+ Attributes::Builder B;
+ B.addAttribute(Attributes::NoUnwind);
+ AttrListPtr Attributes = AttrListPtr().addAttr(~0u, Attributes::get(B));
ReleaseCallee =
M->getOrInsertFunction(
"objc_release",
@@ -1828,7 +1834,9 @@
if (!RetainCallee) {
LLVMContext &C = M->getContext();
Type *Params[] = { PointerType::getUnqual(Type::getInt8Ty(C)) };
- AttrListPtr Attributes = AttrListPtr().addAttr(~0u, Attribute::NoUnwind);
+ Attributes::Builder B;
+ B.addAttribute(Attributes::NoUnwind);
+ AttrListPtr Attributes = AttrListPtr().addAttr(~0u, Attributes::get(B));
RetainCallee =
M->getOrInsertFunction(
"objc_retain",
@@ -1857,7 +1865,9 @@
if (!AutoreleaseCallee) {
LLVMContext &C = M->getContext();
Type *Params[] = { PointerType::getUnqual(Type::getInt8Ty(C)) };
- AttrListPtr Attributes = AttrListPtr().addAttr(~0u, Attribute::NoUnwind);
+ Attributes::Builder B;
+ B.addAttribute(Attributes::NoUnwind);
+ AttrListPtr Attributes = AttrListPtr().addAttr(~0u, Attributes::get(B));
AutoreleaseCallee =
M->getOrInsertFunction(
"objc_autorelease",
@@ -3830,9 +3840,13 @@
Type *I8XX = PointerType::getUnqual(I8X);
Type *Params[] = { I8XX, I8X };
+ Attributes::Builder BNoUnwind;
+ BNoUnwind.addAttribute(Attributes::NoUnwind);
+ Attributes::Builder BNoCapture;
+ BNoCapture.addAttribute(Attributes::NoCapture);
AttrListPtr Attributes = AttrListPtr()
- .addAttr(~0u, Attribute::NoUnwind)
- .addAttr(1, Attribute::NoCapture);
+ .addAttr(~0u, Attributes::get(BNoUnwind))
+ .addAttr(1, Attributes::get(BNoCapture));
StoreStrongCallee =
M->getOrInsertFunction(
@@ -3849,7 +3863,9 @@
Type *I8X = PointerType::getUnqual(Type::getInt8Ty(C));
Type *Params[] = { I8X };
FunctionType *FTy = FunctionType::get(I8X, Params, /*isVarArg=*/false);
- AttrListPtr Attributes = AttrListPtr().addAttr(~0u, Attribute::NoUnwind);
+ Attributes::Builder B;
+ B.addAttribute(Attributes::NoUnwind);
+ AttrListPtr Attributes = AttrListPtr().addAttr(~0u, Attributes::get(B));
RetainAutoreleaseCallee =
M->getOrInsertFunction("objc_retainAutorelease", FTy, Attributes);
}
@@ -3862,7 +3878,9 @@
Type *I8X = PointerType::getUnqual(Type::getInt8Ty(C));
Type *Params[] = { I8X };
FunctionType *FTy = FunctionType::get(I8X, Params, /*isVarArg=*/false);
- AttrListPtr Attributes = AttrListPtr().addAttr(~0u, Attribute::NoUnwind);
+ Attributes::Builder B;
+ B.addAttribute(Attributes::NoUnwind);
+ AttrListPtr Attributes = AttrListPtr().addAttr(~0u, Attributes::get(B));
RetainAutoreleaseRVCallee =
M->getOrInsertFunction("objc_retainAutoreleaseReturnValue", FTy,
Attributes);
Modified: llvm/branches/R600/lib/Transforms/Scalar/SCCP.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/SCCP.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/SCCP.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/SCCP.cpp Thu Oct 11 16:28:00 2012
@@ -26,7 +26,7 @@
#include "llvm/Pass.h"
#include "llvm/Analysis/ConstantFolding.h"
#include "llvm/Transforms/Utils/Local.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Support/CallSite.h"
#include "llvm/Support/Debug.h"
@@ -153,7 +153,7 @@
/// Constant Propagation.
///
class SCCPSolver : public InstVisitor<SCCPSolver> {
- const TargetData *TD;
+ const DataLayout *TD;
const TargetLibraryInfo *TLI;
SmallPtrSet<BasicBlock*, 8> BBExecutable; // The BBs that are executable.
DenseMap<Value*, LatticeVal> ValueState; // The state each value is in.
@@ -205,7 +205,7 @@
typedef std::pair<BasicBlock*, BasicBlock*> Edge;
DenseSet<Edge> KnownFeasibleEdges;
public:
- SCCPSolver(const TargetData *td, const TargetLibraryInfo *tli)
+ SCCPSolver(const DataLayout *td, const TargetLibraryInfo *tli)
: TD(td), TLI(tli) {}
/// MarkBlockExecutable - This method can be used by clients to mark all of
@@ -1564,7 +1564,7 @@
//
bool SCCP::runOnFunction(Function &F) {
DEBUG(dbgs() << "SCCP on function '" << F.getName() << "'\n");
- const TargetData *TD = getAnalysisIfAvailable<TargetData>();
+ const DataLayout *TD = getAnalysisIfAvailable<DataLayout>();
const TargetLibraryInfo *TLI = &getAnalysis<TargetLibraryInfo>();
SCCPSolver Solver(TD, TLI);
@@ -1693,7 +1693,7 @@
}
bool IPSCCP::runOnModule(Module &M) {
- const TargetData *TD = getAnalysisIfAvailable<TargetData>();
+ const DataLayout *TD = getAnalysisIfAvailable<DataLayout>();
const TargetLibraryInfo *TLI = &getAnalysis<TargetLibraryInfo>();
SCCPSolver Solver(TD, TLI);
Modified: llvm/branches/R600/lib/Transforms/Scalar/SROA.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/SROA.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/SROA.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/SROA.cpp Thu Oct 11 16:28:00 2012
@@ -51,7 +51,7 @@
#include "llvm/Support/InstVisitor.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Transforms/Utils/PromoteMemToReg.h"
#include "llvm/Transforms/Utils/SSAUpdater.h"
@@ -137,6 +137,23 @@
/// splittable and eagerly split them into scalar values.
bool IsSplittable;
+ /// \brief Test whether a partition has been marked as dead.
+ bool isDead() const {
+ if (BeginOffset == UINT64_MAX) {
+ assert(EndOffset == UINT64_MAX);
+ return true;
+ }
+ return false;
+ }
+
+ /// \brief Kill a partition.
+ /// This is accomplished by setting both its beginning and end offset to
+ /// the maximum possible value.
+ void kill() {
+ assert(!isDead() && "He's Dead, Jim!");
+ BeginOffset = EndOffset = UINT64_MAX;
+ }
+
Partition() : ByteRange(), IsSplittable() {}
Partition(uint64_t BeginOffset, uint64_t EndOffset, bool IsSplittable)
: ByteRange(BeginOffset, EndOffset), IsSplittable(IsSplittable) {}
@@ -152,7 +169,10 @@
/// intentionally overlap between various uses of the same partition.
struct PartitionUse : public ByteRange {
/// \brief The use in question. Provides access to both user and used value.
- Use* U;
+ ///
+ /// Note that this may be null if the partition use is *dead*, that is, it
+ /// should be ignored.
+ Use *U;
PartitionUse() : ByteRange(), U() {}
PartitionUse(uint64_t BeginOffset, uint64_t EndOffset, Use *U)
@@ -163,7 +183,7 @@
///
/// Construction does most of the work for partitioning the alloca. This
/// performs the necessary walks of users and builds a partitioning from it.
- AllocaPartitioning(const TargetData &TD, AllocaInst &AI);
+ AllocaPartitioning(const DataLayout &TD, AllocaInst &AI);
/// \brief Test whether a pointer to the allocation escapes our analysis.
///
@@ -194,16 +214,6 @@
use_iterator use_begin(const_iterator I) { return Uses[I - begin()].begin(); }
use_iterator use_end(unsigned Idx) { return Uses[Idx].end(); }
use_iterator use_end(const_iterator I) { return Uses[I - begin()].end(); }
- void use_push_back(unsigned Idx, const PartitionUse &PU) {
- Uses[Idx].push_back(PU);
- }
- void use_push_back(const_iterator I, const PartitionUse &PU) {
- Uses[I - begin()].push_back(PU);
- }
- void use_erase(unsigned Idx, use_iterator UI) { Uses[Idx].erase(UI); }
- void use_erase(const_iterator I, use_iterator UI) {
- Uses[I - begin()].erase(UI);
- }
typedef SmallVectorImpl<PartitionUse>::const_iterator const_use_iterator;
const_use_iterator use_begin(unsigned Idx) const { return Uses[Idx].begin(); }
@@ -214,6 +224,22 @@
const_use_iterator use_end(const_iterator I) const {
return Uses[I - begin()].end();
}
+
+ unsigned use_size(unsigned Idx) const { return Uses[Idx].size(); }
+ unsigned use_size(const_iterator I) const { return Uses[I - begin()].size(); }
+ const PartitionUse &getUse(unsigned PIdx, unsigned UIdx) const {
+ return Uses[PIdx][UIdx];
+ }
+ const PartitionUse &getUse(const_iterator I, unsigned UIdx) const {
+ return Uses[I - begin()][UIdx];
+ }
+
+ void use_push_back(unsigned Idx, const PartitionUse &PU) {
+ Uses[Idx].push_back(PU);
+ }
+ void use_push_back(const_iterator I, const PartitionUse &PU) {
+ Uses[I - begin()].push_back(PU);
+ }
/// @}
/// \brief Allow iterating the dead users for this alloca.
@@ -246,8 +272,16 @@
/// correctly represent. We stash extra data to help us untangle this
/// after the partitioning is complete.
struct MemTransferOffsets {
+ /// The destination begin and end offsets when the destination is within
+ /// this alloca. If the end offset is zero the destination is not within
+ /// this alloca.
uint64_t DestBegin, DestEnd;
+
+ /// The source begin and end offsets when the source is within this alloca.
+ /// If the end offset is zero, the source is not within this alloca.
uint64_t SourceBegin, SourceEnd;
+
+ /// Flag for whether an alloca is splittable.
bool IsSplittable;
};
MemTransferOffsets getMemTransferOffsets(MemTransferInst &II) const {
@@ -377,7 +411,7 @@
class AllocaPartitioning::BuilderBase
: public InstVisitor<DerivedT, RetT> {
public:
- BuilderBase(const TargetData &TD, AllocaInst &AI, AllocaPartitioning &P)
+ BuilderBase(const DataLayout &TD, AllocaInst &AI, AllocaPartitioning &P)
: TD(TD),
AllocSize(TD.getTypeAllocSize(AI.getAllocatedType())),
P(P) {
@@ -385,7 +419,7 @@
}
protected:
- const TargetData &TD;
+ const DataLayout &TD;
const uint64_t AllocSize;
AllocaPartitioning &P;
@@ -486,7 +520,7 @@
SmallDenseMap<Instruction *, unsigned> MemTransferPartitionMap;
public:
- PartitionBuilder(const TargetData &TD, AllocaInst &AI, AllocaPartitioning &P)
+ PartitionBuilder(const DataLayout &TD, AllocaInst &AI, AllocaPartitioning &P)
: BuilderBase<PartitionBuilder, bool>(TD, AI, P) {}
/// \brief Run the builder over the allocation.
@@ -546,14 +580,6 @@
EndOffset = AllocSize;
}
- // See if we can just add a user onto the last slot currently occupied.
- if (!P.Partitions.empty() &&
- P.Partitions.back().BeginOffset == BeginOffset &&
- P.Partitions.back().EndOffset == EndOffset) {
- P.Partitions.back().IsSplittable &= IsSplittable;
- return;
- }
-
Partition New(BeginOffset, EndOffset, IsSplittable);
P.Partitions.push_back(New);
}
@@ -634,33 +660,57 @@
// Only intrinsics with a constant length can be split.
Offsets.IsSplittable = Length;
- if (*U != II.getRawDest()) {
- assert(*U == II.getRawSource());
- Offsets.SourceBegin = Offset;
- Offsets.SourceEnd = Offset + Size;
- } else {
+ if (*U == II.getRawDest()) {
Offsets.DestBegin = Offset;
Offsets.DestEnd = Offset + Size;
}
+ if (*U == II.getRawSource()) {
+ Offsets.SourceBegin = Offset;
+ Offsets.SourceEnd = Offset + Size;
+ }
- insertUse(II, Offset, Size, Offsets.IsSplittable);
- unsigned NewIdx = P.Partitions.size() - 1;
+ // If we have set up end offsets for both the source and the destination,
+ // we have found both sides of this transfer pointing at the same alloca.
+ bool SeenBothEnds = Offsets.SourceEnd && Offsets.DestEnd;
+ if (SeenBothEnds && II.getRawDest() != II.getRawSource()) {
+ unsigned PrevIdx = MemTransferPartitionMap[&II];
+
+ // Check if the begin offsets match and this is a non-volatile transfer.
+ // In that case, we can completely elide the transfer.
+ if (!II.isVolatile() && Offsets.SourceBegin == Offsets.DestBegin) {
+ P.Partitions[PrevIdx].kill();
+ return true;
+ }
+
+ // Otherwise we have an offset transfer within the same alloca. We can't
+ // split those.
+ P.Partitions[PrevIdx].IsSplittable = Offsets.IsSplittable = false;
+ } else if (SeenBothEnds) {
+ // Handle the case where this exact use provides both ends of the
+ // operation.
+ assert(II.getRawDest() == II.getRawSource());
+
+ // For non-volatile transfers this is a no-op.
+ if (!II.isVolatile())
+ return true;
- SmallDenseMap<Instruction *, unsigned>::const_iterator PMI;
- bool Inserted = false;
- llvm::tie(PMI, Inserted)
- = MemTransferPartitionMap.insert(std::make_pair(&II, NewIdx));
- if (Offsets.IsSplittable &&
- (!Inserted || II.getRawSource() == II.getRawDest())) {
- // We've found a memory transfer intrinsic which refers to the alloca as
- // both a source and dest. This is detected either by direct equality of
- // the operand values, or when we visit the intrinsic twice due to two
- // different chains of values leading to it. We refuse to split these to
- // simplify splitting logic. If possible, SROA will still split them into
- // separate allocas and then re-analyze.
+ // Otherwise just suppress splitting.
Offsets.IsSplittable = false;
- P.Partitions[PMI->second].IsSplittable = false;
- P.Partitions[NewIdx].IsSplittable = false;
+ }
+
+
+ // Insert the use now that we've fixed up the splittable nature.
+ insertUse(II, Offset, Size, Offsets.IsSplittable);
+
+ // Setup the mapping from intrinsic to partition of we've not seen both
+ // ends of this transfer.
+ if (!SeenBothEnds) {
+ unsigned NewIdx = P.Partitions.size() - 1;
+ bool Inserted
+ = MemTransferPartitionMap.insert(std::make_pair(&II, NewIdx)).second;
+ assert(Inserted &&
+ "Already have intrinsic in map but haven't seen both ends");
+ (void)Inserted;
}
return true;
@@ -799,7 +849,7 @@
SmallPtrSet<Instruction *, 4> VisitedDeadInsts;
public:
- UseBuilder(const TargetData &TD, AllocaInst &AI, AllocaPartitioning &P)
+ UseBuilder(const DataLayout &TD, AllocaInst &AI, AllocaPartitioning &P)
: BuilderBase<UseBuilder>(TD, AI, P) {}
/// \brief Run the builder over the allocation.
@@ -904,6 +954,14 @@
void visitMemTransferInst(MemTransferInst &II) {
ConstantInt *Length = dyn_cast<ConstantInt>(II.getLength());
uint64_t Size = Length ? Length->getZExtValue() : AllocSize - Offset;
+ if (!Size)
+ return markAsDead(II);
+
+ MemTransferOffsets &Offsets = P.MemTransferInstData[&II];
+ if (!II.isVolatile() && Offsets.DestEnd && Offsets.SourceEnd &&
+ Offsets.DestBegin == Offsets.SourceBegin)
+ return markAsDead(II); // Skip identity transfers without side-effects.
+
insertUse(II, Offset, Size);
}
@@ -1002,7 +1060,7 @@
SplitEndOffset = std::max(SplitEndOffset, Partitions[j].EndOffset);
}
- Partitions[j].BeginOffset = Partitions[j].EndOffset = UINT64_MAX;
+ Partitions[j].kill();
++NumDeadPartitions;
++j;
}
@@ -1023,7 +1081,7 @@
if (New.BeginOffset != New.EndOffset)
Partitions.push_back(New);
// Mark the old one for removal.
- Partitions[i].BeginOffset = Partitions[i].EndOffset = UINT64_MAX;
+ Partitions[i].kill();
++NumDeadPartitions;
}
@@ -1050,15 +1108,14 @@
// replaced in the process.
std::sort(Partitions.begin(), Partitions.end());
if (NumDeadPartitions) {
- assert(Partitions.back().BeginOffset == UINT64_MAX);
- assert(Partitions.back().EndOffset == UINT64_MAX);
+ assert(Partitions.back().isDead());
assert((ptrdiff_t)NumDeadPartitions ==
std::count(Partitions.begin(), Partitions.end(), Partitions.back()));
}
Partitions.erase(Partitions.end() - NumDeadPartitions, Partitions.end());
}
-AllocaPartitioning::AllocaPartitioning(const TargetData &TD, AllocaInst &AI)
+AllocaPartitioning::AllocaPartitioning(const DataLayout &TD, AllocaInst &AI)
:
#ifndef NDEBUG
AI(AI),
@@ -1068,11 +1125,15 @@
if (!PB())
return;
- if (Partitions.size() > 1) {
- // Sort the uses. This arranges for the offsets to be in ascending order,
- // and the sizes to be in descending order.
- std::sort(Partitions.begin(), Partitions.end());
+ // Sort the uses. This arranges for the offsets to be in ascending order,
+ // and the sizes to be in descending order.
+ std::sort(Partitions.begin(), Partitions.end());
+ // Remove any partitions from the back which are marked as dead.
+ while (!Partitions.empty() && Partitions.back().isDead())
+ Partitions.pop_back();
+
+ if (Partitions.size() > 1) {
// Intersect splittability for all partitions with equal offsets and sizes.
// Then remove all but the first so that we have a sequence of non-equal but
// potentially overlapping partitions.
@@ -1102,6 +1163,8 @@
Type *AllocaPartitioning::getCommonType(iterator I) const {
Type *Ty = 0;
for (const_use_iterator UI = use_begin(I), UE = use_end(I); UI != UE; ++UI) {
+ if (!UI->U)
+ continue; // Skip dead uses.
if (isa<IntrinsicInst>(*UI->U->getUser()))
continue;
if (UI->BeginOffset != I->BeginOffset || UI->EndOffset != I->EndOffset)
@@ -1137,6 +1200,8 @@
StringRef Indent) const {
for (const_use_iterator UI = use_begin(I), UE = use_end(I);
UI != UE; ++UI) {
+ if (!UI->U)
+ continue; // Skip dead uses.
OS << Indent << " [" << UI->BeginOffset << "," << UI->EndOffset << ") "
<< "used by: " << *UI->U->getUser() << "\n";
if (MemTransferInst *II = dyn_cast<MemTransferInst>(UI->U->getUser())) {
@@ -1282,7 +1347,7 @@
const bool RequiresDomTree;
LLVMContext *C;
- const TargetData *TD;
+ const DataLayout *TD;
DominatorTree *DT;
/// \brief Worklist of alloca instructions to simplify.
@@ -1303,6 +1368,16 @@
/// uses as dead. Only used to guard insertion into DeadInsts.
SmallPtrSet<Instruction *, 4> DeadSplitInsts;
+ /// \brief Post-promotion worklist.
+ ///
+ /// Sometimes we discover an alloca which has a high probability of becoming
+ /// viable for SROA after a round of promotion takes place. In those cases,
+ /// the alloca is enqueued here for re-processing.
+ ///
+ /// Note that we have to be very careful to clear allocas out of this list in
+ /// the event they are deleted.
+ SetVector<AllocaInst *, SmallVector<AllocaInst *, 16> > PostPromotionWorklist;
+
/// \brief A collection of alloca instructions we can directly promote.
std::vector<AllocaInst *> PromotableAllocas;
@@ -1345,694 +1420,719 @@
INITIALIZE_PASS_END(SROA, "sroa", "Scalar Replacement Of Aggregates",
false, false)
-/// \brief Accumulate the constant offsets in a GEP into a single APInt offset.
-///
-/// If the provided GEP is all-constant, the total byte offset formed by the
-/// GEP is computed and Offset is set to it. If the GEP has any non-constant
-/// operands, the function returns false and the value of Offset is unmodified.
-static bool accumulateGEPOffsets(const TargetData &TD, GEPOperator &GEP,
- APInt &Offset) {
- APInt GEPOffset(Offset.getBitWidth(), 0);
- for (gep_type_iterator GTI = gep_type_begin(GEP), GTE = gep_type_end(GEP);
- GTI != GTE; ++GTI) {
- ConstantInt *OpC = dyn_cast<ConstantInt>(GTI.getOperand());
- if (!OpC)
- return false;
- if (OpC->isZero()) continue;
+namespace {
+/// \brief Visitor to speculate PHIs and Selects where possible.
+class PHIOrSelectSpeculator : public InstVisitor<PHIOrSelectSpeculator> {
+ // Befriend the base class so it can delegate to private visit methods.
+ friend class llvm::InstVisitor<PHIOrSelectSpeculator>;
- // Handle a struct index, which adds its field offset to the pointer.
- if (StructType *STy = dyn_cast<StructType>(*GTI)) {
- unsigned ElementIdx = OpC->getZExtValue();
- const StructLayout *SL = TD.getStructLayout(STy);
- GEPOffset += APInt(Offset.getBitWidth(),
- SL->getElementOffset(ElementIdx));
- continue;
- }
+ const DataLayout &TD;
+ AllocaPartitioning &P;
+ SROA &Pass;
- APInt TypeSize(Offset.getBitWidth(),
- TD.getTypeAllocSize(GTI.getIndexedType()));
- if (VectorType *VTy = dyn_cast<VectorType>(*GTI)) {
- assert((VTy->getScalarSizeInBits() % 8) == 0 &&
- "vector element size is not a multiple of 8, cannot GEP over it");
- TypeSize = VTy->getScalarSizeInBits() / 8;
- }
+public:
+ PHIOrSelectSpeculator(const DataLayout &TD, AllocaPartitioning &P, SROA &Pass)
+ : TD(TD), P(P), Pass(Pass) {}
- GEPOffset += OpC->getValue().sextOrTrunc(Offset.getBitWidth()) * TypeSize;
+ /// \brief Visit the users of an alloca partition and rewrite them.
+ void visitUsers(AllocaPartitioning::const_iterator PI) {
+ // Note that we need to use an index here as the underlying vector of uses
+ // may be grown during speculation. However, we never need to re-visit the
+ // new uses, and so we can use the initial size bound.
+ for (unsigned Idx = 0, Size = P.use_size(PI); Idx != Size; ++Idx) {
+ const AllocaPartitioning::PartitionUse &PU = P.getUse(PI, Idx);
+ if (!PU.U)
+ continue; // Skip dead use.
+
+ visit(cast<Instruction>(PU.U->getUser()));
+ }
}
- Offset = GEPOffset;
- return true;
-}
-/// \brief Build a GEP out of a base pointer and indices.
-///
-/// This will return the BasePtr if that is valid, or build a new GEP
-/// instruction using the IRBuilder if GEP-ing is needed.
-static Value *buildGEP(IRBuilder<> &IRB, Value *BasePtr,
- SmallVectorImpl<Value *> &Indices,
- const Twine &Prefix) {
- if (Indices.empty())
- return BasePtr;
+private:
+ // By default, skip this instruction.
+ void visitInstruction(Instruction &I) {}
- // A single zero index is a no-op, so check for this and avoid building a GEP
- // in that case.
- if (Indices.size() == 1 && cast<ConstantInt>(Indices.back())->isZero())
- return BasePtr;
+ /// PHI instructions that use an alloca and are subsequently loaded can be
+ /// rewritten to load both input pointers in the pred blocks and then PHI the
+ /// results, allowing the load of the alloca to be promoted.
+ /// From this:
+ /// %P2 = phi [i32* %Alloca, i32* %Other]
+ /// %V = load i32* %P2
+ /// to:
+ /// %V1 = load i32* %Alloca -> will be mem2reg'd
+ /// ...
+ /// %V2 = load i32* %Other
+ /// ...
+ /// %V = phi [i32 %V1, i32 %V2]
+ ///
+ /// We can do this to a select if its only uses are loads and if the operands
+ /// to the select can be loaded unconditionally.
+ ///
+ /// FIXME: This should be hoisted into a generic utility, likely in
+ /// Transforms/Util/Local.h
+ bool isSafePHIToSpeculate(PHINode &PN, SmallVectorImpl<LoadInst *> &Loads) {
+ // For now, we can only do this promotion if the load is in the same block
+ // as the PHI, and if there are no stores between the phi and load.
+ // TODO: Allow recursive phi users.
+ // TODO: Allow stores.
+ BasicBlock *BB = PN.getParent();
+ unsigned MaxAlign = 0;
+ for (Value::use_iterator UI = PN.use_begin(), UE = PN.use_end();
+ UI != UE; ++UI) {
+ LoadInst *LI = dyn_cast<LoadInst>(*UI);
+ if (LI == 0 || !LI->isSimple()) return false;
- return IRB.CreateInBoundsGEP(BasePtr, Indices, Prefix + ".idx");
-}
+ // For now we only allow loads in the same block as the PHI. This is
+ // a common case that happens when instcombine merges two loads through
+ // a PHI.
+ if (LI->getParent() != BB) return false;
-/// \brief Get a natural GEP off of the BasePtr walking through Ty toward
-/// TargetTy without changing the offset of the pointer.
-///
-/// This routine assumes we've already established a properly offset GEP with
-/// Indices, and arrived at the Ty type. The goal is to continue to GEP with
-/// zero-indices down through type layers until we find one the same as
-/// TargetTy. If we can't find one with the same type, we at least try to use
-/// one with the same size. If none of that works, we just produce the GEP as
-/// indicated by Indices to have the correct offset.
-static Value *getNaturalGEPWithType(IRBuilder<> &IRB, const TargetData &TD,
- Value *BasePtr, Type *Ty, Type *TargetTy,
- SmallVectorImpl<Value *> &Indices,
- const Twine &Prefix) {
- if (Ty == TargetTy)
- return buildGEP(IRB, BasePtr, Indices, Prefix);
+ // Ensure that there are no instructions between the PHI and the load that
+ // could store.
+ for (BasicBlock::iterator BBI = &PN; &*BBI != LI; ++BBI)
+ if (BBI->mayWriteToMemory())
+ return false;
- // See if we can descend into a struct and locate a field with the correct
- // type.
- unsigned NumLayers = 0;
- Type *ElementTy = Ty;
- do {
- if (ElementTy->isPointerTy())
- break;
- if (SequentialType *SeqTy = dyn_cast<SequentialType>(ElementTy)) {
- ElementTy = SeqTy->getElementType();
- Indices.push_back(IRB.getInt(APInt(TD.getPointerSizeInBits(), 0)));
- } else if (StructType *STy = dyn_cast<StructType>(ElementTy)) {
- ElementTy = *STy->element_begin();
- Indices.push_back(IRB.getInt32(0));
- } else {
- break;
+ MaxAlign = std::max(MaxAlign, LI->getAlignment());
+ Loads.push_back(LI);
}
- ++NumLayers;
- } while (ElementTy != TargetTy);
- if (ElementTy != TargetTy)
- Indices.erase(Indices.end() - NumLayers, Indices.end());
- return buildGEP(IRB, BasePtr, Indices, Prefix);
-}
+ // We can only transform this if it is safe to push the loads into the
+ // predecessor blocks. The only thing to watch out for is that we can't put
+ // a possibly trapping load in the predecessor if it is a critical edge.
+ for (unsigned Idx = 0, Num = PN.getNumIncomingValues(); Idx != Num;
+ ++Idx) {
+ TerminatorInst *TI = PN.getIncomingBlock(Idx)->getTerminator();
+ Value *InVal = PN.getIncomingValue(Idx);
-/// \brief Recursively compute indices for a natural GEP.
-///
-/// This is the recursive step for getNaturalGEPWithOffset that walks down the
-/// element types adding appropriate indices for the GEP.
-static Value *getNaturalGEPRecursively(IRBuilder<> &IRB, const TargetData &TD,
- Value *Ptr, Type *Ty, APInt &Offset,
- Type *TargetTy,
- SmallVectorImpl<Value *> &Indices,
- const Twine &Prefix) {
- if (Offset == 0)
- return getNaturalGEPWithType(IRB, TD, Ptr, Ty, TargetTy, Indices, Prefix);
+ // If the value is produced by the terminator of the predecessor (an
+ // invoke) or it has side-effects, there is no valid place to put a load
+ // in the predecessor.
+ if (TI == InVal || TI->mayHaveSideEffects())
+ return false;
- // We can't recurse through pointer types.
- if (Ty->isPointerTy())
- return 0;
+ // If the predecessor has a single successor, then the edge isn't
+ // critical.
+ if (TI->getNumSuccessors() == 1)
+ continue;
- // We try to analyze GEPs over vectors here, but note that these GEPs are
- // extremely poorly defined currently. The long-term goal is to remove GEPing
- // over a vector from the IR completely.
- if (VectorType *VecTy = dyn_cast<VectorType>(Ty)) {
- unsigned ElementSizeInBits = VecTy->getScalarSizeInBits();
- if (ElementSizeInBits % 8)
- return 0; // GEPs over non-multiple of 8 size vector elements are invalid.
- APInt ElementSize(Offset.getBitWidth(), ElementSizeInBits / 8);
- APInt NumSkippedElements = Offset.udiv(ElementSize);
- if (NumSkippedElements.ugt(VecTy->getNumElements()))
- return 0;
- Offset -= NumSkippedElements * ElementSize;
- Indices.push_back(IRB.getInt(NumSkippedElements));
- return getNaturalGEPRecursively(IRB, TD, Ptr, VecTy->getElementType(),
- Offset, TargetTy, Indices, Prefix);
- }
+ // If this pointer is always safe to load, or if we can prove that there
+ // is already a load in the block, then we can move the load to the pred
+ // block.
+ if (InVal->isDereferenceablePointer() ||
+ isSafeToLoadUnconditionally(InVal, TI, MaxAlign, &TD))
+ continue;
- if (ArrayType *ArrTy = dyn_cast<ArrayType>(Ty)) {
- Type *ElementTy = ArrTy->getElementType();
- APInt ElementSize(Offset.getBitWidth(), TD.getTypeAllocSize(ElementTy));
- APInt NumSkippedElements = Offset.udiv(ElementSize);
- if (NumSkippedElements.ugt(ArrTy->getNumElements()))
- return 0;
+ return false;
+ }
- Offset -= NumSkippedElements * ElementSize;
- Indices.push_back(IRB.getInt(NumSkippedElements));
- return getNaturalGEPRecursively(IRB, TD, Ptr, ElementTy, Offset, TargetTy,
- Indices, Prefix);
+ return true;
}
- StructType *STy = dyn_cast<StructType>(Ty);
- if (!STy)
- return 0;
-
- const StructLayout *SL = TD.getStructLayout(STy);
- uint64_t StructOffset = Offset.getZExtValue();
- if (StructOffset >= SL->getSizeInBytes())
- return 0;
- unsigned Index = SL->getElementContainingOffset(StructOffset);
- Offset -= APInt(Offset.getBitWidth(), SL->getElementOffset(Index));
- Type *ElementTy = STy->getElementType(Index);
- if (Offset.uge(TD.getTypeAllocSize(ElementTy)))
- return 0; // The offset points into alignment padding.
-
- Indices.push_back(IRB.getInt32(Index));
- return getNaturalGEPRecursively(IRB, TD, Ptr, ElementTy, Offset, TargetTy,
- Indices, Prefix);
-}
+ void visitPHINode(PHINode &PN) {
+ DEBUG(dbgs() << " original: " << PN << "\n");
-/// \brief Get a natural GEP from a base pointer to a particular offset and
-/// resulting in a particular type.
-///
-/// The goal is to produce a "natural" looking GEP that works with the existing
-/// composite types to arrive at the appropriate offset and element type for
-/// a pointer. TargetTy is the element type the returned GEP should point-to if
-/// possible. We recurse by decreasing Offset, adding the appropriate index to
-/// Indices, and setting Ty to the result subtype.
-///
-/// If no natural GEP can be constructed, this function returns null.
-static Value *getNaturalGEPWithOffset(IRBuilder<> &IRB, const TargetData &TD,
- Value *Ptr, APInt Offset, Type *TargetTy,
- SmallVectorImpl<Value *> &Indices,
- const Twine &Prefix) {
- PointerType *Ty = cast<PointerType>(Ptr->getType());
+ SmallVector<LoadInst *, 4> Loads;
+ if (!isSafePHIToSpeculate(PN, Loads))
+ return;
- // Don't consider any GEPs through an i8* as natural unless the TargetTy is
- // an i8.
- if (Ty == IRB.getInt8PtrTy() && TargetTy->isIntegerTy(8))
- return 0;
+ assert(!Loads.empty());
- Type *ElementTy = Ty->getElementType();
- if (!ElementTy->isSized())
- return 0; // We can't GEP through an unsized element.
- APInt ElementSize(Offset.getBitWidth(), TD.getTypeAllocSize(ElementTy));
- if (ElementSize == 0)
- return 0; // Zero-length arrays can't help us build a natural GEP.
- APInt NumSkippedElements = Offset.udiv(ElementSize);
+ Type *LoadTy = cast<PointerType>(PN.getType())->getElementType();
+ IRBuilder<> PHIBuilder(&PN);
+ PHINode *NewPN = PHIBuilder.CreatePHI(LoadTy, PN.getNumIncomingValues(),
+ PN.getName() + ".sroa.speculated");
- Offset -= NumSkippedElements * ElementSize;
- Indices.push_back(IRB.getInt(NumSkippedElements));
- return getNaturalGEPRecursively(IRB, TD, Ptr, ElementTy, Offset, TargetTy,
- Indices, Prefix);
-}
+ // Get the TBAA tag and alignment to use from one of the loads. It doesn't
+ // matter which one we get and if any differ, it doesn't matter.
+ LoadInst *SomeLoad = cast<LoadInst>(Loads.back());
+ MDNode *TBAATag = SomeLoad->getMetadata(LLVMContext::MD_tbaa);
+ unsigned Align = SomeLoad->getAlignment();
-/// \brief Compute an adjusted pointer from Ptr by Offset bytes where the
-/// resulting pointer has PointerTy.
-///
-/// This tries very hard to compute a "natural" GEP which arrives at the offset
-/// and produces the pointer type desired. Where it cannot, it will try to use
-/// the natural GEP to arrive at the offset and bitcast to the type. Where that
-/// fails, it will try to use an existing i8* and GEP to the byte offset and
-/// bitcast to the type.
-///
-/// The strategy for finding the more natural GEPs is to peel off layers of the
-/// pointer, walking back through bit casts and GEPs, searching for a base
-/// pointer from which we can compute a natural GEP with the desired
-/// properities. The algorithm tries to fold as many constant indices into
-/// a single GEP as possible, thus making each GEP more independent of the
-/// surrounding code.
-static Value *getAdjustedPtr(IRBuilder<> &IRB, const TargetData &TD,
- Value *Ptr, APInt Offset, Type *PointerTy,
- const Twine &Prefix) {
- // Even though we don't look through PHI nodes, we could be called on an
- // instruction in an unreachable block, which may be on a cycle.
- SmallPtrSet<Value *, 4> Visited;
- Visited.insert(Ptr);
- SmallVector<Value *, 4> Indices;
+ // Rewrite all loads of the PN to use the new PHI.
+ do {
+ LoadInst *LI = Loads.pop_back_val();
+ LI->replaceAllUsesWith(NewPN);
+ Pass.DeadInsts.push_back(LI);
+ } while (!Loads.empty());
- // We may end up computing an offset pointer that has the wrong type. If we
- // never are able to compute one directly that has the correct type, we'll
- // fall back to it, so keep it around here.
- Value *OffsetPtr = 0;
+ // Inject loads into all of the pred blocks.
+ for (unsigned Idx = 0, Num = PN.getNumIncomingValues(); Idx != Num; ++Idx) {
+ BasicBlock *Pred = PN.getIncomingBlock(Idx);
+ TerminatorInst *TI = Pred->getTerminator();
+ Use *InUse = &PN.getOperandUse(PN.getOperandNumForIncomingValue(Idx));
+ Value *InVal = PN.getIncomingValue(Idx);
+ IRBuilder<> PredBuilder(TI);
- // Remember any i8 pointer we come across to re-use if we need to do a raw
- // byte offset.
- Value *Int8Ptr = 0;
- APInt Int8PtrOffset(Offset.getBitWidth(), 0);
+ LoadInst *Load
+ = PredBuilder.CreateLoad(InVal, (PN.getName() + ".sroa.speculate.load." +
+ Pred->getName()));
+ ++NumLoadsSpeculated;
+ Load->setAlignment(Align);
+ if (TBAATag)
+ Load->setMetadata(LLVMContext::MD_tbaa, TBAATag);
+ NewPN->addIncoming(Load, Pred);
- Type *TargetTy = PointerTy->getPointerElementType();
+ Instruction *Ptr = dyn_cast<Instruction>(InVal);
+ if (!Ptr)
+ // No uses to rewrite.
+ continue;
- do {
- // First fold any existing GEPs into the offset.
- while (GEPOperator *GEP = dyn_cast<GEPOperator>(Ptr)) {
- APInt GEPOffset(Offset.getBitWidth(), 0);
- if (!accumulateGEPOffsets(TD, *GEP, GEPOffset))
- break;
- Offset += GEPOffset;
- Ptr = GEP->getPointerOperand();
- if (!Visited.insert(Ptr))
- break;
- }
+ // Try to lookup and rewrite any partition uses corresponding to this phi
+ // input.
+ AllocaPartitioning::iterator PI
+ = P.findPartitionForPHIOrSelectOperand(InUse);
+ if (PI == P.end())
+ continue;
- // See if we can perform a natural GEP here.
- Indices.clear();
- if (Value *P = getNaturalGEPWithOffset(IRB, TD, Ptr, Offset, TargetTy,
- Indices, Prefix)) {
- if (P->getType() == PointerTy) {
- // Zap any offset pointer that we ended up computing in previous rounds.
- if (OffsetPtr && OffsetPtr->use_empty())
- if (Instruction *I = dyn_cast<Instruction>(OffsetPtr))
- I->eraseFromParent();
- return P;
- }
- if (!OffsetPtr) {
- OffsetPtr = P;
- }
+ // Replace the Use in the PartitionUse for this operand with the Use
+ // inside the load.
+ AllocaPartitioning::use_iterator UI
+ = P.findPartitionUseForPHIOrSelectOperand(InUse);
+ assert(isa<PHINode>(*UI->U->getUser()));
+ UI->U = &Load->getOperandUse(Load->getPointerOperandIndex());
}
+ DEBUG(dbgs() << " speculated to: " << *NewPN << "\n");
+ }
- // Stash this pointer if we've found an i8*.
- if (Ptr->getType()->isIntegerTy(8)) {
- Int8Ptr = Ptr;
- Int8PtrOffset = Offset;
- }
+ /// Select instructions that use an alloca and are subsequently loaded can be
+ /// rewritten to load both input pointers and then select between the result,
+ /// allowing the load of the alloca to be promoted.
+ /// From this:
+ /// %P2 = select i1 %cond, i32* %Alloca, i32* %Other
+ /// %V = load i32* %P2
+ /// to:
+ /// %V1 = load i32* %Alloca -> will be mem2reg'd
+ /// %V2 = load i32* %Other
+ /// %V = select i1 %cond, i32 %V1, i32 %V2
+ ///
+ /// We can do this to a select if its only uses are loads and if the operand
+ /// to the select can be loaded unconditionally.
+ bool isSafeSelectToSpeculate(SelectInst &SI,
+ SmallVectorImpl<LoadInst *> &Loads) {
+ Value *TValue = SI.getTrueValue();
+ Value *FValue = SI.getFalseValue();
+ bool TDerefable = TValue->isDereferenceablePointer();
+ bool FDerefable = FValue->isDereferenceablePointer();
- // Peel off a layer of the pointer and update the offset appropriately.
- if (Operator::getOpcode(Ptr) == Instruction::BitCast) {
- Ptr = cast<Operator>(Ptr)->getOperand(0);
- } else if (GlobalAlias *GA = dyn_cast<GlobalAlias>(Ptr)) {
- if (GA->mayBeOverridden())
- break;
- Ptr = GA->getAliasee();
- } else {
- break;
- }
- assert(Ptr->getType()->isPointerTy() && "Unexpected operand type!");
- } while (Visited.insert(Ptr));
+ for (Value::use_iterator UI = SI.use_begin(), UE = SI.use_end();
+ UI != UE; ++UI) {
+ LoadInst *LI = dyn_cast<LoadInst>(*UI);
+ if (LI == 0 || !LI->isSimple()) return false;
- if (!OffsetPtr) {
- if (!Int8Ptr) {
- Int8Ptr = IRB.CreateBitCast(Ptr, IRB.getInt8PtrTy(),
- Prefix + ".raw_cast");
- Int8PtrOffset = Offset;
+ // Both operands to the select need to be dereferencable, either
+ // absolutely (e.g. allocas) or at this point because we can see other
+ // accesses to it.
+ if (!TDerefable && !isSafeToLoadUnconditionally(TValue, LI,
+ LI->getAlignment(), &TD))
+ return false;
+ if (!FDerefable && !isSafeToLoadUnconditionally(FValue, LI,
+ LI->getAlignment(), &TD))
+ return false;
+ Loads.push_back(LI);
}
- OffsetPtr = Int8PtrOffset == 0 ? Int8Ptr :
- IRB.CreateInBoundsGEP(Int8Ptr, IRB.getInt(Int8PtrOffset),
- Prefix + ".raw_idx");
+ return true;
}
- Ptr = OffsetPtr;
- // On the off chance we were targeting i8*, guard the bitcast here.
- if (Ptr->getType() != PointerTy)
- Ptr = IRB.CreateBitCast(Ptr, PointerTy, Prefix + ".cast");
+ void visitSelectInst(SelectInst &SI) {
+ DEBUG(dbgs() << " original: " << SI << "\n");
+ IRBuilder<> IRB(&SI);
- return Ptr;
-}
+ // If the select isn't safe to speculate, just use simple logic to emit it.
+ SmallVector<LoadInst *, 4> Loads;
+ if (!isSafeSelectToSpeculate(SI, Loads))
+ return;
-/// \brief Test whether the given alloca partition can be promoted to a vector.
-///
-/// This is a quick test to check whether we can rewrite a particular alloca
-/// partition (and its newly formed alloca) into a vector alloca with only
-/// whole-vector loads and stores such that it could be promoted to a vector
-/// SSA value. We only can ensure this for a limited set of operations, and we
-/// don't want to do the rewrites unless we are confident that the result will
-/// be promotable, so we have an early test here.
-static bool isVectorPromotionViable(const TargetData &TD,
- Type *AllocaTy,
- AllocaPartitioning &P,
- uint64_t PartitionBeginOffset,
- uint64_t PartitionEndOffset,
- AllocaPartitioning::const_use_iterator I,
- AllocaPartitioning::const_use_iterator E) {
- VectorType *Ty = dyn_cast<VectorType>(AllocaTy);
- if (!Ty)
- return false;
+ Use *Ops[2] = { &SI.getOperandUse(1), &SI.getOperandUse(2) };
+ AllocaPartitioning::iterator PIs[2];
+ AllocaPartitioning::PartitionUse PUs[2];
+ for (unsigned i = 0, e = 2; i != e; ++i) {
+ PIs[i] = P.findPartitionForPHIOrSelectOperand(Ops[i]);
+ if (PIs[i] != P.end()) {
+ // If the pointer is within the partitioning, remove the select from
+ // its uses. We'll add in the new loads below.
+ AllocaPartitioning::use_iterator UI
+ = P.findPartitionUseForPHIOrSelectOperand(Ops[i]);
+ PUs[i] = *UI;
+ // Clear out the use here so that the offsets into the use list remain
+ // stable but this use is ignored when rewriting.
+ UI->U = 0;
+ }
+ }
- uint64_t VecSize = TD.getTypeSizeInBits(Ty);
- uint64_t ElementSize = Ty->getScalarSizeInBits();
+ Value *TV = SI.getTrueValue();
+ Value *FV = SI.getFalseValue();
+ // Replace the loads of the select with a select of two loads.
+ while (!Loads.empty()) {
+ LoadInst *LI = Loads.pop_back_val();
- // While the definition of LLVM vectors is bitpacked, we don't support sizes
- // that aren't byte sized.
- if (ElementSize % 8)
- return false;
- assert((VecSize % 8) == 0 && "vector size not a multiple of element size?");
- VecSize /= 8;
- ElementSize /= 8;
+ IRB.SetInsertPoint(LI);
+ LoadInst *TL =
+ IRB.CreateLoad(TV, LI->getName() + ".sroa.speculate.load.true");
+ LoadInst *FL =
+ IRB.CreateLoad(FV, LI->getName() + ".sroa.speculate.load.false");
+ NumLoadsSpeculated += 2;
- for (; I != E; ++I) {
- uint64_t BeginOffset = I->BeginOffset - PartitionBeginOffset;
- uint64_t BeginIndex = BeginOffset / ElementSize;
- if (BeginIndex * ElementSize != BeginOffset ||
- BeginIndex >= Ty->getNumElements())
- return false;
- uint64_t EndOffset = I->EndOffset - PartitionBeginOffset;
- uint64_t EndIndex = EndOffset / ElementSize;
- if (EndIndex * ElementSize != EndOffset ||
- EndIndex > Ty->getNumElements())
- return false;
+ // Transfer alignment and TBAA info if present.
+ TL->setAlignment(LI->getAlignment());
+ FL->setAlignment(LI->getAlignment());
+ if (MDNode *Tag = LI->getMetadata(LLVMContext::MD_tbaa)) {
+ TL->setMetadata(LLVMContext::MD_tbaa, Tag);
+ FL->setMetadata(LLVMContext::MD_tbaa, Tag);
+ }
- // FIXME: We should build shuffle vector instructions to handle
- // non-element-sized accesses.
- if ((EndOffset - BeginOffset) != ElementSize &&
- (EndOffset - BeginOffset) != VecSize)
- return false;
+ Value *V = IRB.CreateSelect(SI.getCondition(), TL, FL,
+ LI->getName() + ".sroa.speculated");
- if (MemIntrinsic *MI = dyn_cast<MemIntrinsic>(I->U->getUser())) {
- if (MI->isVolatile())
- return false;
- if (MemTransferInst *MTI = dyn_cast<MemTransferInst>(I->U->getUser())) {
- const AllocaPartitioning::MemTransferOffsets &MTO
- = P.getMemTransferOffsets(*MTI);
- if (!MTO.IsSplittable)
- return false;
+ LoadInst *Loads[2] = { TL, FL };
+ for (unsigned i = 0, e = 2; i != e; ++i) {
+ if (PIs[i] != P.end()) {
+ Use *LoadUse = &Loads[i]->getOperandUse(0);
+ assert(PUs[i].U->get() == LoadUse->get());
+ PUs[i].U = LoadUse;
+ P.use_push_back(PIs[i], PUs[i]);
+ }
}
- } else if (I->U->get()->getType()->getPointerElementType()->isStructTy()) {
- // Disable vector promotion when there are loads or stores of an FCA.
- return false;
- } else if (!isa<LoadInst>(I->U->getUser()) &&
- !isa<StoreInst>(I->U->getUser())) {
- return false;
+
+ DEBUG(dbgs() << " speculated to: " << *V << "\n");
+ LI->replaceAllUsesWith(V);
+ Pass.DeadInsts.push_back(LI);
}
}
- return true;
+};
}
-/// \brief Test whether the given alloca partition can be promoted to an int.
+/// \brief Accumulate the constant offsets in a GEP into a single APInt offset.
///
-/// This is a quick test to check whether we can rewrite a particular alloca
-/// partition (and its newly formed alloca) into an integer alloca suitable for
-/// promotion to an SSA value. We only can ensure this for a limited set of
-/// operations, and we don't want to do the rewrites unless we are confident
-/// that the result will be promotable, so we have an early test here.
-static bool isIntegerPromotionViable(const TargetData &TD,
- Type *AllocaTy,
- AllocaPartitioning &P,
- AllocaPartitioning::const_use_iterator I,
- AllocaPartitioning::const_use_iterator E) {
- IntegerType *Ty = dyn_cast<IntegerType>(AllocaTy);
- if (!Ty)
- return false;
-
- // Check the uses to ensure the uses are (likely) promoteable integer uses.
- // Also ensure that the alloca has a covering load or store. We don't want
- // promote because of some other unsplittable entry (which we may make
- // splittable later) and lose the ability to promote each element access.
- bool WholeAllocaOp = false;
- for (; I != E; ++I) {
- if (LoadInst *LI = dyn_cast<LoadInst>(I->U->getUser())) {
- if (LI->isVolatile() || !LI->getType()->isIntegerTy())
- return false;
- if (LI->getType() == Ty)
- WholeAllocaOp = true;
- } else if (StoreInst *SI = dyn_cast<StoreInst>(I->U->getUser())) {
- if (SI->isVolatile() || !SI->getValueOperand()->getType()->isIntegerTy())
- return false;
- if (SI->getValueOperand()->getType() == Ty)
- WholeAllocaOp = true;
- } else if (MemIntrinsic *MI = dyn_cast<MemIntrinsic>(I->U->getUser())) {
- if (MI->isVolatile())
- return false;
- if (MemTransferInst *MTI = dyn_cast<MemTransferInst>(I->U->getUser())) {
- const AllocaPartitioning::MemTransferOffsets &MTO
- = P.getMemTransferOffsets(*MTI);
- if (!MTO.IsSplittable)
- return false;
- }
- } else {
+/// If the provided GEP is all-constant, the total byte offset formed by the
+/// GEP is computed and Offset is set to it. If the GEP has any non-constant
+/// operands, the function returns false and the value of Offset is unmodified.
+static bool accumulateGEPOffsets(const DataLayout &TD, GEPOperator &GEP,
+ APInt &Offset) {
+ APInt GEPOffset(Offset.getBitWidth(), 0);
+ for (gep_type_iterator GTI = gep_type_begin(GEP), GTE = gep_type_end(GEP);
+ GTI != GTE; ++GTI) {
+ ConstantInt *OpC = dyn_cast<ConstantInt>(GTI.getOperand());
+ if (!OpC)
return false;
- }
- }
- return WholeAllocaOp;
-}
-
-namespace {
-/// \brief Visitor to speculate PHIs and Selects where possible.
-class PHIOrSelectSpeculator : public InstVisitor<PHIOrSelectSpeculator> {
- // Befriend the base class so it can delegate to private visit methods.
- friend class llvm::InstVisitor<PHIOrSelectSpeculator>;
+ if (OpC->isZero()) continue;
- const TargetData &TD;
- AllocaPartitioning &P;
- SROA &Pass;
+ // Handle a struct index, which adds its field offset to the pointer.
+ if (StructType *STy = dyn_cast<StructType>(*GTI)) {
+ unsigned ElementIdx = OpC->getZExtValue();
+ const StructLayout *SL = TD.getStructLayout(STy);
+ GEPOffset += APInt(Offset.getBitWidth(),
+ SL->getElementOffset(ElementIdx));
+ continue;
+ }
-public:
- PHIOrSelectSpeculator(const TargetData &TD, AllocaPartitioning &P, SROA &Pass)
- : TD(TD), P(P), Pass(Pass) {}
+ APInt TypeSize(Offset.getBitWidth(),
+ TD.getTypeAllocSize(GTI.getIndexedType()));
+ if (VectorType *VTy = dyn_cast<VectorType>(*GTI)) {
+ assert((VTy->getScalarSizeInBits() % 8) == 0 &&
+ "vector element size is not a multiple of 8, cannot GEP over it");
+ TypeSize = VTy->getScalarSizeInBits() / 8;
+ }
- /// \brief Visit the users of the alloca partition and rewrite them.
- void visitUsers(AllocaPartitioning::const_use_iterator I,
- AllocaPartitioning::const_use_iterator E) {
- for (; I != E; ++I)
- visit(cast<Instruction>(I->U->getUser()));
+ GEPOffset += OpC->getValue().sextOrTrunc(Offset.getBitWidth()) * TypeSize;
}
+ Offset = GEPOffset;
+ return true;
+}
-private:
- // By default, skip this instruction.
- void visitInstruction(Instruction &I) {}
+/// \brief Build a GEP out of a base pointer and indices.
+///
+/// This will return the BasePtr if that is valid, or build a new GEP
+/// instruction using the IRBuilder if GEP-ing is needed.
+static Value *buildGEP(IRBuilder<> &IRB, Value *BasePtr,
+ SmallVectorImpl<Value *> &Indices,
+ const Twine &Prefix) {
+ if (Indices.empty())
+ return BasePtr;
- /// PHI instructions that use an alloca and are subsequently loaded can be
- /// rewritten to load both input pointers in the pred blocks and then PHI the
- /// results, allowing the load of the alloca to be promoted.
- /// From this:
- /// %P2 = phi [i32* %Alloca, i32* %Other]
- /// %V = load i32* %P2
- /// to:
- /// %V1 = load i32* %Alloca -> will be mem2reg'd
- /// ...
- /// %V2 = load i32* %Other
- /// ...
- /// %V = phi [i32 %V1, i32 %V2]
- ///
- /// We can do this to a select if its only uses are loads and if the operands
- /// to the select can be loaded unconditionally.
- ///
- /// FIXME: This should be hoisted into a generic utility, likely in
- /// Transforms/Util/Local.h
- bool isSafePHIToSpeculate(PHINode &PN, SmallVectorImpl<LoadInst *> &Loads) {
- // For now, we can only do this promotion if the load is in the same block
- // as the PHI, and if there are no stores between the phi and load.
- // TODO: Allow recursive phi users.
- // TODO: Allow stores.
- BasicBlock *BB = PN.getParent();
- unsigned MaxAlign = 0;
- for (Value::use_iterator UI = PN.use_begin(), UE = PN.use_end();
- UI != UE; ++UI) {
- LoadInst *LI = dyn_cast<LoadInst>(*UI);
- if (LI == 0 || !LI->isSimple()) return false;
+ // A single zero index is a no-op, so check for this and avoid building a GEP
+ // in that case.
+ if (Indices.size() == 1 && cast<ConstantInt>(Indices.back())->isZero())
+ return BasePtr;
- // For now we only allow loads in the same block as the PHI. This is
- // a common case that happens when instcombine merges two loads through
- // a PHI.
- if (LI->getParent() != BB) return false;
+ return IRB.CreateInBoundsGEP(BasePtr, Indices, Prefix + ".idx");
+}
- // Ensure that there are no instructions between the PHI and the load that
- // could store.
- for (BasicBlock::iterator BBI = &PN; &*BBI != LI; ++BBI)
- if (BBI->mayWriteToMemory())
- return false;
+/// \brief Get a natural GEP off of the BasePtr walking through Ty toward
+/// TargetTy without changing the offset of the pointer.
+///
+/// This routine assumes we've already established a properly offset GEP with
+/// Indices, and arrived at the Ty type. The goal is to continue to GEP with
+/// zero-indices down through type layers until we find one the same as
+/// TargetTy. If we can't find one with the same type, we at least try to use
+/// one with the same size. If none of that works, we just produce the GEP as
+/// indicated by Indices to have the correct offset.
+static Value *getNaturalGEPWithType(IRBuilder<> &IRB, const DataLayout &TD,
+ Value *BasePtr, Type *Ty, Type *TargetTy,
+ SmallVectorImpl<Value *> &Indices,
+ const Twine &Prefix) {
+ if (Ty == TargetTy)
+ return buildGEP(IRB, BasePtr, Indices, Prefix);
- MaxAlign = std::max(MaxAlign, LI->getAlignment());
- Loads.push_back(LI);
+ // See if we can descend into a struct and locate a field with the correct
+ // type.
+ unsigned NumLayers = 0;
+ Type *ElementTy = Ty;
+ do {
+ if (ElementTy->isPointerTy())
+ break;
+ if (SequentialType *SeqTy = dyn_cast<SequentialType>(ElementTy)) {
+ ElementTy = SeqTy->getElementType();
+ Indices.push_back(IRB.getInt(APInt(TD.getPointerSizeInBits(), 0)));
+ } else if (StructType *STy = dyn_cast<StructType>(ElementTy)) {
+ if (STy->element_begin() == STy->element_end())
+ break; // Nothing left to descend into.
+ ElementTy = *STy->element_begin();
+ Indices.push_back(IRB.getInt32(0));
+ } else {
+ break;
}
+ ++NumLayers;
+ } while (ElementTy != TargetTy);
+ if (ElementTy != TargetTy)
+ Indices.erase(Indices.end() - NumLayers, Indices.end());
- // We can only transform this if it is safe to push the loads into the
- // predecessor blocks. The only thing to watch out for is that we can't put
- // a possibly trapping load in the predecessor if it is a critical edge.
- for (unsigned Idx = 0, Num = PN.getNumIncomingValues(); Idx != Num;
- ++Idx) {
- TerminatorInst *TI = PN.getIncomingBlock(Idx)->getTerminator();
- Value *InVal = PN.getIncomingValue(Idx);
+ return buildGEP(IRB, BasePtr, Indices, Prefix);
+}
- // If the value is produced by the terminator of the predecessor (an
- // invoke) or it has side-effects, there is no valid place to put a load
- // in the predecessor.
- if (TI == InVal || TI->mayHaveSideEffects())
- return false;
+/// \brief Recursively compute indices for a natural GEP.
+///
+/// This is the recursive step for getNaturalGEPWithOffset that walks down the
+/// element types adding appropriate indices for the GEP.
+static Value *getNaturalGEPRecursively(IRBuilder<> &IRB, const DataLayout &TD,
+ Value *Ptr, Type *Ty, APInt &Offset,
+ Type *TargetTy,
+ SmallVectorImpl<Value *> &Indices,
+ const Twine &Prefix) {
+ if (Offset == 0)
+ return getNaturalGEPWithType(IRB, TD, Ptr, Ty, TargetTy, Indices, Prefix);
- // If the predecessor has a single successor, then the edge isn't
- // critical.
- if (TI->getNumSuccessors() == 1)
- continue;
+ // We can't recurse through pointer types.
+ if (Ty->isPointerTy())
+ return 0;
- // If this pointer is always safe to load, or if we can prove that there
- // is already a load in the block, then we can move the load to the pred
- // block.
- if (InVal->isDereferenceablePointer() ||
- isSafeToLoadUnconditionally(InVal, TI, MaxAlign, &TD))
- continue;
+ // We try to analyze GEPs over vectors here, but note that these GEPs are
+ // extremely poorly defined currently. The long-term goal is to remove GEPing
+ // over a vector from the IR completely.
+ if (VectorType *VecTy = dyn_cast<VectorType>(Ty)) {
+ unsigned ElementSizeInBits = VecTy->getScalarSizeInBits();
+ if (ElementSizeInBits % 8)
+ return 0; // GEPs over non-multiple of 8 size vector elements are invalid.
+ APInt ElementSize(Offset.getBitWidth(), ElementSizeInBits / 8);
+ APInt NumSkippedElements = Offset.udiv(ElementSize);
+ if (NumSkippedElements.ugt(VecTy->getNumElements()))
+ return 0;
+ Offset -= NumSkippedElements * ElementSize;
+ Indices.push_back(IRB.getInt(NumSkippedElements));
+ return getNaturalGEPRecursively(IRB, TD, Ptr, VecTy->getElementType(),
+ Offset, TargetTy, Indices, Prefix);
+ }
- return false;
- }
+ if (ArrayType *ArrTy = dyn_cast<ArrayType>(Ty)) {
+ Type *ElementTy = ArrTy->getElementType();
+ APInt ElementSize(Offset.getBitWidth(), TD.getTypeAllocSize(ElementTy));
+ APInt NumSkippedElements = Offset.udiv(ElementSize);
+ if (NumSkippedElements.ugt(ArrTy->getNumElements()))
+ return 0;
- return true;
+ Offset -= NumSkippedElements * ElementSize;
+ Indices.push_back(IRB.getInt(NumSkippedElements));
+ return getNaturalGEPRecursively(IRB, TD, Ptr, ElementTy, Offset, TargetTy,
+ Indices, Prefix);
}
- void visitPHINode(PHINode &PN) {
- DEBUG(dbgs() << " original: " << PN << "\n");
+ StructType *STy = dyn_cast<StructType>(Ty);
+ if (!STy)
+ return 0;
- SmallVector<LoadInst *, 4> Loads;
- if (!isSafePHIToSpeculate(PN, Loads))
- return;
+ const StructLayout *SL = TD.getStructLayout(STy);
+ uint64_t StructOffset = Offset.getZExtValue();
+ if (StructOffset >= SL->getSizeInBytes())
+ return 0;
+ unsigned Index = SL->getElementContainingOffset(StructOffset);
+ Offset -= APInt(Offset.getBitWidth(), SL->getElementOffset(Index));
+ Type *ElementTy = STy->getElementType(Index);
+ if (Offset.uge(TD.getTypeAllocSize(ElementTy)))
+ return 0; // The offset points into alignment padding.
- assert(!Loads.empty());
+ Indices.push_back(IRB.getInt32(Index));
+ return getNaturalGEPRecursively(IRB, TD, Ptr, ElementTy, Offset, TargetTy,
+ Indices, Prefix);
+}
- Type *LoadTy = cast<PointerType>(PN.getType())->getElementType();
- IRBuilder<> PHIBuilder(&PN);
- PHINode *NewPN = PHIBuilder.CreatePHI(LoadTy, PN.getNumIncomingValues(),
- PN.getName() + ".sroa.speculated");
+/// \brief Get a natural GEP from a base pointer to a particular offset and
+/// resulting in a particular type.
+///
+/// The goal is to produce a "natural" looking GEP that works with the existing
+/// composite types to arrive at the appropriate offset and element type for
+/// a pointer. TargetTy is the element type the returned GEP should point-to if
+/// possible. We recurse by decreasing Offset, adding the appropriate index to
+/// Indices, and setting Ty to the result subtype.
+///
+/// If no natural GEP can be constructed, this function returns null.
+static Value *getNaturalGEPWithOffset(IRBuilder<> &IRB, const DataLayout &TD,
+ Value *Ptr, APInt Offset, Type *TargetTy,
+ SmallVectorImpl<Value *> &Indices,
+ const Twine &Prefix) {
+ PointerType *Ty = cast<PointerType>(Ptr->getType());
- // Get the TBAA tag and alignment to use from one of the loads. It doesn't
- // matter which one we get and if any differ, it doesn't matter.
- LoadInst *SomeLoad = cast<LoadInst>(Loads.back());
- MDNode *TBAATag = SomeLoad->getMetadata(LLVMContext::MD_tbaa);
- unsigned Align = SomeLoad->getAlignment();
+ // Don't consider any GEPs through an i8* as natural unless the TargetTy is
+ // an i8.
+ if (Ty == IRB.getInt8PtrTy() && TargetTy->isIntegerTy(8))
+ return 0;
- // Rewrite all loads of the PN to use the new PHI.
- do {
- LoadInst *LI = Loads.pop_back_val();
- LI->replaceAllUsesWith(NewPN);
- Pass.DeadInsts.push_back(LI);
- } while (!Loads.empty());
+ Type *ElementTy = Ty->getElementType();
+ if (!ElementTy->isSized())
+ return 0; // We can't GEP through an unsized element.
+ APInt ElementSize(Offset.getBitWidth(), TD.getTypeAllocSize(ElementTy));
+ if (ElementSize == 0)
+ return 0; // Zero-length arrays can't help us build a natural GEP.
+ APInt NumSkippedElements = Offset.udiv(ElementSize);
- // Inject loads into all of the pred blocks.
- for (unsigned Idx = 0, Num = PN.getNumIncomingValues(); Idx != Num; ++Idx) {
- BasicBlock *Pred = PN.getIncomingBlock(Idx);
- TerminatorInst *TI = Pred->getTerminator();
- Use *InUse = &PN.getOperandUse(PN.getOperandNumForIncomingValue(Idx));
- Value *InVal = PN.getIncomingValue(Idx);
- IRBuilder<> PredBuilder(TI);
+ Offset -= NumSkippedElements * ElementSize;
+ Indices.push_back(IRB.getInt(NumSkippedElements));
+ return getNaturalGEPRecursively(IRB, TD, Ptr, ElementTy, Offset, TargetTy,
+ Indices, Prefix);
+}
- LoadInst *Load
- = PredBuilder.CreateLoad(InVal, (PN.getName() + ".sroa.speculate.load." +
- Pred->getName()));
- ++NumLoadsSpeculated;
- Load->setAlignment(Align);
- if (TBAATag)
- Load->setMetadata(LLVMContext::MD_tbaa, TBAATag);
- NewPN->addIncoming(Load, Pred);
+/// \brief Compute an adjusted pointer from Ptr by Offset bytes where the
+/// resulting pointer has PointerTy.
+///
+/// This tries very hard to compute a "natural" GEP which arrives at the offset
+/// and produces the pointer type desired. Where it cannot, it will try to use
+/// the natural GEP to arrive at the offset and bitcast to the type. Where that
+/// fails, it will try to use an existing i8* and GEP to the byte offset and
+/// bitcast to the type.
+///
+/// The strategy for finding the more natural GEPs is to peel off layers of the
+/// pointer, walking back through bit casts and GEPs, searching for a base
+/// pointer from which we can compute a natural GEP with the desired
+/// properities. The algorithm tries to fold as many constant indices into
+/// a single GEP as possible, thus making each GEP more independent of the
+/// surrounding code.
+static Value *getAdjustedPtr(IRBuilder<> &IRB, const DataLayout &TD,
+ Value *Ptr, APInt Offset, Type *PointerTy,
+ const Twine &Prefix) {
+ // Even though we don't look through PHI nodes, we could be called on an
+ // instruction in an unreachable block, which may be on a cycle.
+ SmallPtrSet<Value *, 4> Visited;
+ Visited.insert(Ptr);
+ SmallVector<Value *, 4> Indices;
- Instruction *Ptr = dyn_cast<Instruction>(InVal);
- if (!Ptr)
- // No uses to rewrite.
- continue;
+ // We may end up computing an offset pointer that has the wrong type. If we
+ // never are able to compute one directly that has the correct type, we'll
+ // fall back to it, so keep it around here.
+ Value *OffsetPtr = 0;
- // Try to lookup and rewrite any partition uses corresponding to this phi
- // input.
- AllocaPartitioning::iterator PI
- = P.findPartitionForPHIOrSelectOperand(InUse);
- if (PI == P.end())
- continue;
+ // Remember any i8 pointer we come across to re-use if we need to do a raw
+ // byte offset.
+ Value *Int8Ptr = 0;
+ APInt Int8PtrOffset(Offset.getBitWidth(), 0);
- // Replace the Use in the PartitionUse for this operand with the Use
- // inside the load.
- AllocaPartitioning::use_iterator UI
- = P.findPartitionUseForPHIOrSelectOperand(InUse);
- assert(isa<PHINode>(*UI->U->getUser()));
- UI->U = &Load->getOperandUse(Load->getPointerOperandIndex());
+ Type *TargetTy = PointerTy->getPointerElementType();
+
+ do {
+ // First fold any existing GEPs into the offset.
+ while (GEPOperator *GEP = dyn_cast<GEPOperator>(Ptr)) {
+ APInt GEPOffset(Offset.getBitWidth(), 0);
+ if (!accumulateGEPOffsets(TD, *GEP, GEPOffset))
+ break;
+ Offset += GEPOffset;
+ Ptr = GEP->getPointerOperand();
+ if (!Visited.insert(Ptr))
+ break;
+ }
+
+ // See if we can perform a natural GEP here.
+ Indices.clear();
+ if (Value *P = getNaturalGEPWithOffset(IRB, TD, Ptr, Offset, TargetTy,
+ Indices, Prefix)) {
+ if (P->getType() == PointerTy) {
+ // Zap any offset pointer that we ended up computing in previous rounds.
+ if (OffsetPtr && OffsetPtr->use_empty())
+ if (Instruction *I = dyn_cast<Instruction>(OffsetPtr))
+ I->eraseFromParent();
+ return P;
+ }
+ if (!OffsetPtr) {
+ OffsetPtr = P;
+ }
}
- DEBUG(dbgs() << " speculated to: " << *NewPN << "\n");
- }
- /// Select instructions that use an alloca and are subsequently loaded can be
- /// rewritten to load both input pointers and then select between the result,
- /// allowing the load of the alloca to be promoted.
- /// From this:
- /// %P2 = select i1 %cond, i32* %Alloca, i32* %Other
- /// %V = load i32* %P2
- /// to:
- /// %V1 = load i32* %Alloca -> will be mem2reg'd
- /// %V2 = load i32* %Other
- /// %V = select i1 %cond, i32 %V1, i32 %V2
- ///
- /// We can do this to a select if its only uses are loads and if the operand
- /// to the select can be loaded unconditionally.
- bool isSafeSelectToSpeculate(SelectInst &SI,
- SmallVectorImpl<LoadInst *> &Loads) {
- Value *TValue = SI.getTrueValue();
- Value *FValue = SI.getFalseValue();
- bool TDerefable = TValue->isDereferenceablePointer();
- bool FDerefable = FValue->isDereferenceablePointer();
+ // Stash this pointer if we've found an i8*.
+ if (Ptr->getType()->isIntegerTy(8)) {
+ Int8Ptr = Ptr;
+ Int8PtrOffset = Offset;
+ }
- for (Value::use_iterator UI = SI.use_begin(), UE = SI.use_end();
- UI != UE; ++UI) {
- LoadInst *LI = dyn_cast<LoadInst>(*UI);
- if (LI == 0 || !LI->isSimple()) return false;
+ // Peel off a layer of the pointer and update the offset appropriately.
+ if (Operator::getOpcode(Ptr) == Instruction::BitCast) {
+ Ptr = cast<Operator>(Ptr)->getOperand(0);
+ } else if (GlobalAlias *GA = dyn_cast<GlobalAlias>(Ptr)) {
+ if (GA->mayBeOverridden())
+ break;
+ Ptr = GA->getAliasee();
+ } else {
+ break;
+ }
+ assert(Ptr->getType()->isPointerTy() && "Unexpected operand type!");
+ } while (Visited.insert(Ptr));
- // Both operands to the select need to be dereferencable, either
- // absolutely (e.g. allocas) or at this point because we can see other
- // accesses to it.
- if (!TDerefable && !isSafeToLoadUnconditionally(TValue, LI,
- LI->getAlignment(), &TD))
- return false;
- if (!FDerefable && !isSafeToLoadUnconditionally(FValue, LI,
- LI->getAlignment(), &TD))
- return false;
- Loads.push_back(LI);
+ if (!OffsetPtr) {
+ if (!Int8Ptr) {
+ Int8Ptr = IRB.CreateBitCast(Ptr, IRB.getInt8PtrTy(),
+ Prefix + ".raw_cast");
+ Int8PtrOffset = Offset;
}
- return true;
+ OffsetPtr = Int8PtrOffset == 0 ? Int8Ptr :
+ IRB.CreateInBoundsGEP(Int8Ptr, IRB.getInt(Int8PtrOffset),
+ Prefix + ".raw_idx");
}
+ Ptr = OffsetPtr;
- void visitSelectInst(SelectInst &SI) {
- DEBUG(dbgs() << " original: " << SI << "\n");
- IRBuilder<> IRB(&SI);
+ // On the off chance we were targeting i8*, guard the bitcast here.
+ if (Ptr->getType() != PointerTy)
+ Ptr = IRB.CreateBitCast(Ptr, PointerTy, Prefix + ".cast");
- // If the select isn't safe to speculate, just use simple logic to emit it.
- SmallVector<LoadInst *, 4> Loads;
- if (!isSafeSelectToSpeculate(SI, Loads))
- return;
+ return Ptr;
+}
- Use *Ops[2] = { &SI.getOperandUse(1), &SI.getOperandUse(2) };
- AllocaPartitioning::iterator PIs[2];
- AllocaPartitioning::PartitionUse PUs[2];
- for (unsigned i = 0, e = 2; i != e; ++i) {
- PIs[i] = P.findPartitionForPHIOrSelectOperand(Ops[i]);
- if (PIs[i] != P.end()) {
- // If the pointer is within the partitioning, remove the select from
- // its uses. We'll add in the new loads below.
- AllocaPartitioning::use_iterator UI
- = P.findPartitionUseForPHIOrSelectOperand(Ops[i]);
- PUs[i] = *UI;
- P.use_erase(PIs[i], UI);
- }
- }
+/// \brief Test whether the given alloca partition can be promoted to a vector.
+///
+/// This is a quick test to check whether we can rewrite a particular alloca
+/// partition (and its newly formed alloca) into a vector alloca with only
+/// whole-vector loads and stores such that it could be promoted to a vector
+/// SSA value. We only can ensure this for a limited set of operations, and we
+/// don't want to do the rewrites unless we are confident that the result will
+/// be promotable, so we have an early test here.
+static bool isVectorPromotionViable(const DataLayout &TD,
+ Type *AllocaTy,
+ AllocaPartitioning &P,
+ uint64_t PartitionBeginOffset,
+ uint64_t PartitionEndOffset,
+ AllocaPartitioning::const_use_iterator I,
+ AllocaPartitioning::const_use_iterator E) {
+ VectorType *Ty = dyn_cast<VectorType>(AllocaTy);
+ if (!Ty)
+ return false;
- Value *TV = SI.getTrueValue();
- Value *FV = SI.getFalseValue();
- // Replace the loads of the select with a select of two loads.
- while (!Loads.empty()) {
- LoadInst *LI = Loads.pop_back_val();
+ uint64_t VecSize = TD.getTypeSizeInBits(Ty);
+ uint64_t ElementSize = Ty->getScalarSizeInBits();
- IRB.SetInsertPoint(LI);
- LoadInst *TL =
- IRB.CreateLoad(TV, LI->getName() + ".sroa.speculate.load.true");
- LoadInst *FL =
- IRB.CreateLoad(FV, LI->getName() + ".sroa.speculate.load.false");
- NumLoadsSpeculated += 2;
+ // While the definition of LLVM vectors is bitpacked, we don't support sizes
+ // that aren't byte sized.
+ if (ElementSize % 8)
+ return false;
+ assert((VecSize % 8) == 0 && "vector size not a multiple of element size?");
+ VecSize /= 8;
+ ElementSize /= 8;
- // Transfer alignment and TBAA info if present.
- TL->setAlignment(LI->getAlignment());
- FL->setAlignment(LI->getAlignment());
- if (MDNode *Tag = LI->getMetadata(LLVMContext::MD_tbaa)) {
- TL->setMetadata(LLVMContext::MD_tbaa, Tag);
- FL->setMetadata(LLVMContext::MD_tbaa, Tag);
- }
+ for (; I != E; ++I) {
+ if (!I->U)
+ continue; // Skip dead use.
- Value *V = IRB.CreateSelect(SI.getCondition(), TL, FL,
- LI->getName() + ".sroa.speculated");
+ uint64_t BeginOffset = I->BeginOffset - PartitionBeginOffset;
+ uint64_t BeginIndex = BeginOffset / ElementSize;
+ if (BeginIndex * ElementSize != BeginOffset ||
+ BeginIndex >= Ty->getNumElements())
+ return false;
+ uint64_t EndOffset = I->EndOffset - PartitionBeginOffset;
+ uint64_t EndIndex = EndOffset / ElementSize;
+ if (EndIndex * ElementSize != EndOffset ||
+ EndIndex > Ty->getNumElements())
+ return false;
- LoadInst *Loads[2] = { TL, FL };
- for (unsigned i = 0, e = 2; i != e; ++i) {
- if (PIs[i] != P.end()) {
- Use *LoadUse = &Loads[i]->getOperandUse(0);
- assert(PUs[i].U->get() == LoadUse->get());
- PUs[i].U = LoadUse;
- P.use_push_back(PIs[i], PUs[i]);
- }
+ // FIXME: We should build shuffle vector instructions to handle
+ // non-element-sized accesses.
+ if ((EndOffset - BeginOffset) != ElementSize &&
+ (EndOffset - BeginOffset) != VecSize)
+ return false;
+
+ if (MemIntrinsic *MI = dyn_cast<MemIntrinsic>(I->U->getUser())) {
+ if (MI->isVolatile())
+ return false;
+ if (MemTransferInst *MTI = dyn_cast<MemTransferInst>(I->U->getUser())) {
+ const AllocaPartitioning::MemTransferOffsets &MTO
+ = P.getMemTransferOffsets(*MTI);
+ if (!MTO.IsSplittable)
+ return false;
}
+ } else if (I->U->get()->getType()->getPointerElementType()->isStructTy()) {
+ // Disable vector promotion when there are loads or stores of an FCA.
+ return false;
+ } else if (!isa<LoadInst>(I->U->getUser()) &&
+ !isa<StoreInst>(I->U->getUser())) {
+ return false;
+ }
+ }
+ return true;
+}
- DEBUG(dbgs() << " speculated to: " << *V << "\n");
- LI->replaceAllUsesWith(V);
- Pass.DeadInsts.push_back(LI);
+/// \brief Test whether the given alloca partition can be promoted to an int.
+///
+/// This is a quick test to check whether we can rewrite a particular alloca
+/// partition (and its newly formed alloca) into an integer alloca suitable for
+/// promotion to an SSA value. We only can ensure this for a limited set of
+/// operations, and we don't want to do the rewrites unless we are confident
+/// that the result will be promotable, so we have an early test here.
+static bool isIntegerPromotionViable(const DataLayout &TD,
+ Type *AllocaTy,
+ uint64_t AllocBeginOffset,
+ AllocaPartitioning &P,
+ AllocaPartitioning::const_use_iterator I,
+ AllocaPartitioning::const_use_iterator E) {
+ IntegerType *Ty = dyn_cast<IntegerType>(AllocaTy);
+ if (!Ty || 8*TD.getTypeStoreSize(Ty) != Ty->getBitWidth())
+ return false;
+
+ // Check the uses to ensure the uses are (likely) promoteable integer uses.
+ // Also ensure that the alloca has a covering load or store. We don't want
+ // promote because of some other unsplittable entry (which we may make
+ // splittable later) and lose the ability to promote each element access.
+ bool WholeAllocaOp = false;
+ for (; I != E; ++I) {
+ if (!I->U)
+ continue; // Skip dead use.
+
+ // We can't reasonably handle cases where the load or store extends past
+ // the end of the aloca's type and into its padding.
+ if ((I->EndOffset - AllocBeginOffset) > TD.getTypeStoreSize(Ty))
+ return false;
+
+ if (LoadInst *LI = dyn_cast<LoadInst>(I->U->getUser())) {
+ if (LI->isVolatile() || !LI->getType()->isIntegerTy())
+ return false;
+ if (LI->getType() == Ty)
+ WholeAllocaOp = true;
+ } else if (StoreInst *SI = dyn_cast<StoreInst>(I->U->getUser())) {
+ if (SI->isVolatile() || !SI->getValueOperand()->getType()->isIntegerTy())
+ return false;
+ if (SI->getValueOperand()->getType() == Ty)
+ WholeAllocaOp = true;
+ } else if (MemIntrinsic *MI = dyn_cast<MemIntrinsic>(I->U->getUser())) {
+ if (MI->isVolatile())
+ return false;
+ if (MemTransferInst *MTI = dyn_cast<MemTransferInst>(I->U->getUser())) {
+ const AllocaPartitioning::MemTransferOffsets &MTO
+ = P.getMemTransferOffsets(*MTI);
+ if (!MTO.IsSplittable)
+ return false;
+ }
+ } else {
+ return false;
}
}
-};
+ return WholeAllocaOp;
+}
+namespace {
/// \brief Visitor to rewrite instructions using a partition of an alloca to
/// use a new alloca.
///
@@ -2044,7 +2144,7 @@
// Befriend the base class so it can delegate to private visit methods.
friend class llvm::InstVisitor<AllocaPartitionRewriter, bool>;
- const TargetData &TD;
+ const DataLayout &TD;
AllocaPartitioning &P;
SROA &Pass;
AllocaInst &OldAI, &NewAI;
@@ -2078,7 +2178,7 @@
std::string NamePrefix;
public:
- AllocaPartitionRewriter(const TargetData &TD, AllocaPartitioning &P,
+ AllocaPartitionRewriter(const DataLayout &TD, AllocaPartitioning &P,
AllocaPartitioning::iterator PI,
SROA &Pass, AllocaInst &OldAI, AllocaInst &NewAI,
uint64_t NewBeginOffset, uint64_t NewEndOffset)
@@ -2103,11 +2203,13 @@
"Only multiple-of-8 sized vector elements are viable");
ElementSize = VecTy->getScalarSizeInBits() / 8;
} else if (isIntegerPromotionViable(TD, NewAI.getAllocatedType(),
- P, I, E)) {
+ NewAllocaBeginOffset, P, I, E)) {
IntPromotionTy = cast<IntegerType>(NewAI.getAllocatedType());
}
bool CanSROA = true;
for (; I != E; ++I) {
+ if (!I->U)
+ continue; // Skip dead uses.
BeginOffset = I->BeginOffset;
EndOffset = I->EndOffset;
OldUse = I->U;
@@ -2141,18 +2243,36 @@
return getAdjustedPtr(IRB, TD, &NewAI, Offset, PointerTy, getName(""));
}
- unsigned getAdjustedAlign(uint64_t Offset) {
+ /// \brief Compute suitable alignment to access an offset into the new alloca.
+ unsigned getOffsetAlign(uint64_t Offset) {
unsigned NewAIAlign = NewAI.getAlignment();
if (!NewAIAlign)
NewAIAlign = TD.getABITypeAlignment(NewAI.getAllocatedType());
return MinAlign(NewAIAlign, Offset);
}
- unsigned getAdjustedAlign() {
- return getAdjustedAlign(BeginOffset - NewAllocaBeginOffset);
+
+ /// \brief Compute suitable alignment to access this partition of the new
+ /// alloca.
+ unsigned getPartitionAlign() {
+ return getOffsetAlign(BeginOffset - NewAllocaBeginOffset);
+ }
+
+ /// \brief Compute suitable alignment to access a type at an offset of the
+ /// new alloca.
+ ///
+ /// \returns zero if the type's ABI alignment is a suitable alignment,
+ /// otherwise returns the maximal suitable alignment.
+ unsigned getOffsetTypeAlign(Type *Ty, uint64_t Offset) {
+ unsigned Align = getOffsetAlign(Offset);
+ return Align == TD.getABITypeAlignment(Ty) ? 0 : Align;
}
- bool isTypeAlignSufficient(Type *Ty) {
- return TD.getABITypeAlignment(Ty) >= getAdjustedAlign();
+ /// \brief Compute suitable alignment to access a type at the beginning of
+ /// this partition of the new alloca.
+ ///
+ /// See \c getOffsetTypeAlign for details; this routine delegates to it.
+ unsigned getPartitionTypeAlign(Type *Ty) {
+ return getOffsetTypeAlign(Ty, BeginOffset - NewAllocaBeginOffset);
}
ConstantInt *getIndex(IRBuilder<> &IRB, uint64_t Offset) {
@@ -2171,8 +2291,15 @@
getName(".load"));
assert(Offset >= NewAllocaBeginOffset && "Out of bounds offset");
uint64_t RelOffset = Offset - NewAllocaBeginOffset;
- if (RelOffset)
- V = IRB.CreateLShr(V, RelOffset*8, getName(".shift"));
+ assert(TD.getTypeStoreSize(TargetTy) + RelOffset <=
+ TD.getTypeStoreSize(IntPromotionTy) &&
+ "Element load outside of alloca store");
+ uint64_t ShAmt = 8*RelOffset;
+ if (TD.isBigEndian())
+ ShAmt = 8*(TD.getTypeStoreSize(IntPromotionTy) -
+ TD.getTypeStoreSize(TargetTy) - RelOffset);
+ if (ShAmt)
+ V = IRB.CreateLShr(V, ShAmt, getName(".shift"));
if (TargetTy != IntPromotionTy) {
assert(TargetTy->getBitWidth() < IntPromotionTy->getBitWidth() &&
"Cannot extract to a larger integer!");
@@ -2191,11 +2318,17 @@
V = IRB.CreateZExt(V, IntPromotionTy, getName(".ext"));
assert(Offset >= NewAllocaBeginOffset && "Out of bounds offset");
uint64_t RelOffset = Offset - NewAllocaBeginOffset;
- if (RelOffset)
- V = IRB.CreateShl(V, RelOffset*8, getName(".shift"));
+ assert(TD.getTypeStoreSize(Ty) + RelOffset <=
+ TD.getTypeStoreSize(IntPromotionTy) &&
+ "Element store outside of alloca store");
+ uint64_t ShAmt = 8*RelOffset;
+ if (TD.isBigEndian())
+ ShAmt = 8*(TD.getTypeStoreSize(IntPromotionTy) - TD.getTypeStoreSize(Ty)
+ - RelOffset);
+ if (ShAmt)
+ V = IRB.CreateShl(V, ShAmt, getName(".shift"));
- APInt Mask = ~Ty->getMask().zext(IntPromotionTy->getBitWidth())
- .shl(RelOffset*8);
+ APInt Mask = ~Ty->getMask().zext(IntPromotionTy->getBitWidth()).shl(ShAmt);
Value *Old = IRB.CreateAnd(IRB.CreateAlignedLoad(&NewAI,
NewAI.getAlignment(),
getName(".oldload")),
@@ -2263,8 +2396,7 @@
Value *NewPtr = getAdjustedAllocaPtr(IRB,
LI.getPointerOperand()->getType());
LI.setOperand(0, NewPtr);
- if (LI.getAlignment() || !isTypeAlignSufficient(LI.getType()))
- LI.setAlignment(getAdjustedAlign());
+ LI.setAlignment(getPartitionTypeAlign(LI.getType()));
DEBUG(dbgs() << " to: " << LI << "\n");
deleteIfTriviallyDead(OldOp);
@@ -2313,15 +2445,17 @@
if (IntPromotionTy)
return rewriteIntegerStore(IRB, SI);
+ // Strip all inbounds GEPs and pointer casts to try to dig out any root
+ // alloca that should be re-examined after promoting this alloca.
+ if (SI.getValueOperand()->getType()->isPointerTy())
+ if (AllocaInst *AI = dyn_cast<AllocaInst>(SI.getValueOperand()
+ ->stripInBoundsOffsets()))
+ Pass.PostPromotionWorklist.insert(AI);
+
Value *NewPtr = getAdjustedAllocaPtr(IRB,
SI.getPointerOperand()->getType());
SI.setOperand(1, NewPtr);
- if (SI.getAlignment() ||
- !isTypeAlignSufficient(SI.getValueOperand()->getType()))
- SI.setAlignment(getAdjustedAlign());
- if (SI.getAlignment())
- SI.setAlignment(MinAlign(NewAI.getAlignment(),
- BeginOffset - NewAllocaBeginOffset));
+ SI.setAlignment(getPartitionTypeAlign(SI.getValueOperand()->getType()));
DEBUG(dbgs() << " to: " << SI << "\n");
deleteIfTriviallyDead(OldOp);
@@ -2338,7 +2472,7 @@
if (!isa<Constant>(II.getLength())) {
II.setDest(getAdjustedAllocaPtr(IRB, II.getRawDest()->getType()));
Type *CstTy = II.getAlignmentCst()->getType();
- II.setAlignment(ConstantInt::get(CstTy, getAdjustedAlign()));
+ II.setAlignment(ConstantInt::get(CstTy, getPartitionAlign()));
deleteIfTriviallyDead(OldPtr);
return false;
@@ -2362,7 +2496,7 @@
CallInst *New
= IRB.CreateMemSet(getAdjustedAllocaPtr(IRB,
II.getRawDest()->getType()),
- II.getValue(), Size, getAdjustedAlign(),
+ II.getValue(), Size, getPartitionAlign(),
II.isVolatile());
(void)New;
DEBUG(dbgs() << " to: " << *New << "\n");
@@ -2452,7 +2586,7 @@
unsigned Align = II.getAlignment();
if (Align > 1)
Align = MinAlign(RelOffset.zextOrTrunc(64).getZExtValue(),
- MinAlign(II.getAlignment(), getAdjustedAlign()));
+ MinAlign(II.getAlignment(), getPartitionAlign()));
// For unsplit intrinsics, we simply modify the source and destination
// pointers in place. This isn't just an optimization, it is a matter of
@@ -2544,6 +2678,12 @@
return false;
}
+ // Note that we clamp the alignment to 1 here as a 0 alignment for a memcpy
+ // is equivalent to 1, but that isn't true if we end up rewriting this as
+ // a load or store.
+ if (!Align)
+ Align = 1;
+
Value *SrcPtr = OtherPtr;
Value *DstPtr = &NewAI;
if (!IsDest)
@@ -2653,7 +2793,7 @@
// Befriend the base class so it can delegate to private visit methods.
friend class llvm::InstVisitor<AggLoadStoreRewriter, bool>;
- const TargetData &TD;
+ const DataLayout &TD;
/// Queue of pointer uses to analyze and potentially rewrite.
SmallVector<Use *, 8> Queue;
@@ -2666,7 +2806,7 @@
Use *U;
public:
- AggLoadStoreRewriter(const TargetData &TD) : TD(TD) {}
+ AggLoadStoreRewriter(const DataLayout &TD) : TD(TD) {}
/// Rewrite loads and stores through a pointer and all pointers derived from
/// it.
@@ -2866,7 +3006,7 @@
/// when the size or offset cause either end of type-based partition to be off.
/// Also, this is a best-effort routine. It is reasonable to give up and not
/// return a type if necessary.
-static Type *getTypePartition(const TargetData &TD, Type *Ty,
+static Type *getTypePartition(const DataLayout &TD, Type *Ty,
uint64_t Offset, uint64_t Size) {
if (Offset == 0 && TD.getTypeAllocSize(Ty) == Size)
return Ty;
@@ -2982,7 +3122,13 @@
AllocaPartitioning &P,
AllocaPartitioning::iterator PI) {
uint64_t AllocaSize = PI->EndOffset - PI->BeginOffset;
- if (P.use_begin(PI) == P.use_end(PI))
+ bool IsLive = false;
+ for (AllocaPartitioning::use_iterator UI = P.use_begin(PI),
+ UE = P.use_end(PI);
+ UI != UE && !IsLive; ++UI)
+ if (UI->U)
+ IsLive = true;
+ if (!IsLive)
return false; // No live uses left of this partition.
DEBUG(dbgs() << "Speculating PHIs and selects in partition "
@@ -2991,7 +3137,7 @@
PHIOrSelectSpeculator Speculator(*TD, P, *this);
DEBUG(dbgs() << " speculating ");
DEBUG(P.print(dbgs(), PI, ""));
- Speculator.visitUsers(P.use_begin(PI), P.use_end(PI));
+ Speculator.visitUsers(PI);
// Try to compute a friendly type for this partition of the alloca. This
// won't always succeed, in which case we fall back to a legal integer type
@@ -3046,11 +3192,16 @@
<< "[" << PI->BeginOffset << "," << PI->EndOffset << ") to: "
<< *NewAI << "\n");
+ // Track the high watermark of the post-promotion worklist. We will reset it
+ // to this point if the alloca is not in fact scheduled for promotion.
+ unsigned PPWOldSize = PostPromotionWorklist.size();
+
AllocaPartitionRewriter Rewriter(*TD, P, PI, *this, AI, *NewAI,
PI->BeginOffset, PI->EndOffset);
DEBUG(dbgs() << " rewriting ");
DEBUG(P.print(dbgs(), PI, ""));
- if (Rewriter.visitUsers(P.use_begin(PI), P.use_end(PI))) {
+ bool Promotable = Rewriter.visitUsers(P.use_begin(PI), P.use_end(PI));
+ if (Promotable) {
DEBUG(dbgs() << " and queuing for promotion\n");
PromotableAllocas.push_back(NewAI);
} else if (NewAI != &AI) {
@@ -3059,6 +3210,12 @@
// alloca which didn't actually change and didn't get promoted.
Worklist.insert(NewAI);
}
+
+ // Drop any post-promotion work items if promotion didn't happen.
+ if (!Promotable)
+ while (PostPromotionWorklist.size() > PPWOldSize)
+ PostPromotionWorklist.pop_back();
+
return true;
}
@@ -3092,13 +3249,6 @@
TD->getTypeAllocSize(AI.getAllocatedType()) == 0)
return false;
- // First check if this is a non-aggregate type that we should simply promote.
- if (!AI.getAllocatedType()->isAggregateType() && isAllocaPromotable(&AI)) {
- DEBUG(dbgs() << " Trivially scalar type, queuing for promotion...\n");
- PromotableAllocas.push_back(&AI);
- return false;
- }
-
bool Changed = false;
// First, split any FCA loads and stores touching this alloca to promote
@@ -3112,10 +3262,6 @@
if (P.isEscaped())
return Changed;
- // No partitions to split. Leave the dead alloca for a later pass to clean up.
- if (P.begin() == P.end())
- return Changed;
-
// Delete all the dead users of this alloca before splitting and rewriting it.
for (AllocaPartitioning::dead_user_iterator DI = P.dead_user_begin(),
DE = P.dead_user_end();
@@ -3137,6 +3283,10 @@
}
}
+ // No partitions to split. Leave the dead alloca for a later pass to clean up.
+ if (P.begin() == P.end())
+ return Changed;
+
return splitAlloca(AI, P) || Changed;
}
@@ -3238,15 +3388,17 @@
const SetType &Set;
public:
+ typedef AllocaInst *argument_type;
+
IsAllocaInSet(const SetType &Set) : Set(Set) {}
- bool operator()(AllocaInst *AI) { return Set.count(AI); }
+ bool operator()(AllocaInst *AI) const { return Set.count(AI); }
};
}
bool SROA::runOnFunction(Function &F) {
DEBUG(dbgs() << "SROA function: " << F.getName() << "\n");
C = &F.getContext();
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
if (!TD) {
DEBUG(dbgs() << " Skipping SROA -- no target data!\n");
return false;
@@ -3264,19 +3416,29 @@
// the list of promotable allocas.
SmallPtrSet<AllocaInst *, 4> DeletedAllocas;
- while (!Worklist.empty()) {
- Changed |= runOnAlloca(*Worklist.pop_back_val());
- deleteDeadInstructions(DeletedAllocas);
- if (!DeletedAllocas.empty()) {
- PromotableAllocas.erase(std::remove_if(PromotableAllocas.begin(),
- PromotableAllocas.end(),
- IsAllocaInSet(DeletedAllocas)),
- PromotableAllocas.end());
- DeletedAllocas.clear();
+ do {
+ while (!Worklist.empty()) {
+ Changed |= runOnAlloca(*Worklist.pop_back_val());
+ deleteDeadInstructions(DeletedAllocas);
+
+ // Remove the deleted allocas from various lists so that we don't try to
+ // continue processing them.
+ if (!DeletedAllocas.empty()) {
+ Worklist.remove_if(IsAllocaInSet(DeletedAllocas));
+ PostPromotionWorklist.remove_if(IsAllocaInSet(DeletedAllocas));
+ PromotableAllocas.erase(std::remove_if(PromotableAllocas.begin(),
+ PromotableAllocas.end(),
+ IsAllocaInSet(DeletedAllocas)),
+ PromotableAllocas.end());
+ DeletedAllocas.clear();
+ }
}
- }
- Changed |= promoteAllocas(F);
+ Changed |= promoteAllocas(F);
+
+ Worklist = PostPromotionWorklist;
+ PostPromotionWorklist.clear();
+ } while (!Worklist.empty());
return Changed;
}
Modified: llvm/branches/R600/lib/Transforms/Scalar/Scalar.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/Scalar.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/Scalar.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/Scalar.cpp Thu Oct 11 16:28:00 2012
@@ -19,7 +19,7 @@
#include "llvm/PassManager.h"
#include "llvm/Analysis/Passes.h"
#include "llvm/Analysis/Verifier.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Transforms/Scalar.h"
using namespace llvm;
Modified: llvm/branches/R600/lib/Transforms/Scalar/ScalarReplAggregates.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/ScalarReplAggregates.cpp Thu Oct 11 16:28:00 2012
@@ -46,7 +46,7 @@
#include "llvm/Support/GetElementPtrTypeIterator.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Transforms/Utils/PromoteMemToReg.h"
#include "llvm/Transforms/Utils/SSAUpdater.h"
@@ -87,7 +87,7 @@
private:
bool HasDomTree;
- TargetData *TD;
+ DataLayout *TD;
/// DeadInsts - Keep track of instructions we have made dead, so that
/// we can remove them after we are done working.
@@ -258,7 +258,7 @@
class ConvertToScalarInfo {
/// AllocaSize - The size of the alloca being considered in bytes.
unsigned AllocaSize;
- const TargetData &TD;
+ const DataLayout &TD;
unsigned ScalarLoadThreshold;
/// IsNotTrivial - This is set to true if there is some access to the object
@@ -301,7 +301,7 @@
bool HadDynamicAccess;
public:
- explicit ConvertToScalarInfo(unsigned Size, const TargetData &td,
+ explicit ConvertToScalarInfo(unsigned Size, const DataLayout &td,
unsigned SLT)
: AllocaSize(Size), TD(td), ScalarLoadThreshold(SLT), IsNotTrivial(false),
ScalarKind(Unknown), VectorTy(0), HadNonMemTransferAccess(false),
@@ -1020,11 +1020,11 @@
bool SROA::runOnFunction(Function &F) {
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
bool Changed = performPromotion(F);
- // FIXME: ScalarRepl currently depends on TargetData more than it
+ // FIXME: ScalarRepl currently depends on DataLayout more than it
// theoretically needs to. It should be refactored in order to support
// target-independent IR. Until this is done, just skip the actual
// scalar-replacement portion of this pass.
@@ -1134,7 +1134,7 @@
///
/// We can do this to a select if its only uses are loads and if the operand to
/// the select can be loaded unconditionally.
-static bool isSafeSelectToSpeculate(SelectInst *SI, const TargetData *TD) {
+static bool isSafeSelectToSpeculate(SelectInst *SI, const DataLayout *TD) {
bool TDerefable = SI->getTrueValue()->isDereferenceablePointer();
bool FDerefable = SI->getFalseValue()->isDereferenceablePointer();
@@ -1172,7 +1172,7 @@
///
/// We can do this to a select if its only uses are loads and if the operand to
/// the select can be loaded unconditionally.
-static bool isSafePHIToSpeculate(PHINode *PN, const TargetData *TD) {
+static bool isSafePHIToSpeculate(PHINode *PN, const DataLayout *TD) {
// For now, we can only do this promotion if the load is in the same block as
// the PHI, and if there are no stores between the phi and load.
// TODO: Allow recursive phi users.
@@ -1236,7 +1236,7 @@
/// direct (non-volatile) loads and stores to it. If the alloca is close but
/// not quite there, this will transform the code to allow promotion. As such,
/// it is a non-pure predicate.
-static bool tryToMakeAllocaBePromotable(AllocaInst *AI, const TargetData *TD) {
+static bool tryToMakeAllocaBePromotable(AllocaInst *AI, const DataLayout *TD) {
SetVector<Instruction*, SmallVector<Instruction*, 4>,
SmallPtrSet<Instruction*, 4> > InstsToRewrite;
@@ -2537,7 +2537,7 @@
/// HasPadding - Return true if the specified type has any structure or
/// alignment padding in between the elements that would be split apart
/// by SROA; return false otherwise.
-static bool HasPadding(Type *Ty, const TargetData &TD) {
+static bool HasPadding(Type *Ty, const DataLayout &TD) {
if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
Ty = ATy->getElementType();
return TD.getTypeSizeInBits(Ty) != TD.getTypeAllocSizeInBits(Ty);
Modified: llvm/branches/R600/lib/Transforms/Scalar/SimplifyCFGPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/SimplifyCFGPass.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/SimplifyCFGPass.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/SimplifyCFGPass.cpp Thu Oct 11 16:28:00 2012
@@ -31,7 +31,7 @@
#include "llvm/Attributes.h"
#include "llvm/Support/CFG.h"
#include "llvm/Pass.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/Statistic.h"
@@ -293,7 +293,7 @@
/// iterativelySimplifyCFG - Call SimplifyCFG on all the blocks in the function,
/// iterating until no more changes are made.
-static bool iterativelySimplifyCFG(Function &F, const TargetData *TD) {
+static bool iterativelySimplifyCFG(Function &F, const DataLayout *TD) {
bool Changed = false;
bool LocalChange = true;
while (LocalChange) {
@@ -316,7 +316,7 @@
// simplify the CFG.
//
bool CFGSimplifyPass::runOnFunction(Function &F) {
- const TargetData *TD = getAnalysisIfAvailable<TargetData>();
+ const DataLayout *TD = getAnalysisIfAvailable<DataLayout>();
bool EverChanged = removeUnreachableBlocksFromFn(F);
EverChanged |= mergeEmptyReturnBlocks(F);
EverChanged |= iterativelySimplifyCFG(F, TD);
Modified: llvm/branches/R600/lib/Transforms/Scalar/SimplifyLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Scalar/SimplifyLibCalls.cpp Thu Oct 11 16:28:00 2012
@@ -31,7 +31,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Config/config.h" // FIXME: Shouldn't depend on host!
using namespace llvm;
@@ -53,7 +53,7 @@
class LibCallOptimization {
protected:
Function *Caller;
- const TargetData *TD;
+ const DataLayout *TD;
const TargetLibraryInfo *TLI;
LLVMContext* Context;
public:
@@ -68,7 +68,7 @@
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B)
=0;
- Value *OptimizeCall(CallInst *CI, const TargetData *TD,
+ Value *OptimizeCall(CallInst *CI, const DataLayout *TD,
const TargetLibraryInfo *TLI, IRBuilder<> &B) {
Caller = CI->getParent()->getParent();
this->TD = TD;
@@ -159,7 +159,7 @@
if (Len == 0)
return Dst;
- // These optimizations require TargetData.
+ // These optimizations require DataLayout.
if (!TD) return 0;
return EmitStrLenMemCpy(Src, Dst, Len, B);
@@ -220,7 +220,7 @@
// strncat(x, c, 0) -> x
if (SrcLen == 0 || Len == 0) return Dst;
- // These optimizations require TargetData.
+ // These optimizations require DataLayout.
if (!TD) return 0;
// We don't optimize this case
@@ -251,7 +251,7 @@
// of the input string and turn this into memchr.
ConstantInt *CharC = dyn_cast<ConstantInt>(CI->getArgOperand(1));
if (CharC == 0) {
- // These optimizations require TargetData.
+ // These optimizations require DataLayout.
if (!TD) return 0;
uint64_t Len = GetStringLength(SrcStr);
@@ -356,7 +356,7 @@
uint64_t Len1 = GetStringLength(Str1P);
uint64_t Len2 = GetStringLength(Str2P);
if (Len1 && Len2) {
- // These optimizations require TargetData.
+ // These optimizations require DataLayout.
if (!TD) return 0;
return EmitMemCmp(Str1P, Str2P,
@@ -444,7 +444,7 @@
if (Dst == Src) // strcpy(x,x) -> x
return Src;
- // These optimizations require TargetData.
+ // These optimizations require DataLayout.
if (!TD) return 0;
// See if we can get the length of the input string.
@@ -481,7 +481,7 @@
FT->getParamType(0) != B.getInt8PtrTy())
return 0;
- // These optimizations require TargetData.
+ // These optimizations require DataLayout.
if (!TD) return 0;
Value *Dst = CI->getArgOperand(0), *Src = CI->getArgOperand(1);
@@ -543,7 +543,7 @@
if (Len == 0) return Dst; // strncpy(x, y, 0) -> x
- // These optimizations require TargetData.
+ // These optimizations require DataLayout.
if (!TD) return 0;
// Let strncpy handle the zero padding
@@ -636,7 +636,9 @@
if (isa<ConstantPointerNull>(EndPtr)) {
// With a null EndPtr, this function won't capture the main argument.
// It would be readonly too, except that it still may write to errno.
- CI->addAttribute(1, Attribute::NoCapture);
+ Attributes::Builder B;
+ B.addAttribute(Attributes::NoCapture);
+ CI->addAttribute(1, Attributes::get(B));
}
return 0;
@@ -832,7 +834,7 @@
struct MemCpyOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
- // These optimizations require TargetData.
+ // These optimizations require DataLayout.
if (!TD) return 0;
FunctionType *FT = Callee->getFunctionType();
@@ -854,7 +856,7 @@
struct MemMoveOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
- // These optimizations require TargetData.
+ // These optimizations require DataLayout.
if (!TD) return 0;
FunctionType *FT = Callee->getFunctionType();
@@ -876,7 +878,7 @@
struct MemSetOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
- // These optimizations require TargetData.
+ // These optimizations require DataLayout.
if (!TD) return 0;
FunctionType *FT = Callee->getFunctionType();
@@ -1304,7 +1306,7 @@
if (FormatStr[i] == '%')
return 0; // we found a format specifier, bail out.
- // These optimizations require TargetData.
+ // These optimizations require DataLayout.
if (!TD) return 0;
// sprintf(str, fmt) -> llvm.memcpy(str, fmt, strlen(fmt)+1, 1)
@@ -1334,7 +1336,7 @@
}
if (FormatStr[1] == 's') {
- // These optimizations require TargetData.
+ // These optimizations require DataLayout.
if (!TD) return 0;
// sprintf(dest, "%s", str) -> llvm.memcpy(dest, str, strlen(str)+1, 1)
@@ -1422,7 +1424,7 @@
struct FPutsOpt : public LibCallOptimization {
virtual Value *CallOptimizer(Function *Callee, CallInst *CI, IRBuilder<> &B) {
- // These optimizations require TargetData.
+ // These optimizations require DataLayout.
if (!TD) return 0;
// Require two pointers. Also, we can't optimize if return value is used.
@@ -1459,7 +1461,7 @@
if (FormatStr[i] == '%') // Could handle %% -> % if we cared.
return 0; // We found a format specifier.
- // These optimizations require TargetData.
+ // These optimizations require DataLayout.
if (!TD) return 0;
Value *NewCI = EmitFWrite(CI->getArgOperand(1),
@@ -1749,7 +1751,7 @@
if (Optimizations.empty())
InitOptimizations();
- const TargetData *TD = getAnalysisIfAvailable<TargetData>();
+ const DataLayout *TD = getAnalysisIfAvailable<DataLayout>();
IRBuilder<> Builder(F.getContext());
Modified: llvm/branches/R600/lib/Transforms/Utils/AddrModeMatcher.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Utils/AddrModeMatcher.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Utils/AddrModeMatcher.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Utils/AddrModeMatcher.cpp Thu Oct 11 16:28:00 2012
@@ -16,7 +16,7 @@
#include "llvm/GlobalValue.h"
#include "llvm/Instruction.h"
#include "llvm/Assembly/Writer.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/GetElementPtrTypeIterator.h"
#include "llvm/Support/PatternMatch.h"
@@ -221,7 +221,7 @@
unsigned VariableScale = 0;
int64_t ConstantOffset = 0;
- const TargetData *TD = TLI.getTargetData();
+ const DataLayout *TD = TLI.getDataLayout();
gep_type_iterator GTI = gep_type_begin(AddrInst);
for (unsigned i = 1, e = AddrInst->getNumOperands(); i != e; ++i, ++GTI) {
if (StructType *STy = dyn_cast<StructType>(*GTI)) {
Modified: llvm/branches/R600/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Utils/BasicBlockUtils.cpp Thu Oct 11 16:28:00 2012
@@ -22,7 +22,7 @@
#include "llvm/Analysis/Dominators.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/MemoryDependenceAnalysis.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/ErrorHandling.h"
Modified: llvm/branches/R600/lib/Transforms/Utils/BuildLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Utils/BuildLibCalls.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Utils/BuildLibCalls.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Utils/BuildLibCalls.cpp Thu Oct 11 16:28:00 2012
@@ -22,7 +22,7 @@
#include "llvm/Module.h"
#include "llvm/Type.h"
#include "llvm/ADT/SmallString.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
using namespace llvm;
@@ -34,16 +34,16 @@
/// EmitStrLen - Emit a call to the strlen function to the builder, for the
/// specified pointer. This always returns an integer value of size intptr_t.
-Value *llvm::EmitStrLen(Value *Ptr, IRBuilder<> &B, const TargetData *TD,
+Value *llvm::EmitStrLen(Value *Ptr, IRBuilder<> &B, const DataLayout *TD,
const TargetLibraryInfo *TLI) {
if (!TLI->has(LibFunc::strlen))
return 0;
Module *M = B.GetInsertBlock()->getParent()->getParent();
AttributeWithIndex AWI[2];
- AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture);
- AWI[1] = AttributeWithIndex::get(~0u, Attribute::ReadOnly |
- Attribute::NoUnwind);
+ AWI[0] = AttributeWithIndex::get(1, Attributes::NoCapture);
+ Attributes::AttrVal AVs[2] = { Attributes::ReadOnly, Attributes::NoUnwind };
+ AWI[1] = AttributeWithIndex::get(~0u, ArrayRef<Attributes::AttrVal>(AVs, 2));
LLVMContext &Context = B.GetInsertBlock()->getContext();
Constant *StrLen = M->getOrInsertFunction("strlen", AttrListPtr::get(AWI),
@@ -61,15 +61,15 @@
/// specified pointer. Ptr is required to be some pointer type, MaxLen must
/// be of size_t type, and the return value has 'intptr_t' type.
Value *llvm::EmitStrNLen(Value *Ptr, Value *MaxLen, IRBuilder<> &B,
- const TargetData *TD, const TargetLibraryInfo *TLI) {
+ const DataLayout *TD, const TargetLibraryInfo *TLI) {
if (!TLI->has(LibFunc::strnlen))
return 0;
Module *M = B.GetInsertBlock()->getParent()->getParent();
AttributeWithIndex AWI[2];
- AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture);
- AWI[1] = AttributeWithIndex::get(~0u, Attribute::ReadOnly |
- Attribute::NoUnwind);
+ AWI[0] = AttributeWithIndex::get(1, Attributes::NoCapture);
+ Attributes::AttrVal AVs[2] = { Attributes::ReadOnly, Attributes::NoUnwind };
+ AWI[1] = AttributeWithIndex::get(~0u, ArrayRef<Attributes::AttrVal>(AVs, 2));
LLVMContext &Context = B.GetInsertBlock()->getContext();
Constant *StrNLen = M->getOrInsertFunction("strnlen", AttrListPtr::get(AWI),
@@ -88,13 +88,14 @@
/// specified pointer and character. Ptr is required to be some pointer type,
/// and the return value has 'i8*' type.
Value *llvm::EmitStrChr(Value *Ptr, char C, IRBuilder<> &B,
- const TargetData *TD, const TargetLibraryInfo *TLI) {
+ const DataLayout *TD, const TargetLibraryInfo *TLI) {
if (!TLI->has(LibFunc::strchr))
return 0;
Module *M = B.GetInsertBlock()->getParent()->getParent();
+ Attributes::AttrVal AVs[2] = { Attributes::ReadOnly, Attributes::NoUnwind };
AttributeWithIndex AWI =
- AttributeWithIndex::get(~0u, Attribute::ReadOnly | Attribute::NoUnwind);
+ AttributeWithIndex::get(~0u, ArrayRef<Attributes::AttrVal>(AVs, 2));
Type *I8Ptr = B.getInt8PtrTy();
Type *I32Ty = B.getInt32Ty();
@@ -109,17 +110,17 @@
/// EmitStrNCmp - Emit a call to the strncmp function to the builder.
Value *llvm::EmitStrNCmp(Value *Ptr1, Value *Ptr2, Value *Len,
- IRBuilder<> &B, const TargetData *TD,
+ IRBuilder<> &B, const DataLayout *TD,
const TargetLibraryInfo *TLI) {
if (!TLI->has(LibFunc::strncmp))
return 0;
Module *M = B.GetInsertBlock()->getParent()->getParent();
AttributeWithIndex AWI[3];
- AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture);
- AWI[1] = AttributeWithIndex::get(2, Attribute::NoCapture);
- AWI[2] = AttributeWithIndex::get(~0u, Attribute::ReadOnly |
- Attribute::NoUnwind);
+ AWI[0] = AttributeWithIndex::get(1, Attributes::NoCapture);
+ AWI[1] = AttributeWithIndex::get(2, Attributes::NoCapture);
+ Attributes::AttrVal AVs[2] = { Attributes::ReadOnly, Attributes::NoUnwind };
+ AWI[2] = AttributeWithIndex::get(~0u, ArrayRef<Attributes::AttrVal>(AVs, 2));
LLVMContext &Context = B.GetInsertBlock()->getContext();
Value *StrNCmp = M->getOrInsertFunction("strncmp", AttrListPtr::get(AWI),
@@ -139,15 +140,15 @@
/// EmitStrCpy - Emit a call to the strcpy function to the builder, for the
/// specified pointer arguments.
Value *llvm::EmitStrCpy(Value *Dst, Value *Src, IRBuilder<> &B,
- const TargetData *TD, const TargetLibraryInfo *TLI,
+ const DataLayout *TD, const TargetLibraryInfo *TLI,
StringRef Name) {
if (!TLI->has(LibFunc::strcpy))
return 0;
Module *M = B.GetInsertBlock()->getParent()->getParent();
AttributeWithIndex AWI[2];
- AWI[0] = AttributeWithIndex::get(2, Attribute::NoCapture);
- AWI[1] = AttributeWithIndex::get(~0u, Attribute::NoUnwind);
+ AWI[0] = AttributeWithIndex::get(2, Attributes::NoCapture);
+ AWI[1] = AttributeWithIndex::get(~0u, Attributes::NoUnwind);
Type *I8Ptr = B.getInt8PtrTy();
Value *StrCpy = M->getOrInsertFunction(Name, AttrListPtr::get(AWI),
I8Ptr, I8Ptr, I8Ptr, NULL);
@@ -161,15 +162,15 @@
/// EmitStrNCpy - Emit a call to the strncpy function to the builder, for the
/// specified pointer arguments.
Value *llvm::EmitStrNCpy(Value *Dst, Value *Src, Value *Len,
- IRBuilder<> &B, const TargetData *TD,
+ IRBuilder<> &B, const DataLayout *TD,
const TargetLibraryInfo *TLI, StringRef Name) {
if (!TLI->has(LibFunc::strncpy))
return 0;
Module *M = B.GetInsertBlock()->getParent()->getParent();
AttributeWithIndex AWI[2];
- AWI[0] = AttributeWithIndex::get(2, Attribute::NoCapture);
- AWI[1] = AttributeWithIndex::get(~0u, Attribute::NoUnwind);
+ AWI[0] = AttributeWithIndex::get(2, Attributes::NoCapture);
+ AWI[1] = AttributeWithIndex::get(~0u, Attributes::NoUnwind);
Type *I8Ptr = B.getInt8PtrTy();
Value *StrNCpy = M->getOrInsertFunction(Name, AttrListPtr::get(AWI),
I8Ptr, I8Ptr, I8Ptr,
@@ -185,14 +186,14 @@
/// This expects that the Len and ObjSize have type 'intptr_t' and Dst/Src
/// are pointers.
Value *llvm::EmitMemCpyChk(Value *Dst, Value *Src, Value *Len, Value *ObjSize,
- IRBuilder<> &B, const TargetData *TD,
+ IRBuilder<> &B, const DataLayout *TD,
const TargetLibraryInfo *TLI) {
if (!TLI->has(LibFunc::memcpy_chk))
return 0;
Module *M = B.GetInsertBlock()->getParent()->getParent();
AttributeWithIndex AWI;
- AWI = AttributeWithIndex::get(~0u, Attribute::NoUnwind);
+ AWI = AttributeWithIndex::get(~0u, Attributes::NoUnwind);
LLVMContext &Context = B.GetInsertBlock()->getContext();
Value *MemCpy = M->getOrInsertFunction("__memcpy_chk",
AttrListPtr::get(AWI),
@@ -212,14 +213,15 @@
/// EmitMemChr - Emit a call to the memchr function. This assumes that Ptr is
/// a pointer, Val is an i32 value, and Len is an 'intptr_t' value.
Value *llvm::EmitMemChr(Value *Ptr, Value *Val,
- Value *Len, IRBuilder<> &B, const TargetData *TD,
+ Value *Len, IRBuilder<> &B, const DataLayout *TD,
const TargetLibraryInfo *TLI) {
if (!TLI->has(LibFunc::memchr))
return 0;
Module *M = B.GetInsertBlock()->getParent()->getParent();
AttributeWithIndex AWI;
- AWI = AttributeWithIndex::get(~0u, Attribute::ReadOnly | Attribute::NoUnwind);
+ Attributes::AttrVal AVs[2] = { Attributes::ReadOnly, Attributes::NoUnwind };
+ AWI = AttributeWithIndex::get(~0u, ArrayRef<Attributes::AttrVal>(AVs, 2));
LLVMContext &Context = B.GetInsertBlock()->getContext();
Value *MemChr = M->getOrInsertFunction("memchr", AttrListPtr::get(AWI),
B.getInt8PtrTy(),
@@ -237,17 +239,17 @@
/// EmitMemCmp - Emit a call to the memcmp function.
Value *llvm::EmitMemCmp(Value *Ptr1, Value *Ptr2,
- Value *Len, IRBuilder<> &B, const TargetData *TD,
+ Value *Len, IRBuilder<> &B, const DataLayout *TD,
const TargetLibraryInfo *TLI) {
if (!TLI->has(LibFunc::memcmp))
return 0;
Module *M = B.GetInsertBlock()->getParent()->getParent();
AttributeWithIndex AWI[3];
- AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture);
- AWI[1] = AttributeWithIndex::get(2, Attribute::NoCapture);
- AWI[2] = AttributeWithIndex::get(~0u, Attribute::ReadOnly |
- Attribute::NoUnwind);
+ AWI[0] = AttributeWithIndex::get(1, Attributes::NoCapture);
+ AWI[1] = AttributeWithIndex::get(2, Attributes::NoCapture);
+ Attributes::AttrVal AVs[2] = { Attributes::ReadOnly, Attributes::NoUnwind };
+ AWI[2] = AttributeWithIndex::get(~0u, ArrayRef<Attributes::AttrVal>(AVs, 2));
LLVMContext &Context = B.GetInsertBlock()->getContext();
Value *MemCmp = M->getOrInsertFunction("memcmp", AttrListPtr::get(AWI),
@@ -294,7 +296,7 @@
/// EmitPutChar - Emit a call to the putchar function. This assumes that Char
/// is an integer.
-Value *llvm::EmitPutChar(Value *Char, IRBuilder<> &B, const TargetData *TD,
+Value *llvm::EmitPutChar(Value *Char, IRBuilder<> &B, const DataLayout *TD,
const TargetLibraryInfo *TLI) {
if (!TLI->has(LibFunc::putchar))
return 0;
@@ -316,15 +318,15 @@
/// EmitPutS - Emit a call to the puts function. This assumes that Str is
/// some pointer.
-Value *llvm::EmitPutS(Value *Str, IRBuilder<> &B, const TargetData *TD,
+Value *llvm::EmitPutS(Value *Str, IRBuilder<> &B, const DataLayout *TD,
const TargetLibraryInfo *TLI) {
if (!TLI->has(LibFunc::puts))
return 0;
Module *M = B.GetInsertBlock()->getParent()->getParent();
AttributeWithIndex AWI[2];
- AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture);
- AWI[1] = AttributeWithIndex::get(~0u, Attribute::NoUnwind);
+ AWI[0] = AttributeWithIndex::get(1, Attributes::NoCapture);
+ AWI[1] = AttributeWithIndex::get(~0u, Attributes::NoUnwind);
Value *PutS = M->getOrInsertFunction("puts", AttrListPtr::get(AWI),
B.getInt32Ty(),
@@ -339,14 +341,14 @@
/// EmitFPutC - Emit a call to the fputc function. This assumes that Char is
/// an integer and File is a pointer to FILE.
Value *llvm::EmitFPutC(Value *Char, Value *File, IRBuilder<> &B,
- const TargetData *TD, const TargetLibraryInfo *TLI) {
+ const DataLayout *TD, const TargetLibraryInfo *TLI) {
if (!TLI->has(LibFunc::fputc))
return 0;
Module *M = B.GetInsertBlock()->getParent()->getParent();
AttributeWithIndex AWI[2];
- AWI[0] = AttributeWithIndex::get(2, Attribute::NoCapture);
- AWI[1] = AttributeWithIndex::get(~0u, Attribute::NoUnwind);
+ AWI[0] = AttributeWithIndex::get(2, Attributes::NoCapture);
+ AWI[1] = AttributeWithIndex::get(~0u, Attributes::NoUnwind);
Constant *F;
if (File->getType()->isPointerTy())
F = M->getOrInsertFunction("fputc", AttrListPtr::get(AWI),
@@ -370,15 +372,15 @@
/// EmitFPutS - Emit a call to the puts function. Str is required to be a
/// pointer and File is a pointer to FILE.
Value *llvm::EmitFPutS(Value *Str, Value *File, IRBuilder<> &B,
- const TargetData *TD, const TargetLibraryInfo *TLI) {
+ const DataLayout *TD, const TargetLibraryInfo *TLI) {
if (!TLI->has(LibFunc::fputs))
return 0;
Module *M = B.GetInsertBlock()->getParent()->getParent();
AttributeWithIndex AWI[3];
- AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture);
- AWI[1] = AttributeWithIndex::get(2, Attribute::NoCapture);
- AWI[2] = AttributeWithIndex::get(~0u, Attribute::NoUnwind);
+ AWI[0] = AttributeWithIndex::get(1, Attributes::NoCapture);
+ AWI[1] = AttributeWithIndex::get(2, Attributes::NoCapture);
+ AWI[2] = AttributeWithIndex::get(~0u, Attributes::NoUnwind);
StringRef FPutsName = TLI->getName(LibFunc::fputs);
Constant *F;
if (File->getType()->isPointerTy())
@@ -400,16 +402,16 @@
/// EmitFWrite - Emit a call to the fwrite function. This assumes that Ptr is
/// a pointer, Size is an 'intptr_t', and File is a pointer to FILE.
Value *llvm::EmitFWrite(Value *Ptr, Value *Size, Value *File,
- IRBuilder<> &B, const TargetData *TD,
+ IRBuilder<> &B, const DataLayout *TD,
const TargetLibraryInfo *TLI) {
if (!TLI->has(LibFunc::fwrite))
return 0;
Module *M = B.GetInsertBlock()->getParent()->getParent();
AttributeWithIndex AWI[3];
- AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture);
- AWI[1] = AttributeWithIndex::get(4, Attribute::NoCapture);
- AWI[2] = AttributeWithIndex::get(~0u, Attribute::NoUnwind);
+ AWI[0] = AttributeWithIndex::get(1, Attributes::NoCapture);
+ AWI[1] = AttributeWithIndex::get(4, Attributes::NoCapture);
+ AWI[2] = AttributeWithIndex::get(~0u, Attributes::NoUnwind);
LLVMContext &Context = B.GetInsertBlock()->getContext();
StringRef FWriteName = TLI->getName(LibFunc::fwrite);
Constant *F;
@@ -436,9 +438,9 @@
SimplifyFortifiedLibCalls::~SimplifyFortifiedLibCalls() { }
-bool SimplifyFortifiedLibCalls::fold(CallInst *CI, const TargetData *TD,
+bool SimplifyFortifiedLibCalls::fold(CallInst *CI, const DataLayout *TD,
const TargetLibraryInfo *TLI) {
- // We really need TargetData for later.
+ // We really need DataLayout for later.
if (!TD) return false;
this->CI = CI;
Modified: llvm/branches/R600/lib/Transforms/Utils/BypassSlowDivision.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Utils/BypassSlowDivision.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Utils/BypassSlowDivision.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Utils/BypassSlowDivision.cpp Thu Oct 11 16:28:00 2012
@@ -221,7 +221,7 @@
// be profitably bypassed and carried out with a shorter, faster divide.
bool llvm::bypassSlowDivision(Function &F,
Function::iterator &I,
- const DenseMap<Type*, Type*> &BypassTypeMap) {
+ const DenseMap<unsigned int, unsigned int> &BypassWidths) {
DivCacheTy DivCache;
bool MadeChange = false;
@@ -238,14 +238,23 @@
if (!UseDivOp && !UseRemOp)
continue;
- // Continue if div/rem type is not bypassed
- DenseMap<Type *, Type *>::const_iterator BT =
- BypassTypeMap.find(J->getType());
- if (BT == BypassTypeMap.end())
+ // Skip division on vector types, only optimize integer instructions
+ if (!J->getType()->isIntegerTy())
continue;
- IntegerType *BypassType = cast<IntegerType>(BT->second);
- MadeChange |= reuseOrInsertFastDiv(F, I, J, BypassType, UseDivOp,
+ // Get bitwidth of div/rem instruction
+ IntegerType *T = cast<IntegerType>(J->getType());
+ int bitwidth = T->getBitWidth();
+
+ // Continue if bitwidth is not bypassed
+ DenseMap<unsigned int, unsigned int>::const_iterator BI = BypassWidths.find(bitwidth);
+ if (BI == BypassWidths.end())
+ continue;
+
+ // Get type for div/rem instruction with bypass bitwidth
+ IntegerType *BT = IntegerType::get(J->getContext(), BI->second);
+
+ MadeChange |= reuseOrInsertFastDiv(F, I, J, BT, UseDivOp,
UseSignedOp, DivCache);
}
Modified: llvm/branches/R600/lib/Transforms/Utils/CloneFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Utils/CloneFunction.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Utils/CloneFunction.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Utils/CloneFunction.cpp Thu Oct 11 16:28:00 2012
@@ -202,14 +202,14 @@
bool ModuleLevelChanges;
const char *NameSuffix;
ClonedCodeInfo *CodeInfo;
- const TargetData *TD;
+ const DataLayout *TD;
public:
PruningFunctionCloner(Function *newFunc, const Function *oldFunc,
ValueToValueMapTy &valueMap,
bool moduleLevelChanges,
const char *nameSuffix,
ClonedCodeInfo *codeInfo,
- const TargetData *td)
+ const DataLayout *td)
: NewFunc(newFunc), OldFunc(oldFunc),
VMap(valueMap), ModuleLevelChanges(moduleLevelChanges),
NameSuffix(nameSuffix), CodeInfo(codeInfo), TD(td) {
@@ -365,7 +365,7 @@
SmallVectorImpl<ReturnInst*> &Returns,
const char *NameSuffix,
ClonedCodeInfo *CodeInfo,
- const TargetData *TD,
+ const DataLayout *TD,
Instruction *TheCall) {
assert(NameSuffix && "NameSuffix cannot be null!");
Modified: llvm/branches/R600/lib/Transforms/Utils/CodeExtractor.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Utils/CodeExtractor.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Utils/CodeExtractor.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Utils/CodeExtractor.cpp Thu Oct 11 16:28:00 2012
@@ -346,7 +346,7 @@
header->getName(), M);
// If the old function is no-throw, so is the new one.
if (oldFunction->doesNotThrow())
- newFunction->setDoesNotThrow(true);
+ newFunction->setDoesNotThrow();
newFunction->getBasicBlockList().push_back(newRootNode);
Modified: llvm/branches/R600/lib/Transforms/Utils/InlineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Utils/InlineFunction.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Utils/InlineFunction.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Utils/InlineFunction.cpp Thu Oct 11 16:28:00 2012
@@ -27,7 +27,7 @@
#include "llvm/Analysis/CallGraph.h"
#include "llvm/Analysis/InstructionSimplify.h"
#include "llvm/Support/CallSite.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Transforms/Utils/Local.h"
using namespace llvm;
@@ -357,7 +357,7 @@
Type *VoidPtrTy = Type::getInt8PtrTy(Context);
- // Create the alloca. If we have TargetData, use nice alignment.
+ // Create the alloca. If we have DataLayout, use nice alignment.
unsigned Align = 1;
if (IFI.TD)
Align = IFI.TD->getPrefTypeAlignment(AggTy);
Modified: llvm/branches/R600/lib/Transforms/Utils/Local.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Utils/Local.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Utils/Local.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Utils/Local.cpp Thu Oct 11 16:28:00 2012
@@ -39,7 +39,7 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/ValueHandle.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
using namespace llvm;
//===----------------------------------------------------------------------===//
@@ -397,7 +397,7 @@
///
/// This returns true if it changed the code, note that it can delete
/// instructions in other blocks as well in this block.
-bool llvm::SimplifyInstructionsInBlock(BasicBlock *BB, const TargetData *TD,
+bool llvm::SimplifyInstructionsInBlock(BasicBlock *BB, const DataLayout *TD,
const TargetLibraryInfo *TLI) {
bool MadeChange = false;
@@ -445,7 +445,7 @@
/// .. and delete the predecessor corresponding to the '1', this will attempt to
/// recursively fold the and to 0.
void llvm::RemovePredecessorAndSimplify(BasicBlock *BB, BasicBlock *Pred,
- TargetData *TD) {
+ DataLayout *TD) {
// This only adjusts blocks with PHI nodes.
if (!isa<PHINode>(BB->begin()))
return;
@@ -760,7 +760,7 @@
/// their preferred alignment from the beginning.
///
static unsigned enforceKnownAlignment(Value *V, unsigned Align,
- unsigned PrefAlign, const TargetData *TD) {
+ unsigned PrefAlign, const DataLayout *TD) {
V = V->stripPointerCasts();
if (AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
@@ -803,7 +803,7 @@
/// and it is more than the alignment of the ultimate object, see if we can
/// increase the alignment of the ultimate object, making this check succeed.
unsigned llvm::getOrEnforceKnownAlignment(Value *V, unsigned PrefAlign,
- const TargetData *TD) {
+ const DataLayout *TD) {
assert(V->getType()->isPointerTy() &&
"getOrEnforceKnownAlignment expects a pointer!");
unsigned BitWidth = TD ? TD->getPointerSizeInBits() : 64;
Modified: llvm/branches/R600/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Utils/SimplifyCFG.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Utils/SimplifyCFG.cpp Thu Oct 11 16:28:00 2012
@@ -39,7 +39,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/NoFolder.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include <algorithm>
#include <set>
@@ -79,7 +79,7 @@
};
class SimplifyCFGOpt {
- const TargetData *const TD;
+ const DataLayout *const TD;
Value *isValueEqualityComparison(TerminatorInst *TI);
BasicBlock *GetValueEqualityComparisonCases(TerminatorInst *TI,
@@ -99,7 +99,7 @@
bool SimplifyCondBranch(BranchInst *BI, IRBuilder <>&Builder);
public:
- explicit SimplifyCFGOpt(const TargetData *td) : TD(td) {}
+ explicit SimplifyCFGOpt(const DataLayout *td) : TD(td) {}
bool run(BasicBlock *BB);
};
}
@@ -382,7 +382,7 @@
/// GetConstantInt - Extract ConstantInt from value, looking through IntToPtr
/// and PointerNullValue. Return NULL if value is not a constant int.
-static ConstantInt *GetConstantInt(Value *V, const TargetData *TD) {
+static ConstantInt *GetConstantInt(Value *V, const DataLayout *TD) {
// Normal constant int.
ConstantInt *CI = dyn_cast<ConstantInt>(V);
if (CI || !TD || !isa<Constant>(V) || !V->getType()->isPointerTy())
@@ -416,7 +416,7 @@
/// Values vector.
static Value *
GatherConstantCompares(Value *V, std::vector<ConstantInt*> &Vals, Value *&Extra,
- const TargetData *TD, bool isEQ, unsigned &UsedICmps) {
+ const DataLayout *TD, bool isEQ, unsigned &UsedICmps) {
Instruction *I = dyn_cast<Instruction>(V);
if (I == 0) return 0;
@@ -982,7 +982,7 @@
Builder.SetInsertPoint(PTI);
// Convert pointer to int before we switch.
if (CV->getType()->isPointerTy()) {
- assert(TD && "Cannot switch on pointer without TargetData");
+ assert(TD && "Cannot switch on pointer without DataLayout");
CV = Builder.CreatePtrToInt(CV, TD->getIntPtrType(CV->getContext()),
"magicptr");
}
@@ -1510,7 +1510,7 @@
/// that is defined in the same block as the branch and if any PHI entries are
/// constants, thread edges corresponding to that entry to be branches to their
/// ultimate destination.
-static bool FoldCondBranchOnPHI(BranchInst *BI, const TargetData *TD) {
+static bool FoldCondBranchOnPHI(BranchInst *BI, const DataLayout *TD) {
BasicBlock *BB = BI->getParent();
PHINode *PN = dyn_cast<PHINode>(BI->getCondition());
// NOTE: we currently cannot transform this case if the PHI node is used
@@ -1606,7 +1606,7 @@
/// FoldTwoEntryPHINode - Given a BB that starts with the specified two-entry
/// PHI node, see if we can eliminate it.
-static bool FoldTwoEntryPHINode(PHINode *PN, const TargetData *TD) {
+static bool FoldTwoEntryPHINode(PHINode *PN, const DataLayout *TD) {
// Ok, this is a two entry PHI node. Check to see if this is a simple "if
// statement", which has a very simple dominance structure. Basically, we
// are trying to find the condition that is being branched on, which
@@ -2522,7 +2522,7 @@
/// We prefer to split the edge to 'end' so that there is a true/false entry to
/// the PHI, merging the third icmp into the switch.
static bool TryToSimplifyUncondBranchWithICmpInIt(ICmpInst *ICI,
- const TargetData *TD,
+ const DataLayout *TD,
IRBuilder<> &Builder) {
BasicBlock *BB = ICI->getParent();
@@ -2628,7 +2628,7 @@
/// SimplifyBranchOnICmpChain - The specified branch is a conditional branch.
/// Check to see if it is branching on an or/and chain of icmp instructions, and
/// fold it into a switch instruction if so.
-static bool SimplifyBranchOnICmpChain(BranchInst *BI, const TargetData *TD,
+static bool SimplifyBranchOnICmpChain(BranchInst *BI, const DataLayout *TD,
IRBuilder<> &Builder) {
Instruction *Cond = dyn_cast<Instruction>(BI->getCondition());
if (Cond == 0) return false;
@@ -2709,7 +2709,7 @@
Builder.SetInsertPoint(BI);
// Convert pointer to int before we switch.
if (CompVal->getType()->isPointerTy()) {
- assert(TD && "Cannot switch on pointer without TargetData");
+ assert(TD && "Cannot switch on pointer without DataLayout");
CompVal = Builder.CreatePtrToInt(CompVal,
TD->getIntPtrType(CompVal->getContext()),
"magicptr");
@@ -3258,7 +3258,7 @@
ConstantInt *Offset,
const SmallVector<std::pair<ConstantInt*, Constant*>, 4>& Values,
Constant *DefaultValue,
- const TargetData *TD);
+ const DataLayout *TD);
/// BuildLookup - Build instructions with Builder to retrieve the value at
/// the position given by Index in the lookup table.
@@ -3266,7 +3266,7 @@
/// WouldFitInRegister - Return true if a table with TableSize elements of
/// type ElementType would fit in a target-legal register.
- static bool WouldFitInRegister(const TargetData *TD,
+ static bool WouldFitInRegister(const DataLayout *TD,
uint64_t TableSize,
const Type *ElementType);
@@ -3305,7 +3305,7 @@
ConstantInt *Offset,
const SmallVector<std::pair<ConstantInt*, Constant*>, 4>& Values,
Constant *DefaultValue,
- const TargetData *TD) {
+ const DataLayout *TD) {
assert(Values.size() && "Can't build lookup table without values!");
assert(TableSize >= Values.size() && "Can't fit values in table!");
@@ -3411,7 +3411,7 @@
llvm_unreachable("Unknown lookup table kind!");
}
-bool SwitchLookupTable::WouldFitInRegister(const TargetData *TD,
+bool SwitchLookupTable::WouldFitInRegister(const DataLayout *TD,
uint64_t TableSize,
const Type *ElementType) {
if (!TD)
@@ -3433,7 +3433,7 @@
/// types of the results.
static bool ShouldBuildLookupTable(SwitchInst *SI,
uint64_t TableSize,
- const TargetData *TD,
+ const DataLayout *TD,
const SmallDenseMap<PHINode*, Type*>& ResultTypes) {
// The table density should be at least 40%. This is the same criterion as for
// jump tables, see SelectionDAGBuilder::handleJTSwitchCase.
@@ -3457,7 +3457,7 @@
/// replace the switch with lookup tables.
static bool SwitchToLookupTable(SwitchInst *SI,
IRBuilder<> &Builder,
- const TargetData* TD) {
+ const DataLayout* TD) {
assert(SI->getNumCases() > 1 && "Degenerate switch?");
// FIXME: Handle unreachable cases.
@@ -3786,11 +3786,12 @@
if (!C)
return false;
- if (!I->hasOneUse()) // Only look at single-use instructions, for compile time
+ if (I->use_empty())
return false;
if (C->isNullValue()) {
- Instruction *Use = I->use_back();
+ // Only look at the first use, avoid hurting compile time with long uselists
+ User *Use = *I->use_begin();
// Now make sure that there are no instructions in between that can alter
// control flow (eg. calls)
@@ -3915,6 +3916,6 @@
/// eliminates unreachable basic blocks, and does other "peephole" optimization
/// of the CFG. It returns true if a modification was made.
///
-bool llvm::SimplifyCFG(BasicBlock *BB, const TargetData *TD) {
+bool llvm::SimplifyCFG(BasicBlock *BB, const DataLayout *TD) {
return SimplifyCFGOpt(TD).run(BB);
}
Modified: llvm/branches/R600/lib/Transforms/Utils/SimplifyIndVar.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Utils/SimplifyIndVar.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Utils/SimplifyIndVar.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Utils/SimplifyIndVar.cpp Thu Oct 11 16:28:00 2012
@@ -24,7 +24,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Transforms/Utils/SimplifyIndVar.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
@@ -44,7 +44,7 @@
Loop *L;
LoopInfo *LI;
ScalarEvolution *SE;
- const TargetData *TD; // May be NULL
+ const DataLayout *TD; // May be NULL
SmallVectorImpl<WeakVH> &DeadInsts;
@@ -56,7 +56,7 @@
L(Loop),
LI(LPM->getAnalysisIfAvailable<LoopInfo>()),
SE(SE),
- TD(LPM->getAnalysisIfAvailable<TargetData>()),
+ TD(LPM->getAnalysisIfAvailable<DataLayout>()),
DeadInsts(Dead),
Changed(false) {
assert(LI && "IV simplification requires LoopInfo");
Modified: llvm/branches/R600/lib/Transforms/Utils/SimplifyInstructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Utils/SimplifyInstructions.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Utils/SimplifyInstructions.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Utils/SimplifyInstructions.cpp Thu Oct 11 16:28:00 2012
@@ -23,7 +23,7 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/Dominators.h"
#include "llvm/Analysis/InstructionSimplify.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/Utils/Local.h"
@@ -46,7 +46,7 @@
/// runOnFunction - Remove instructions that simplify.
bool runOnFunction(Function &F) {
const DominatorTree *DT = getAnalysisIfAvailable<DominatorTree>();
- const TargetData *TD = getAnalysisIfAvailable<TargetData>();
+ const DataLayout *TD = getAnalysisIfAvailable<DataLayout>();
const TargetLibraryInfo *TLI = &getAnalysis<TargetLibraryInfo>();
SmallPtrSet<const Instruction*, 8> S1, S2, *ToSimplify = &S1, *Next = &S2;
bool Changed = false;
Modified: llvm/branches/R600/lib/Transforms/Vectorize/BBVectorize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Transforms/Vectorize/BBVectorize.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Transforms/Vectorize/BBVectorize.cpp (original)
+++ llvm/branches/R600/lib/Transforms/Vectorize/BBVectorize.cpp Thu Oct 11 16:28:00 2012
@@ -41,7 +41,7 @@
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Support/ValueHandle.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Transforms/Vectorize.h"
#include <algorithm>
@@ -178,7 +178,7 @@
: BasicBlockPass(ID), Config(C) {
AA = &P->getAnalysis<AliasAnalysis>();
SE = &P->getAnalysis<ScalarEvolution>();
- TD = P->getAnalysisIfAvailable<TargetData>();
+ TD = P->getAnalysisIfAvailable<DataLayout>();
}
typedef std::pair<Value *, Value *> ValuePair;
@@ -192,7 +192,7 @@
AliasAnalysis *AA;
ScalarEvolution *SE;
- TargetData *TD;
+ DataLayout *TD;
// FIXME: const correct?
@@ -364,7 +364,7 @@
virtual bool runOnBasicBlock(BasicBlock &BB) {
AA = &getAnalysis<AliasAnalysis>();
SE = &getAnalysis<ScalarEvolution>();
- TD = getAnalysisIfAvailable<TargetData>();
+ TD = getAnalysisIfAvailable<DataLayout>();
return vectorizeBB(BB);
}
Modified: llvm/branches/R600/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/VMCore/AsmWriter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/branches/R600/lib/VMCore/AsmWriter.cpp Thu Oct 11 16:28:00 2012
@@ -1243,7 +1243,7 @@
// Print the type
TypePrinter.print(Operand->getType(), Out);
// Print parameter attributes list
- if (Attrs != Attribute::None)
+ if (Attrs.hasAttributes())
Out << ' ' << Attrs.getAsString();
Out << ' ';
// Print the operand
@@ -1556,7 +1556,7 @@
FunctionType *FT = F->getFunctionType();
const AttrListPtr &Attrs = F->getAttributes();
Attributes RetAttrs = Attrs.getRetAttributes();
- if (RetAttrs != Attribute::None)
+ if (RetAttrs.hasAttributes())
Out << Attrs.getRetAttributes().getAsString() << ' ';
TypePrinter.print(F->getReturnType(), Out);
Out << ' ';
@@ -1586,7 +1586,7 @@
TypePrinter.print(FT->getParamType(i), Out);
Attributes ArgAttrs = Attrs.getParamAttributes(i+1);
- if (ArgAttrs != Attribute::None)
+ if (ArgAttrs.hasAttributes())
Out << ' ' << ArgAttrs.getAsString();
}
}
@@ -1600,7 +1600,7 @@
if (F->hasUnnamedAddr())
Out << " unnamed_addr";
Attributes FnAttrs = Attrs.getFnAttributes();
- if (FnAttrs != Attribute::None)
+ if (FnAttrs.hasAttributes())
Out << ' ' << Attrs.getFnAttributes().getAsString();
if (F->hasSection()) {
Out << " section \"";
@@ -1634,7 +1634,7 @@
TypePrinter.print(Arg->getType(), Out);
// Output parameter attributes list
- if (Attrs != Attribute::None)
+ if (Attrs.hasAttributes())
Out << ' ' << Attrs.getAsString();
// Output name, if available...
@@ -1849,7 +1849,7 @@
Type *RetTy = FTy->getReturnType();
const AttrListPtr &PAL = CI->getAttributes();
- if (PAL.getRetAttributes() != Attribute::None)
+ if (PAL.getRetAttributes().hasAttributes())
Out << ' ' << PAL.getRetAttributes().getAsString();
// If possible, print out the short form of the call instruction. We can
@@ -1873,7 +1873,7 @@
writeParamOperand(CI->getArgOperand(op), PAL.getParamAttributes(op + 1));
}
Out << ')';
- if (PAL.getFnAttributes() != Attribute::None)
+ if (PAL.getFnAttributes().hasAttributes())
Out << ' ' << PAL.getFnAttributes().getAsString();
} else if (const InvokeInst *II = dyn_cast<InvokeInst>(&I)) {
Operand = II->getCalledValue();
@@ -1888,7 +1888,7 @@
PrintCallingConv(II->getCallingConv(), Out);
}
- if (PAL.getRetAttributes() != Attribute::None)
+ if (PAL.getRetAttributes().hasAttributes())
Out << ' ' << PAL.getRetAttributes().getAsString();
// If possible, print out the short form of the invoke instruction. We can
@@ -1913,7 +1913,7 @@
}
Out << ')';
- if (PAL.getFnAttributes() != Attribute::None)
+ if (PAL.getFnAttributes().hasAttributes())
Out << ' ' << PAL.getFnAttributes().getAsString();
Out << "\n to ";
Modified: llvm/branches/R600/lib/VMCore/Attributes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/VMCore/Attributes.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/VMCore/Attributes.cpp (original)
+++ llvm/branches/R600/lib/VMCore/Attributes.cpp Thu Oct 11 16:28:00 2012
@@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===//
#include "llvm/Attributes.h"
-#include "AttributesImpl.h"
#include "LLVMContextImpl.h"
#include "llvm/Type.h"
#include "llvm/ADT/StringExtras.h"
@@ -25,67 +24,174 @@
using namespace llvm;
//===----------------------------------------------------------------------===//
-// Attribute Function Definitions
+// Attributes Implementation
//===----------------------------------------------------------------------===//
+Attributes::Attributes(uint64_t Val) : Attrs(Val) {}
+
+Attributes::Attributes(AttributesImpl *A) : Attrs(A->Bits) {}
+
+Attributes::Attributes(const Attributes &A) : Attrs(A.Attrs) {}
+
+// FIXME: This is temporary until we have implemented the uniquified version of
+// AttributesImpl.
+Attributes Attributes::get(Attributes::Builder &B) {
+ return Attributes(B.Bits);
+}
+
+Attributes Attributes::get(LLVMContext &Context, Attributes::Builder &B) {
+ // If there are no attributes, return an empty Attributes class.
+ if (B.Bits == 0)
+ return Attributes();
+
+ // Otherwise, build a key to look up the existing attributes.
+ LLVMContextImpl *pImpl = Context.pImpl;
+ FoldingSetNodeID ID;
+ ID.AddInteger(B.Bits);
+
+ void *InsertPoint;
+ AttributesImpl *PA = pImpl->AttrsSet.FindNodeOrInsertPos(ID, InsertPoint);
+
+ if (!PA) {
+ // If we didn't find any existing attributes of the same shape then create a
+ // new one and insert it.
+ PA = new AttributesImpl(B.Bits);
+ pImpl->AttrsSet.InsertNode(PA, InsertPoint);
+ }
+
+ // Return the AttributesList that we found or created.
+ return Attributes(PA);
+}
+
+bool Attributes::hasAttribute(AttrVal Val) const {
+ return Attrs.hasAttribute(Val);
+}
+
+bool Attributes::hasAttributes(const Attributes &A) const {
+ return Attrs.hasAttributes(A);
+}
+
+/// This returns the alignment field of an attribute as a byte alignment value.
+unsigned Attributes::getAlignment() const {
+ if (!hasAttribute(Attributes::Alignment))
+ return 0;
+ return 1U << ((Attrs.getAlignment() >> 16) - 1);
+}
+
+/// This returns the stack alignment field of an attribute as a byte alignment
+/// value.
+unsigned Attributes::getStackAlignment() const {
+ if (!hasAttribute(Attributes::StackAlignment))
+ return 0;
+ return 1U << ((Attrs.getStackAlignment() >> 26) - 1);
+}
+
+bool Attributes::isEmptyOrSingleton() const {
+ return Attrs.isEmptyOrSingleton();
+}
+
+Attributes Attributes::operator | (const Attributes &A) const {
+ return Attributes(Raw() | A.Raw());
+}
+Attributes Attributes::operator & (const Attributes &A) const {
+ return Attributes(Raw() & A.Raw());
+}
+Attributes Attributes::operator ^ (const Attributes &A) const {
+ return Attributes(Raw() ^ A.Raw());
+}
+Attributes &Attributes::operator |= (const Attributes &A) {
+ Attrs.Bits |= A.Raw();
+ return *this;
+}
+Attributes &Attributes::operator &= (const Attributes &A) {
+ Attrs.Bits &= A.Raw();
+ return *this;
+}
+Attributes Attributes::operator ~ () const {
+ return Attributes(~Raw());
+}
+
+uint64_t Attributes::Raw() const {
+ return Attrs.Bits;
+}
+
+Attributes Attributes::typeIncompatible(Type *Ty) {
+ Attributes::Builder Incompatible;
+
+ if (!Ty->isIntegerTy())
+ // Attributes that only apply to integers.
+ Incompatible.addAttribute(Attributes::SExt)
+ .addAttribute(Attributes::ZExt);
+
+ if (!Ty->isPointerTy())
+ // Attributes that only apply to pointers.
+ Incompatible.addAttribute(Attributes::ByVal)
+ .addAttribute(Attributes::Nest)
+ .addAttribute(Attributes::NoAlias)
+ .addAttribute(Attributes::NoCapture)
+ .addAttribute(Attributes::StructRet);
+
+ return Attributes(Incompatible.Bits); // FIXME: Use Attributes::get().
+}
+
std::string Attributes::getAsString() const {
std::string Result;
- if (hasZExtAttr())
+ if (hasAttribute(Attributes::ZExt))
Result += "zeroext ";
- if (hasSExtAttr())
+ if (hasAttribute(Attributes::SExt))
Result += "signext ";
- if (hasNoReturnAttr())
+ if (hasAttribute(Attributes::NoReturn))
Result += "noreturn ";
- if (hasNoUnwindAttr())
+ if (hasAttribute(Attributes::NoUnwind))
Result += "nounwind ";
- if (hasUWTableAttr())
+ if (hasAttribute(Attributes::UWTable))
Result += "uwtable ";
- if (hasReturnsTwiceAttr())
+ if (hasAttribute(Attributes::ReturnsTwice))
Result += "returns_twice ";
- if (hasInRegAttr())
+ if (hasAttribute(Attributes::InReg))
Result += "inreg ";
- if (hasNoAliasAttr())
+ if (hasAttribute(Attributes::NoAlias))
Result += "noalias ";
- if (hasNoCaptureAttr())
+ if (hasAttribute(Attributes::NoCapture))
Result += "nocapture ";
- if (hasStructRetAttr())
+ if (hasAttribute(Attributes::StructRet))
Result += "sret ";
- if (hasByValAttr())
+ if (hasAttribute(Attributes::ByVal))
Result += "byval ";
- if (hasNestAttr())
+ if (hasAttribute(Attributes::Nest))
Result += "nest ";
- if (hasReadNoneAttr())
+ if (hasAttribute(Attributes::ReadNone))
Result += "readnone ";
- if (hasReadOnlyAttr())
+ if (hasAttribute(Attributes::ReadOnly))
Result += "readonly ";
- if (hasOptimizeForSizeAttr())
+ if (hasAttribute(Attributes::OptimizeForSize))
Result += "optsize ";
- if (hasNoInlineAttr())
+ if (hasAttribute(Attributes::NoInline))
Result += "noinline ";
- if (hasInlineHintAttr())
+ if (hasAttribute(Attributes::InlineHint))
Result += "inlinehint ";
- if (hasAlwaysInlineAttr())
+ if (hasAttribute(Attributes::AlwaysInline))
Result += "alwaysinline ";
- if (hasStackProtectAttr())
+ if (hasAttribute(Attributes::StackProtect))
Result += "ssp ";
- if (hasStackProtectReqAttr())
+ if (hasAttribute(Attributes::StackProtectReq))
Result += "sspreq ";
- if (hasNoRedZoneAttr())
+ if (hasAttribute(Attributes::NoRedZone))
Result += "noredzone ";
- if (hasNoImplicitFloatAttr())
+ if (hasAttribute(Attributes::NoImplicitFloat))
Result += "noimplicitfloat ";
- if (hasNakedAttr())
+ if (hasAttribute(Attributes::Naked))
Result += "naked ";
- if (hasNonLazyBindAttr())
+ if (hasAttribute(Attributes::NonLazyBind))
Result += "nonlazybind ";
- if (hasAddressSafetyAttr())
+ if (hasAttribute(Attributes::AddressSafety))
Result += "address_safety ";
- if (hasStackAlignmentAttr()) {
+ if (hasAttribute(Attributes::StackAlignment)) {
Result += "alignstack(";
Result += utostr(getStackAlignment());
Result += ") ";
}
- if (hasAlignmentAttr()) {
+ if (hasAttribute(Attributes::Alignment)) {
Result += "align ";
Result += utostr(getAlignment());
Result += " ";
@@ -96,49 +202,128 @@
return Result;
}
-Attributes Attributes::typeIncompatible(Type *Ty) {
- Attributes Incompatible = Attribute::None;
-
- if (!Ty->isIntegerTy())
- // Attributes that only apply to integers.
- Incompatible |= Attribute::SExt | Attribute::ZExt;
-
- if (!Ty->isPointerTy())
- // Attributes that only apply to pointers.
- Incompatible |= Attribute::ByVal | Attribute::Nest | Attribute::NoAlias |
- Attribute::StructRet | Attribute::NoCapture;
-
- return Incompatible;
-}
-
//===----------------------------------------------------------------------===//
-// AttributeImpl Definition
+// Attributes::Builder Implementation
//===----------------------------------------------------------------------===//
-Attributes::Attributes(AttributesImpl *A) : Bits(0) {}
+Attributes::Builder &Attributes::Builder::
+addAttribute(Attributes::AttrVal Val) {
+ Bits |= AttributesImpl::getAttrMask(Val);
+ return *this;
+}
-Attributes Attributes::get(LLVMContext &Context, Attributes::Builder &B) {
- // If there are no attributes, return an empty Attributes class.
- if (B.Bits == 0)
- return Attributes();
+void Attributes::Builder::addAlignmentAttr(unsigned Align) {
+ if (Align == 0) return;
+ assert(isPowerOf2_32(Align) && "Alignment must be a power of two.");
+ assert(Align <= 0x40000000 && "Alignment too large.");
+ Bits |= (Log2_32(Align) + 1) << 16;
+}
+void Attributes::Builder::addStackAlignmentAttr(unsigned Align) {
+ // Default alignment, allow the target to define how to align it.
+ if (Align == 0) return;
+ assert(isPowerOf2_32(Align) && "Alignment must be a power of two.");
+ assert(Align <= 0x100 && "Alignment too large.");
+ Bits |= (Log2_32(Align) + 1) << 26;
+}
+
+Attributes::Builder &Attributes::Builder::
+removeAttribute(Attributes::AttrVal Val) {
+ Bits &= ~AttributesImpl::getAttrMask(Val);
+ return *this;
+}
- // Otherwise, build a key to look up the existing attributes.
- LLVMContextImpl *pImpl = Context.pImpl;
- FoldingSetNodeID ID;
- ID.AddInteger(B.Bits);
+void Attributes::Builder::removeAttributes(const Attributes &A) {
+ Bits &= ~A.Raw();
+}
- void *InsertPoint;
- AttributesImpl *PA = pImpl->AttrsSet.FindNodeOrInsertPos(ID, InsertPoint);
+bool Attributes::Builder::hasAttribute(Attributes::AttrVal A) const {
+ return Bits & AttributesImpl::getAttrMask(A);
+}
- if (!PA) {
- // If we didn't find any existing attributes of the same shape then create a
- // new one and insert it.
- PA = new AttributesImpl(B.Bits);
- pImpl->AttrsSet.InsertNode(PA, InsertPoint);
- }
+bool Attributes::Builder::hasAttributes() const {
+ return Bits != 0;
+}
+bool Attributes::Builder::hasAttributes(const Attributes &A) const {
+ return Bits & A.Raw();
+}
+bool Attributes::Builder::hasAlignmentAttr() const {
+ return Bits & AttributesImpl::getAttrMask(Attributes::Alignment);
+}
- // Return the AttributesList that we found or created.
- return Attributes(PA);
+uint64_t Attributes::Builder::getAlignment() const {
+ if (!hasAlignmentAttr())
+ return 0;
+ return 1U <<
+ (((Bits & AttributesImpl::getAttrMask(Attributes::Alignment)) >> 16) - 1);
+}
+
+uint64_t Attributes::Builder::getStackAlignment() const {
+ if (!hasAlignmentAttr())
+ return 0;
+ return 1U <<
+ (((Bits & AttributesImpl::getAttrMask(Attributes::StackAlignment))>>26)-1);
+}
+
+//===----------------------------------------------------------------------===//
+// AttributeImpl Definition
+//===----------------------------------------------------------------------===//
+
+uint64_t AttributesImpl::getAttrMask(uint64_t Val) {
+ switch (Val) {
+ case Attributes::None: return 0;
+ case Attributes::ZExt: return 1 << 0;
+ case Attributes::SExt: return 1 << 1;
+ case Attributes::NoReturn: return 1 << 2;
+ case Attributes::InReg: return 1 << 3;
+ case Attributes::StructRet: return 1 << 4;
+ case Attributes::NoUnwind: return 1 << 5;
+ case Attributes::NoAlias: return 1 << 6;
+ case Attributes::ByVal: return 1 << 7;
+ case Attributes::Nest: return 1 << 8;
+ case Attributes::ReadNone: return 1 << 9;
+ case Attributes::ReadOnly: return 1 << 10;
+ case Attributes::NoInline: return 1 << 11;
+ case Attributes::AlwaysInline: return 1 << 12;
+ case Attributes::OptimizeForSize: return 1 << 13;
+ case Attributes::StackProtect: return 1 << 14;
+ case Attributes::StackProtectReq: return 1 << 15;
+ case Attributes::Alignment: return 31 << 16;
+ case Attributes::NoCapture: return 1 << 21;
+ case Attributes::NoRedZone: return 1 << 22;
+ case Attributes::NoImplicitFloat: return 1 << 23;
+ case Attributes::Naked: return 1 << 24;
+ case Attributes::InlineHint: return 1 << 25;
+ case Attributes::StackAlignment: return 7 << 26;
+ case Attributes::ReturnsTwice: return 1 << 29;
+ case Attributes::UWTable: return 1 << 30;
+ case Attributes::NonLazyBind: return 1U << 31;
+ case Attributes::AddressSafety: return 1ULL << 32;
+ }
+ llvm_unreachable("Unsupported attribute type");
+}
+
+bool AttributesImpl::hasAttribute(uint64_t A) const {
+ return (Bits & getAttrMask(A)) != 0;
+}
+
+bool AttributesImpl::hasAttributes() const {
+ return Bits != 0;
+}
+
+bool AttributesImpl::hasAttributes(const Attributes &A) const {
+ return Bits & A.Raw(); // FIXME: Raw() won't work here in the future.
+}
+
+uint64_t AttributesImpl::getAlignment() const {
+ return Bits & getAttrMask(Attributes::Alignment);
+}
+
+uint64_t AttributesImpl::getStackAlignment() const {
+ return Bits & getAttrMask(Attributes::StackAlignment);
+}
+
+bool AttributesImpl::isEmptyOrSingleton() const {
+ return (Bits & (Bits - 1)) == 0;
}
//===----------------------------------------------------------------------===//
@@ -292,16 +477,25 @@
/// hasAttrSomewhere - Return true if the specified attribute is set for at
/// least one parameter or for the return value.
-bool AttrListPtr::hasAttrSomewhere(Attributes Attr) const {
+bool AttrListPtr::hasAttrSomewhere(Attributes::AttrVal Attr) const {
if (AttrList == 0) return false;
-
+
const SmallVector<AttributeWithIndex, 4> &Attrs = AttrList->Attrs;
for (unsigned i = 0, e = Attrs.size(); i != e; ++i)
- if (Attrs[i].Attrs.hasAttributes(Attr))
+ if (Attrs[i].Attrs.hasAttribute(Attr))
return true;
return false;
}
+unsigned AttrListPtr::getNumAttrs() const {
+ return AttrList ? AttrList->Attrs.size() : 0;
+}
+
+Attributes &AttrListPtr::getAttributesAtIndex(unsigned i) const {
+ assert(AttrList && "Trying to get an attribute from an empty list!");
+ assert(i < AttrList->Attrs.size() && "Index out of range!");
+ return AttrList->Attrs[i].Attrs;
+}
AttrListPtr AttrListPtr::addAttr(unsigned Idx, Attributes Attrs) const {
Attributes OldAttrs = getAttributes(Idx);
@@ -348,7 +542,8 @@
#ifndef NDEBUG
// FIXME it is not obvious how this should work for alignment.
// For now, say we can't pass in alignment, which no current use does.
- assert(!Attrs.hasAlignmentAttr() && "Attempt to exclude alignment!");
+ assert(!Attrs.hasAttribute(Attributes::Alignment) &&
+ "Attempt to exclude alignment!");
#endif
if (AttrList == 0) return AttrListPtr();
Removed: llvm/branches/R600/lib/VMCore/AttributesImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/VMCore/AttributesImpl.h?rev=165747&view=auto
==============================================================================
--- llvm/branches/R600/lib/VMCore/AttributesImpl.h (original)
+++ llvm/branches/R600/lib/VMCore/AttributesImpl.h (removed)
@@ -1,40 +0,0 @@
-//===-- AttributesImpl.h - Attributes Internals -----------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines various helper methods and classes used by LLVMContextImpl
-// for creating and managing attributes.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_ATTRIBUTESIMPL_H
-#define LLVM_ATTRIBUTESIMPL_H
-
-#include "llvm/ADT/FoldingSet.h"
-
-namespace llvm {
-
-class AttributesImpl : public FoldingSetNode {
- uint64_t Bits; // FIXME: We will be expanding this.
-
- void operator=(const AttributesImpl &) LLVM_DELETED_FUNCTION;
- AttributesImpl(const AttributesImpl &) LLVM_DELETED_FUNCTION;
-public:
- AttributesImpl(uint64_t bits) : Bits(bits) {}
-
- void Profile(FoldingSetNodeID &ID) const {
- Profile(ID, Bits);
- }
- static void Profile(FoldingSetNodeID &ID, uint64_t Bits) {
- ID.AddInteger(Bits);
- }
-};
-
-} // end llvm namespace
-
-#endif
Modified: llvm/branches/R600/lib/VMCore/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/VMCore/CMakeLists.txt?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/VMCore/CMakeLists.txt (original)
+++ llvm/branches/R600/lib/VMCore/CMakeLists.txt Thu Oct 11 16:28:00 2012
@@ -8,6 +8,7 @@
ConstantFold.cpp
Constants.cpp
Core.cpp
+ DataLayout.cpp
DebugInfo.cpp
DebugLoc.cpp
DIBuilder.cpp
Modified: llvm/branches/R600/lib/VMCore/ConstantFold.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/VMCore/ConstantFold.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/VMCore/ConstantFold.cpp (original)
+++ llvm/branches/R600/lib/VMCore/ConstantFold.cpp Thu Oct 11 16:28:00 2012
@@ -12,7 +12,7 @@
// ConstantExpr::get* methods to automatically fold constants when possible.
//
// The current constant folding implementation is implemented in two pieces: the
-// pieces that don't need TargetData, and the pieces that do. This is to avoid
+// pieces that don't need DataLayout, and the pieces that do. This is to avoid
// a dependence in VMCore on Target.
//
//===----------------------------------------------------------------------===//
Modified: llvm/branches/R600/lib/VMCore/DIBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/VMCore/DIBuilder.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/VMCore/DIBuilder.cpp (original)
+++ llvm/branches/R600/lib/VMCore/DIBuilder.cpp Thu Oct 11 16:28:00 2012
@@ -550,7 +550,7 @@
uint64_t SizeInBits,
uint64_t AlignInBits,
DIArray Elements,
- DIType ClassType, unsigned Flags) {
+ DIType ClassType) {
// TAG_enumeration_type is encoded in DICompositeType format.
Value *Elts[] = {
GetTagConstant(VMContext, dwarf::DW_TAG_enumeration_type),
@@ -561,7 +561,7 @@
ConstantInt::get(Type::getInt64Ty(VMContext), SizeInBits),
ConstantInt::get(Type::getInt64Ty(VMContext), AlignInBits),
ConstantInt::get(Type::getInt32Ty(VMContext), 0),
- ConstantInt::get(Type::getInt32Ty(VMContext), Flags),
+ ConstantInt::get(Type::getInt32Ty(VMContext), 0),
ClassType,
Elements,
ConstantInt::get(Type::getInt32Ty(VMContext), 0),
@@ -706,7 +706,9 @@
/// can be RAUW'd if the full type is seen.
DIType DIBuilder::createForwardDecl(unsigned Tag, StringRef Name,
DIDescriptor Scope, DIFile F,
- unsigned Line, unsigned RuntimeLang) {
+ unsigned Line, unsigned RuntimeLang,
+ uint64_t SizeInBits,
+ uint64_t AlignInBits) {
// Create a temporary MDNode.
Value *Elts[] = {
GetTagConstant(VMContext, Tag),
@@ -714,9 +716,8 @@
MDString::get(VMContext, Name),
F,
ConstantInt::get(Type::getInt32Ty(VMContext), Line),
- // To ease transition include sizes etc of 0.
- ConstantInt::get(Type::getInt32Ty(VMContext), 0),
- ConstantInt::get(Type::getInt32Ty(VMContext), 0),
+ ConstantInt::get(Type::getInt64Ty(VMContext), SizeInBits),
+ ConstantInt::get(Type::getInt64Ty(VMContext), AlignInBits),
ConstantInt::get(Type::getInt32Ty(VMContext), 0),
ConstantInt::get(Type::getInt32Ty(VMContext),
DIDescriptor::FlagFwdDecl),
Copied: llvm/branches/R600/lib/VMCore/DataLayout.cpp (from r165622, llvm/branches/R600/lib/Target/TargetData.cpp)
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/VMCore/DataLayout.cpp?p2=llvm/branches/R600/lib/VMCore/DataLayout.cpp&p1=llvm/branches/R600/lib/Target/TargetData.cpp&r1=165622&r2=165748&rev=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/TargetData.cpp (original)
+++ llvm/branches/R600/lib/VMCore/DataLayout.cpp Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-//===-- TargetData.cpp - Data size & alignment routines --------------------==//
+//===-- DataLayout.cpp - Data size & alignment routines --------------------==//
//
// The LLVM Compiler Infrastructure
//
@@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
-// This file defines target properties related to datatype size/offset/alignment
+// This file defines layout properties related to datatype size/offset/alignment
// information.
//
// This structure should be created once, filled in if the defaults are not
@@ -16,7 +16,7 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Module.h"
@@ -31,17 +31,17 @@
#include <cstdlib>
using namespace llvm;
-// Handle the Pass registration stuff necessary to use TargetData's.
+// Handle the Pass registration stuff necessary to use DataLayout's.
// Register the default SparcV9 implementation...
-INITIALIZE_PASS(TargetData, "targetdata", "Target Data Layout", false, true)
-char TargetData::ID = 0;
+INITIALIZE_PASS(DataLayout, "datalayout", "Data Layout", false, true)
+char DataLayout::ID = 0;
//===----------------------------------------------------------------------===//
// Support for StructLayout
//===----------------------------------------------------------------------===//
-StructLayout::StructLayout(StructType *ST, const TargetData &TD) {
+StructLayout::StructLayout(StructType *ST, const DataLayout &TD) {
assert(!ST->isOpaque() && "Cannot get layout of opaque structs");
StructAlignment = 0;
StructSize = 0;
@@ -54,7 +54,7 @@
// Add padding if necessary to align the data element properly.
if ((StructSize & (TyAlign-1)) != 0)
- StructSize = TargetData::RoundUpAlignment(StructSize, TyAlign);
+ StructSize = DataLayout::RoundUpAlignment(StructSize, TyAlign);
// Keep track of maximum alignment constraint.
StructAlignment = std::max(TyAlign, StructAlignment);
@@ -69,7 +69,7 @@
// Add padding to the end of the struct so that it could be put in an array
// and all array elements would be aligned correctly.
if ((StructSize & (StructAlignment-1)) != 0)
- StructSize = TargetData::RoundUpAlignment(StructSize, StructAlignment);
+ StructSize = DataLayout::RoundUpAlignment(StructSize, StructAlignment);
}
@@ -94,14 +94,14 @@
}
//===----------------------------------------------------------------------===//
-// TargetAlignElem, TargetAlign support
+// LayoutAlignElem, LayoutAlign support
//===----------------------------------------------------------------------===//
-TargetAlignElem
-TargetAlignElem::get(AlignTypeEnum align_type, unsigned abi_align,
+LayoutAlignElem
+LayoutAlignElem::get(AlignTypeEnum align_type, unsigned abi_align,
unsigned pref_align, uint32_t bit_width) {
assert(abi_align <= pref_align && "Preferred alignment worse than ABI!");
- TargetAlignElem retval;
+ LayoutAlignElem retval;
retval.AlignType = align_type;
retval.ABIAlign = abi_align;
retval.PrefAlign = pref_align;
@@ -110,18 +110,46 @@
}
bool
-TargetAlignElem::operator==(const TargetAlignElem &rhs) const {
+LayoutAlignElem::operator==(const LayoutAlignElem &rhs) const {
return (AlignType == rhs.AlignType
&& ABIAlign == rhs.ABIAlign
&& PrefAlign == rhs.PrefAlign
&& TypeBitWidth == rhs.TypeBitWidth);
}
-const TargetAlignElem
-TargetData::InvalidAlignmentElem = { (AlignTypeEnum)0xFF, 0, 0, 0 };
+const LayoutAlignElem
+DataLayout::InvalidAlignmentElem =
+ LayoutAlignElem::get((AlignTypeEnum) -1, 0, 0, 0);
//===----------------------------------------------------------------------===//
-// TargetData Class Implementation
+// PointerAlignElem, PointerAlign support
+//===----------------------------------------------------------------------===//
+
+PointerAlignElem
+PointerAlignElem::get(uint32_t addr_space, unsigned abi_align,
+ unsigned pref_align, uint32_t bit_width) {
+ assert(abi_align <= pref_align && "Preferred alignment worse than ABI!");
+ PointerAlignElem retval;
+ retval.AddressSpace = addr_space;
+ retval.ABIAlign = abi_align;
+ retval.PrefAlign = pref_align;
+ retval.TypeBitWidth = bit_width;
+ return retval;
+}
+
+bool
+PointerAlignElem::operator==(const PointerAlignElem &rhs) const {
+ return (ABIAlign == rhs.ABIAlign
+ && AddressSpace == rhs.AddressSpace
+ && PrefAlign == rhs.PrefAlign
+ && TypeBitWidth == rhs.TypeBitWidth);
+}
+
+const PointerAlignElem
+DataLayout::InvalidPointerElem = PointerAlignElem::get(~0U, 0U, 0U, 0U);
+
+//===----------------------------------------------------------------------===//
+// DataLayout Class Implementation
//===----------------------------------------------------------------------===//
/// getInt - Get an integer ignoring errors.
@@ -131,14 +159,11 @@
return Result;
}
-void TargetData::init() {
- initializeTargetDataPass(*PassRegistry::getPassRegistry());
+void DataLayout::init() {
+ initializeDataLayoutPass(*PassRegistry::getPassRegistry());
LayoutMap = 0;
LittleEndian = false;
- PointerMemSize = 8;
- PointerABIAlign = 8;
- PointerPrefAlign = PointerABIAlign;
StackNaturalAlign = 0;
// Default alignments
@@ -154,9 +179,10 @@
setAlignment(VECTOR_ALIGN, 8, 8, 64); // v2i32, v1i64, ...
setAlignment(VECTOR_ALIGN, 16, 16, 128); // v16i8, v8i16, v4i32, ...
setAlignment(AGGREGATE_ALIGN, 0, 8, 0); // struct
+ setPointerAlignment(0, 8, 8, 8);
}
-std::string TargetData::parseSpecifier(StringRef Desc, TargetData *td) {
+std::string DataLayout::parseSpecifier(StringRef Desc, DataLayout *td) {
if (td)
td->init();
@@ -185,13 +211,16 @@
td->LittleEndian = true;
break;
case 'p': {
- // Pointer size.
+ int AddrSpace = 0;
+ if (Specifier.size() > 1) {
+ AddrSpace = getInt(Specifier.substr(1));
+ if (AddrSpace < 0 || AddrSpace > (1 << 24))
+ return "Invalid address space, must be a positive 24bit integer";
+ }
Split = Token.split(':');
int PointerMemSizeBits = getInt(Split.first);
if (PointerMemSizeBits < 0 || PointerMemSizeBits % 8 != 0)
return "invalid pointer size, must be a positive 8-bit multiple";
- if (td)
- td->PointerMemSize = PointerMemSizeBits / 8;
// Pointer ABI alignment.
Split = Split.second.split(':');
@@ -200,8 +229,6 @@
return "invalid pointer ABI alignment, "
"must be a positive 8-bit multiple";
}
- if (td)
- td->PointerABIAlign = PointerABIAlignBits / 8;
// Pointer preferred alignment.
Split = Split.second.split(':');
@@ -210,11 +237,12 @@
return "invalid pointer preferred alignment, "
"must be a positive 8-bit multiple";
}
- if (td) {
- td->PointerPrefAlign = PointerPrefAlignBits / 8;
- if (td->PointerPrefAlign == 0)
- td->PointerPrefAlign = td->PointerABIAlign;
- }
+
+ if (PointerPrefAlignBits == 0)
+ PointerPrefAlignBits = PointerABIAlignBits;
+ if (td)
+ td->setPointerAlignment(AddrSpace, PointerABIAlignBits/8,
+ PointerPrefAlignBits/8, PointerMemSizeBits/8);
break;
}
case 'i':
@@ -256,7 +284,7 @@
unsigned PrefAlign = PrefAlignBits / 8;
if (PrefAlign == 0)
PrefAlign = ABIAlign;
-
+
if (td)
td->setAlignment(AlignType, ABIAlign, PrefAlign, Size);
break;
@@ -266,8 +294,8 @@
do {
int Width = getInt(Specifier);
if (Width <= 0) {
- return std::string("invalid native integer size \'") + Specifier.str() +
- "\', must be a positive integer.";
+ return std::string("invalid native integer size \'") +
+ Specifier.str() + "\', must be a positive integer.";
}
if (td && Width != 0)
td->LegalIntWidths.push_back(Width);
@@ -298,26 +326,26 @@
///
/// @note This has to exist, because this is a pass, but it should never be
/// used.
-TargetData::TargetData() : ImmutablePass(ID) {
- report_fatal_error("Bad TargetData ctor used. "
- "Tool did not specify a TargetData to use?");
+DataLayout::DataLayout() : ImmutablePass(ID) {
+ report_fatal_error("Bad DataLayout ctor used. "
+ "Tool did not specify a DataLayout to use?");
}
-TargetData::TargetData(const Module *M)
+DataLayout::DataLayout(const Module *M)
: ImmutablePass(ID) {
std::string errMsg = parseSpecifier(M->getDataLayout(), this);
- assert(errMsg == "" && "Module M has malformed target data layout string.");
+ assert(errMsg == "" && "Module M has malformed data layout string.");
(void)errMsg;
}
void
-TargetData::setAlignment(AlignTypeEnum align_type, unsigned abi_align,
+DataLayout::setAlignment(AlignTypeEnum align_type, unsigned abi_align,
unsigned pref_align, uint32_t bit_width) {
assert(abi_align <= pref_align && "Preferred alignment worse than ABI!");
assert(pref_align < (1 << 16) && "Alignment doesn't fit in bitfield");
assert(bit_width < (1 << 24) && "Bit width doesn't fit in bitfield");
for (unsigned i = 0, e = Alignments.size(); i != e; ++i) {
- if (Alignments[i].AlignType == align_type &&
+ if (Alignments[i].AlignType == (unsigned)align_type &&
Alignments[i].TypeBitWidth == bit_width) {
// Update the abi, preferred alignments.
Alignments[i].ABIAlign = abi_align;
@@ -326,20 +354,35 @@
}
}
- Alignments.push_back(TargetAlignElem::get(align_type, abi_align,
+ Alignments.push_back(LayoutAlignElem::get(align_type, abi_align,
pref_align, bit_width));
}
+void
+DataLayout::setPointerAlignment(uint32_t addr_space, unsigned abi_align,
+ unsigned pref_align, uint32_t bit_width) {
+ assert(abi_align <= pref_align && "Preferred alignment worse than ABI!");
+ DenseMap<unsigned,PointerAlignElem>::iterator val = Pointers.find(addr_space);
+ if (val == Pointers.end()) {
+ Pointers[addr_space] = PointerAlignElem::get(addr_space,
+ abi_align, pref_align, bit_width);
+ } else {
+ val->second.ABIAlign = abi_align;
+ val->second.PrefAlign = pref_align;
+ val->second.TypeBitWidth = bit_width;
+ }
+}
+
/// getAlignmentInfo - Return the alignment (either ABI if ABIInfo = true or
-/// preferred if ABIInfo = false) the target wants for the specified datatype.
-unsigned TargetData::getAlignmentInfo(AlignTypeEnum AlignType,
+/// preferred if ABIInfo = false) the layout wants for the specified datatype.
+unsigned DataLayout::getAlignmentInfo(AlignTypeEnum AlignType,
uint32_t BitWidth, bool ABIInfo,
Type *Ty) const {
// Check to see if we have an exact match and remember the best match we see.
int BestMatchIdx = -1;
int LargestInt = -1;
for (unsigned i = 0, e = Alignments.size(); i != e; ++i) {
- if (Alignments[i].AlignType == AlignType &&
+ if (Alignments[i].AlignType == (unsigned)AlignType &&
Alignments[i].TypeBitWidth == BitWidth)
return ABIInfo ? Alignments[i].ABIAlign : Alignments[i].PrefAlign;
@@ -412,11 +455,11 @@
} // end anonymous namespace
-TargetData::~TargetData() {
+DataLayout::~DataLayout() {
delete static_cast<StructLayoutMap*>(LayoutMap);
}
-const StructLayout *TargetData::getStructLayout(StructType *Ty) const {
+const StructLayout *DataLayout::getStructLayout(StructType *Ty) const {
if (!LayoutMap)
LayoutMap = new StructLayoutMap();
@@ -439,17 +482,35 @@
return L;
}
-std::string TargetData::getStringRepresentation() const {
+std::string DataLayout::getStringRepresentation() const {
std::string Result;
raw_string_ostream OS(Result);
- OS << (LittleEndian ? "e" : "E")
- << "-p:" << PointerMemSize*8 << ':' << PointerABIAlign*8
- << ':' << PointerPrefAlign*8
- << "-S" << StackNaturalAlign*8;
+ OS << (LittleEndian ? "e" : "E");
+ SmallVector<unsigned, 8> addrSpaces;
+ // Lets get all of the known address spaces and sort them
+ // into increasing order so that we can emit the string
+ // in a cleaner format.
+ for (DenseMap<unsigned, PointerAlignElem>::const_iterator
+ pib = Pointers.begin(), pie = Pointers.end();
+ pib != pie; ++pib) {
+ addrSpaces.push_back(pib->first);
+ }
+ std::sort(addrSpaces.begin(), addrSpaces.end());
+ for (SmallVector<unsigned, 8>::iterator asb = addrSpaces.begin(),
+ ase = addrSpaces.end(); asb != ase; ++asb) {
+ const PointerAlignElem &PI = Pointers.find(*asb)->second;
+ OS << "-p";
+ if (PI.AddressSpace) {
+ OS << PI.AddressSpace;
+ }
+ OS << ":" << PI.TypeBitWidth*8 << ':' << PI.ABIAlign*8
+ << ':' << PI.PrefAlign*8;
+ }
+ OS << "-S" << StackNaturalAlign*8;
for (unsigned i = 0, e = Alignments.size(); i != e; ++i) {
- const TargetAlignElem &AI = Alignments[i];
+ const LayoutAlignElem &AI = Alignments[i];
OS << '-' << (char)AI.AlignType << AI.TypeBitWidth << ':'
<< AI.ABIAlign*8 << ':' << AI.PrefAlign*8;
}
@@ -464,12 +525,15 @@
}
-uint64_t TargetData::getTypeSizeInBits(Type *Ty) const {
+uint64_t DataLayout::getTypeSizeInBits(Type *Ty) const {
assert(Ty->isSized() && "Cannot getTypeInfo() on a type that is unsized!");
switch (Ty->getTypeID()) {
case Type::LabelTyID:
- case Type::PointerTyID:
- return getPointerSizeInBits();
+ return getPointerSizeInBits(0);
+ case Type::PointerTyID: {
+ unsigned AS = dyn_cast<PointerType>(Ty)->getAddressSpace();
+ return getPointerSizeInBits(AS);
+ }
case Type::ArrayTyID: {
ArrayType *ATy = cast<ArrayType>(Ty);
return getTypeAllocSizeInBits(ATy->getElementType())*ATy->getNumElements();
@@ -498,7 +562,7 @@
case Type::VectorTyID:
return cast<VectorType>(Ty)->getBitWidth();
default:
- llvm_unreachable("TargetData::getTypeSizeInBits(): Unsupported type");
+ llvm_unreachable("DataLayout::getTypeSizeInBits(): Unsupported type");
}
}
@@ -510,17 +574,22 @@
Get the ABI (\a abi_or_pref == true) or preferred alignment (\a abi_or_pref
== false) for the requested type \a Ty.
*/
-unsigned TargetData::getAlignment(Type *Ty, bool abi_or_pref) const {
+unsigned DataLayout::getAlignment(Type *Ty, bool abi_or_pref) const {
int AlignType = -1;
assert(Ty->isSized() && "Cannot getTypeInfo() on a type that is unsized!");
switch (Ty->getTypeID()) {
// Early escape for the non-numeric types.
case Type::LabelTyID:
- case Type::PointerTyID:
return (abi_or_pref
- ? getPointerABIAlignment()
- : getPointerPrefAlignment());
+ ? getPointerABIAlignment(0)
+ : getPointerPrefAlignment(0));
+ case Type::PointerTyID: {
+ unsigned AS = dyn_cast<PointerType>(Ty)->getAddressSpace();
+ return (abi_or_pref
+ ? getPointerABIAlignment(AS)
+ : getPointerPrefAlignment(AS));
+ }
case Type::ArrayTyID:
return getAlignment(cast<ArrayType>(Ty)->getElementType(), abi_or_pref);
@@ -560,18 +629,18 @@
abi_or_pref, Ty);
}
-unsigned TargetData::getABITypeAlignment(Type *Ty) const {
+unsigned DataLayout::getABITypeAlignment(Type *Ty) const {
return getAlignment(Ty, true);
}
/// getABIIntegerTypeAlignment - Return the minimum ABI-required alignment for
/// an integer type of the specified bitwidth.
-unsigned TargetData::getABIIntegerTypeAlignment(unsigned BitWidth) const {
+unsigned DataLayout::getABIIntegerTypeAlignment(unsigned BitWidth) const {
return getAlignmentInfo(INTEGER_ALIGN, BitWidth, true, 0);
}
-unsigned TargetData::getCallFrameTypeAlignment(Type *Ty) const {
+unsigned DataLayout::getCallFrameTypeAlignment(Type *Ty) const {
for (unsigned i = 0, e = Alignments.size(); i != e; ++i)
if (Alignments[i].AlignType == STACK_ALIGN)
return Alignments[i].ABIAlign;
@@ -579,11 +648,11 @@
return getABITypeAlignment(Ty);
}
-unsigned TargetData::getPrefTypeAlignment(Type *Ty) const {
+unsigned DataLayout::getPrefTypeAlignment(Type *Ty) const {
return getAlignment(Ty, false);
}
-unsigned TargetData::getPreferredTypeAlignmentShift(Type *Ty) const {
+unsigned DataLayout::getPreferredTypeAlignmentShift(Type *Ty) const {
unsigned Align = getPrefTypeAlignment(Ty);
assert(!(Align & (Align-1)) && "Alignment is not a power of two!");
return Log2_32(Align);
@@ -591,12 +660,13 @@
/// getIntPtrType - Return an unsigned integer type that is the same size or
/// greater to the host pointer size.
-IntegerType *TargetData::getIntPtrType(LLVMContext &C) const {
- return IntegerType::get(C, getPointerSizeInBits());
+IntegerType *DataLayout::getIntPtrType(LLVMContext &C,
+ unsigned AddressSpace) const {
+ return IntegerType::get(C, getPointerSizeInBits(AddressSpace));
}
-uint64_t TargetData::getIndexedOffset(Type *ptrTy,
+uint64_t DataLayout::getIndexedOffset(Type *ptrTy,
ArrayRef<Value *> Indices) const {
Type *Ty = ptrTy;
assert(Ty->isPointerTy() && "Illegal argument for getIndexedOffset()");
@@ -636,7 +706,7 @@
/// getPreferredAlignment - Return the preferred alignment of the specified
/// global. This includes an explicitly requested alignment (if the global
/// has one).
-unsigned TargetData::getPreferredAlignment(const GlobalVariable *GV) const {
+unsigned DataLayout::getPreferredAlignment(const GlobalVariable *GV) const {
Type *ElemType = GV->getType()->getElementType();
unsigned Alignment = getPrefTypeAlignment(ElemType);
unsigned GVAlignment = GV->getAlignment();
@@ -660,6 +730,6 @@
/// getPreferredAlignmentLog - Return the preferred alignment of the
/// specified global, returned in log form. This includes an explicitly
/// requested alignment (if the global has one).
-unsigned TargetData::getPreferredAlignmentLog(const GlobalVariable *GV) const {
+unsigned DataLayout::getPreferredAlignmentLog(const GlobalVariable *GV) const {
return Log2_32(getPreferredAlignment(GV));
}
Modified: llvm/branches/R600/lib/VMCore/DebugInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/VMCore/DebugInfo.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/VMCore/DebugInfo.cpp (original)
+++ llvm/branches/R600/lib/VMCore/DebugInfo.cpp Thu Oct 11 16:28:00 2012
@@ -111,6 +111,16 @@
return 0;
}
+void DIDescriptor::replaceFunctionField(unsigned Elt, Function *F) {
+ if (DbgNode == 0)
+ return;
+
+ if (Elt < DbgNode->getNumOperands()) {
+ MDNode *Node = const_cast<MDNode*>(DbgNode);
+ Node->replaceOperandWith(Elt, F);
+ }
+}
+
unsigned DIVariable::getNumAddrElements() const {
if (getVersion() <= LLVMDebugVersion8)
return DbgNode->getNumOperands()-6;
Modified: llvm/branches/R600/lib/VMCore/Function.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/VMCore/Function.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/VMCore/Function.cpp (original)
+++ llvm/branches/R600/lib/VMCore/Function.cpp Thu Oct 11 16:28:00 2012
@@ -78,7 +78,8 @@
/// in its containing function.
bool Argument::hasByValAttr() const {
if (!getType()->isPointerTy()) return false;
- return getParent()->getParamAttributes(getArgNo()+1).hasByValAttr();
+ return getParent()->getParamAttributes(getArgNo()+1).
+ hasAttribute(Attributes::ByVal);
}
unsigned Argument::getParamAlignment() const {
@@ -91,21 +92,24 @@
/// it in its containing function.
bool Argument::hasNestAttr() const {
if (!getType()->isPointerTy()) return false;
- return getParent()->getParamAttributes(getArgNo()+1).hasNestAttr();
+ return getParent()->getParamAttributes(getArgNo()+1).
+ hasAttribute(Attributes::Nest);
}
/// hasNoAliasAttr - Return true if this argument has the noalias attribute on
/// it in its containing function.
bool Argument::hasNoAliasAttr() const {
if (!getType()->isPointerTy()) return false;
- return getParent()->getParamAttributes(getArgNo()+1).hasNoAliasAttr();
+ return getParent()->getParamAttributes(getArgNo()+1).
+ hasAttribute(Attributes::NoAlias);
}
/// hasNoCaptureAttr - Return true if this argument has the nocapture attribute
/// on it in its containing function.
bool Argument::hasNoCaptureAttr() const {
if (!getType()->isPointerTy()) return false;
- return getParent()->getParamAttributes(getArgNo()+1).hasNoCaptureAttr();
+ return getParent()->getParamAttributes(getArgNo()+1).
+ hasAttribute(Attributes::NoCapture);
}
/// hasSRetAttr - Return true if this argument has the sret attribute on
@@ -114,7 +118,8 @@
if (!getType()->isPointerTy()) return false;
if (this != getParent()->arg_begin())
return false; // StructRet param must be first param
- return getParent()->getParamAttributes(1).hasStructRetAttr();
+ return getParent()->getParamAttributes(1).
+ hasAttribute(Attributes::StructRet);
}
/// addAttr - Add a Attribute to an argument
Modified: llvm/branches/R600/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/VMCore/Instructions.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/VMCore/Instructions.cpp (original)
+++ llvm/branches/R600/lib/VMCore/Instructions.cpp Thu Oct 11 16:28:00 2012
@@ -342,11 +342,19 @@
setAttributes(PAL);
}
-bool CallInst::paramHasAttr(unsigned i, Attributes attr) const {
- if (AttributeList.paramHasAttr(i, attr))
+bool CallInst::hasFnAttr(Attributes::AttrVal A) const {
+ if (AttributeList.getParamAttributes(~0U).hasAttribute(A))
return true;
if (const Function *F = getCalledFunction())
- return F->paramHasAttr(i, attr);
+ return F->getParamAttributes(~0U).hasAttribute(A);
+ return false;
+}
+
+bool CallInst::paramHasAttr(unsigned i, Attributes::AttrVal A) const {
+ if (AttributeList.getParamAttributes(i).hasAttribute(A))
+ return true;
+ if (const Function *F = getCalledFunction())
+ return F->getParamAttributes(i).hasAttribute(A);
return false;
}
@@ -562,11 +570,19 @@
return setSuccessor(idx, B);
}
-bool InvokeInst::paramHasAttr(unsigned i, Attributes attr) const {
- if (AttributeList.paramHasAttr(i, attr))
+bool InvokeInst::hasFnAttr(Attributes::AttrVal A) const {
+ if (AttributeList.getParamAttributes(~0U).hasAttribute(A))
+ return true;
+ if (const Function *F = getCalledFunction())
+ return F->getParamAttributes(~0U).hasAttribute(A);
+ return false;
+}
+
+bool InvokeInst::paramHasAttr(unsigned i, Attributes::AttrVal A) const {
+ if (AttributeList.getParamAttributes(i).hasAttribute(A))
return true;
if (const Function *F = getCalledFunction())
- return F->paramHasAttr(i, attr);
+ return F->getParamAttributes(i).hasAttribute(A);
return false;
}
Modified: llvm/branches/R600/lib/VMCore/LLVMContextImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/VMCore/LLVMContextImpl.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/VMCore/LLVMContextImpl.h (original)
+++ llvm/branches/R600/lib/VMCore/LLVMContextImpl.h Thu Oct 11 16:28:00 2012
@@ -16,9 +16,9 @@
#define LLVM_LLVMCONTEXT_IMPL_H
#include "llvm/LLVMContext.h"
-#include "AttributesImpl.h"
#include "ConstantsContext.h"
#include "LeaksContext.h"
+#include "llvm/AttributesImpl.h"
#include "llvm/Constants.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Metadata.h"
Modified: llvm/branches/R600/lib/VMCore/Value.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/VMCore/Value.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/VMCore/Value.cpp (original)
+++ llvm/branches/R600/lib/VMCore/Value.cpp Thu Oct 11 16:28:00 2012
@@ -394,7 +394,7 @@
// It's also not always safe to follow a bitcast, for example:
// bitcast i8* (alloca i8) to i32*
// would result in a 4-byte load from a 1-byte alloca. Some cases could
- // be handled using TargetData to check sizes and alignments though.
+ // be handled using DataLayout to check sizes and alignments though.
// These are obviously ok.
if (isa<AllocaInst>(V)) return true;
Modified: llvm/branches/R600/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/VMCore/Verifier.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/lib/VMCore/Verifier.cpp (original)
+++ llvm/branches/R600/lib/VMCore/Verifier.cpp Thu Oct 11 16:28:00 2012
@@ -526,40 +526,59 @@
// value of the specified type. The value V is printed in error messages.
void Verifier::VerifyParameterAttrs(Attributes Attrs, Type *Ty,
bool isReturnValue, const Value *V) {
- if (Attrs == Attribute::None)
+ if (!Attrs.hasAttributes())
return;
- Attributes FnCheckAttr = Attrs & Attribute::FunctionOnly;
- Assert1(!FnCheckAttr, "Attribute " + FnCheckAttr.getAsString() +
- " only applies to the function!", V);
-
- if (isReturnValue) {
- Attributes RetI = Attrs & Attribute::ParameterOnly;
- Assert1(!RetI, "Attribute " + RetI.getAsString() +
- " does not apply to return values!", V);
- }
-
- for (unsigned i = 0;
- i < array_lengthof(Attribute::MutuallyIncompatible); ++i) {
- Attributes MutI = Attrs & Attribute::MutuallyIncompatible[i];
- Assert1(MutI.isEmptyOrSingleton(), "Attributes " +
- MutI.getAsString() + " are incompatible!", V);
- }
+ Assert1(!Attrs.hasFunctionOnlyAttrs(),
+ "Some attributes in '" + Attrs.getAsString() +
+ "' only apply to functions!", V);
+
+ if (isReturnValue)
+ Assert1(!Attrs.hasParameterOnlyAttrs(),
+ "Attributes 'byval', 'nest', 'sret', and 'nocapture' "
+ "do not apply to return values!", V);
+
+ // Check for mutually incompatible attributes.
+ Assert1(!((Attrs.hasAttribute(Attributes::ByVal) &&
+ Attrs.hasAttribute(Attributes::Nest)) ||
+ (Attrs.hasAttribute(Attributes::ByVal) &&
+ Attrs.hasAttribute(Attributes::StructRet)) ||
+ (Attrs.hasAttribute(Attributes::Nest) &&
+ Attrs.hasAttribute(Attributes::StructRet))), "Attributes "
+ "'byval, nest, and sret' are incompatible!", V);
+
+ Assert1(!((Attrs.hasAttribute(Attributes::ByVal) &&
+ Attrs.hasAttribute(Attributes::Nest)) ||
+ (Attrs.hasAttribute(Attributes::ByVal) &&
+ Attrs.hasAttribute(Attributes::InReg)) ||
+ (Attrs.hasAttribute(Attributes::Nest) &&
+ Attrs.hasAttribute(Attributes::InReg))), "Attributes "
+ "'byval, nest, and inreg' are incompatible!", V);
+
+ Assert1(!(Attrs.hasAttribute(Attributes::ZExt) &&
+ Attrs.hasAttribute(Attributes::SExt)), "Attributes "
+ "'zeroext and signext' are incompatible!", V);
+
+ Assert1(!(Attrs.hasAttribute(Attributes::ReadNone) &&
+ Attrs.hasAttribute(Attributes::ReadOnly)), "Attributes "
+ "'readnone and readonly' are incompatible!", V);
+
+ Assert1(!(Attrs.hasAttribute(Attributes::NoInline) &&
+ Attrs.hasAttribute(Attributes::AlwaysInline)), "Attributes "
+ "'noinline and alwaysinline' are incompatible!", V);
Attributes TypeI = Attrs & Attributes::typeIncompatible(Ty);
Assert1(!TypeI, "Wrong type for attribute " +
TypeI.getAsString(), V);
- Attributes ByValI = Attrs & Attribute::ByVal;
- if (PointerType *PTy = dyn_cast<PointerType>(Ty)) {
- Assert1(!ByValI || PTy->getElementType()->isSized(),
- "Attribute " + ByValI.getAsString() +
- " does not support unsized types!", V);
- } else {
- Assert1(!ByValI,
- "Attribute " + ByValI.getAsString() +
- " only applies to parameters with pointer type!", V);
- }
+ if (PointerType *PTy = dyn_cast<PointerType>(Ty))
+ Assert1(!Attrs.hasAttribute(Attributes::ByVal) ||
+ PTy->getElementType()->isSized(),
+ "Attribute 'byval' does not support unsized types!", V);
+ else
+ Assert1(!Attrs.hasAttribute(Attributes::ByVal),
+ "Attribute 'byval' only applies to parameters with pointer type!",
+ V);
}
// VerifyFunctionAttrs - Check parameter attributes against a function type.
@@ -585,26 +604,50 @@
VerifyParameterAttrs(Attr.Attrs, Ty, Attr.Index == 0, V);
- if (Attr.Attrs.hasNestAttr()) {
+ if (Attr.Attrs.hasAttribute(Attributes::Nest)) {
Assert1(!SawNest, "More than one parameter has attribute nest!", V);
SawNest = true;
}
- if (Attr.Attrs.hasStructRetAttr())
+ if (Attr.Attrs.hasAttribute(Attributes::StructRet))
Assert1(Attr.Index == 1, "Attribute sret not on first parameter!", V);
}
Attributes FAttrs = Attrs.getFnAttributes();
- Attributes NotFn = FAttrs & (~Attribute::FunctionOnly);
- Assert1(!NotFn, "Attribute " + NotFn.getAsString() +
- " does not apply to the function!", V);
-
- for (unsigned i = 0;
- i < array_lengthof(Attribute::MutuallyIncompatible); ++i) {
- Attributes MutI = FAttrs & Attribute::MutuallyIncompatible[i];
- Assert1(MutI.isEmptyOrSingleton(), "Attributes " +
- MutI.getAsString() + " are incompatible!", V);
- }
+ Attributes::Builder NotFn(FAttrs);
+ NotFn.removeFunctionOnlyAttrs();
+ Assert1(!NotFn.hasAttributes(), "Attributes '" +
+ Attributes::get(NotFn).getAsString() +
+ "' do not apply to the function!", V);
+
+ // Check for mutually incompatible attributes.
+ Assert1(!((FAttrs.hasAttribute(Attributes::ByVal) &&
+ FAttrs.hasAttribute(Attributes::Nest)) ||
+ (FAttrs.hasAttribute(Attributes::ByVal) &&
+ FAttrs.hasAttribute(Attributes::StructRet)) ||
+ (FAttrs.hasAttribute(Attributes::Nest) &&
+ FAttrs.hasAttribute(Attributes::StructRet))), "Attributes "
+ "'byval, nest, and sret' are incompatible!", V);
+
+ Assert1(!((FAttrs.hasAttribute(Attributes::ByVal) &&
+ FAttrs.hasAttribute(Attributes::Nest)) ||
+ (FAttrs.hasAttribute(Attributes::ByVal) &&
+ FAttrs.hasAttribute(Attributes::InReg)) ||
+ (FAttrs.hasAttribute(Attributes::Nest) &&
+ FAttrs.hasAttribute(Attributes::InReg))), "Attributes "
+ "'byval, nest, and inreg' are incompatible!", V);
+
+ Assert1(!(FAttrs.hasAttribute(Attributes::ZExt) &&
+ FAttrs.hasAttribute(Attributes::SExt)), "Attributes "
+ "'zeroext and signext' are incompatible!", V);
+
+ Assert1(!(FAttrs.hasAttribute(Attributes::ReadNone) &&
+ FAttrs.hasAttribute(Attributes::ReadOnly)), "Attributes "
+ "'readnone and readonly' are incompatible!", V);
+
+ Assert1(!(FAttrs.hasAttribute(Attributes::NoInline) &&
+ FAttrs.hasAttribute(Attributes::AlwaysInline)), "Attributes "
+ "'noinline and alwaysinline' are incompatible!", V);
}
static bool VerifyAttributeCount(const AttrListPtr &Attrs, unsigned Params) {
@@ -1170,9 +1213,8 @@
VerifyParameterAttrs(Attr, CS.getArgument(Idx-1)->getType(), false, I);
- Attributes VArgI = Attr & Attribute::VarArgsIncompatible;
- Assert1(!VArgI, "Attribute " + VArgI.getAsString() +
- " cannot be used for vararg call arguments!", I);
+ Assert1(!Attr.hasIncompatibleWithVarArgsAttrs(),
+ "Attribute 'sret' cannot be used for vararg call arguments!", I);
}
// Verify that there's no metadata unless it's a direct call to an intrinsic.
Modified: llvm/branches/R600/runtime/libprofile/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/runtime/libprofile/Makefile?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/runtime/libprofile/Makefile (original)
+++ llvm/branches/R600/runtime/libprofile/Makefile Thu Oct 11 16:28:00 2012
@@ -44,8 +44,15 @@
# command line.
DARWIN_VERS := $(shell echo $(TARGET_TRIPLE) | sed 's/.*darwin\([0-9]*\).*/\1/')
ifneq ($(DARWIN_VERS),8)
- LLVMLibsOptions := $(LLVMLibsOptions) \
+ LLVMLibsOptions := $(LLVMLibsOptions) \
-Wl,-install_name \
-Wl,"@executable_path/../lib/lib$(LIBRARYNAME)$(SHLIBEXT)"
endif
+
+ # If we're doing an Apple-style build, add the LTO object path.
+ ifeq ($(RC_BUILDIT),YES)
+ TempFile := $(shell mkdir -p ${OBJROOT}/dSYMs ; mktemp ${OBJROOT}/dSYMs/profile_rt-lto.XXXXXX)
+ LLVMLibsOptions := $(LLVMLibsOptions) \
+ -Wl,-object_path_lto -Wl,$(TempFile)
+ endif
endif
Modified: llvm/branches/R600/test/Assembler/2008-09-02-FunctionNotes2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Assembler/2008-09-02-FunctionNotes2.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Assembler/2008-09-02-FunctionNotes2.ll (original)
+++ llvm/branches/R600/test/Assembler/2008-09-02-FunctionNotes2.ll Thu Oct 11 16:28:00 2012
@@ -1,5 +1,5 @@
; Test function notes
-; RUN: not llvm-as %s -o /dev/null 2>&1 | grep "Attributes noinline alwaysinline are incompatible"
+; RUN: not llvm-as %s -o /dev/null 2>&1 | grep "Attributes 'noinline and alwaysinline' are incompatible"
define void @fn1() alwaysinline noinline {
ret void
}
Modified: llvm/branches/R600/test/Bindings/Ocaml/ipo_opts.ml
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Bindings/Ocaml/ipo_opts.ml?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Bindings/Ocaml/ipo_opts.ml (original)
+++ llvm/branches/R600/test/Bindings/Ocaml/ipo_opts.ml Thu Oct 11 16:28:00 2012
@@ -43,10 +43,10 @@
ignore (build_ret (build_call fn [| |] "" b) b);
end;
- let td = TargetData.create (target_triple m) in
+ let td = DataLayout.create (target_triple m) in
ignore (PassManager.create ()
- ++ TargetData.add td
+ ++ DataLayout.add td
++ add_argument_promotion
++ add_constant_merge
++ add_dead_arg_elimination
@@ -63,7 +63,7 @@
++ PassManager.run_module m
++ PassManager.dispose);
- TargetData.dispose td
+ DataLayout.dispose td
(*===-- Driver ------------------------------------------------------------===*)
Modified: llvm/branches/R600/test/Bindings/Ocaml/scalar_opts.ml
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Bindings/Ocaml/scalar_opts.ml?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Bindings/Ocaml/scalar_opts.ml (original)
+++ llvm/branches/R600/test/Bindings/Ocaml/scalar_opts.ml Thu Oct 11 16:28:00 2012
@@ -38,10 +38,10 @@
let fn = define_function "fn" fty m in
ignore (build_ret_void (builder_at_end context (entry_block fn)));
- let td = TargetData.create (target_triple m) in
+ let td = DataLayout.create (target_triple m) in
ignore (PassManager.create_function m
- ++ TargetData.add td
+ ++ DataLayout.add td
++ add_verifier
++ add_constant_propagation
++ add_sccp
@@ -78,7 +78,7 @@
++ PassManager.finalize
++ PassManager.dispose);
- TargetData.dispose td
+ DataLayout.dispose td
(*===-- Driver ------------------------------------------------------------===*)
Modified: llvm/branches/R600/test/Bindings/Ocaml/target.ml
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Bindings/Ocaml/target.ml?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Bindings/Ocaml/target.ml (original)
+++ llvm/branches/R600/test/Bindings/Ocaml/target.ml Thu Oct 11 16:28:00 2012
@@ -33,10 +33,10 @@
(*===-- Target Data -------------------------------------------------------===*)
let test_target_data () =
- let td = TargetData.create (target_triple m) in
+ let td = DataLayout.create (target_triple m) in
let sty = struct_type context [| i32_type; i64_type |] in
- ignore (TargetData.as_string td);
+ ignore (DataLayout.as_string td);
ignore (byte_order td);
ignore (pointer_size td);
ignore (intptr_type td);
@@ -49,7 +49,7 @@
ignore (element_at_offset td sty (Int64.of_int 1));
ignore (offset_of_element td sty 1);
- TargetData.dispose td
+ DataLayout.dispose td
(*===-- Driver ------------------------------------------------------------===*)
Modified: llvm/branches/R600/test/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CMakeLists.txt?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/CMakeLists.txt (original)
+++ llvm/branches/R600/test/CMakeLists.txt Thu Oct 11 16:28:00 2012
@@ -7,6 +7,11 @@
${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg
)
+# Don't include check-llvm into check-all without LLVM_BUILD_TOOLS.
+if(NOT LLVM_BUILD_TOOLS)
+ set(EXCLUDE_FROM_ALL ON)
+endif()
+
add_lit_testsuite(check-llvm "Running the LLVM regression tests"
${CMAKE_CURRENT_BINARY_DIR}
PARAMS llvm_site_config=${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg
Added: llvm/branches/R600/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll (added)
+++ llvm/branches/R600/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s
+
+ at .str = private unnamed_addr constant [12 x i8] c"val.a = %f\0A\00"
+%struct_t = type { double, double, double }
+ at static_val = constant %struct_t { double 1.0, double 2.0, double 3.0 }
+
+declare i32 @printf(i8*, ...)
+
+; CHECK: test_byval_usage_scheduling:
+; CHECK: str r3, [sp, #12]
+; CHECK: str r2, [sp, #8]
+; CHECK: vldr d16, [sp, #8]
+define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval %val) nounwind {
+entry:
+ %a = getelementptr inbounds %struct_t* %val, i32 0, i32 0
+ %0 = load double* %a
+ %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), double %0)
+ ret void
+}
Added: llvm/branches/R600/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll (added)
+++ llvm/branches/R600/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,23 @@
+; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s
+; Check that LDRB_POST_IMM instruction emitted properly.
+
+%my_struct_t = type { double, double, double }
+ at main.val = private unnamed_addr constant %my_struct_t { double 1.0, double 2.0, double 3.0 }, align 8
+
+declare void @f(i32 %n1, %my_struct_t* byval %val);
+
+
+; CHECK: main:
+define i32 @main() nounwind {
+entry:
+ %val = alloca %my_struct_t, align 8
+ %0 = bitcast %my_struct_t* %val to i8*
+
+; CHECK: ldrb {{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1
+ call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* bitcast (%my_struct_t* @main.val to i8*), i32 24, i32 8, i1 false)
+
+ call void @f(i32 555, %my_struct_t* byval %val)
+ ret i32 0
+}
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
Modified: llvm/branches/R600/test/CodeGen/ARM/coalesce-subregs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/ARM/coalesce-subregs.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/CodeGen/ARM/coalesce-subregs.ll (original)
+++ llvm/branches/R600/test/CodeGen/ARM/coalesce-subregs.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mcpu=cortex-a9 -new-coalescer | FileCheck %s
+; RUN: llc < %s -mcpu=cortex-a9 -verify-coalescing | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
target triple = "thumbv7-apple-ios0.0.0"
@@ -189,3 +189,28 @@
declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
+
+; CHECK: pr13999
+define void @pr13999() nounwind readonly {
+entry:
+ br i1 true, label %outer_loop, label %loop.end
+
+outer_loop:
+ %d = phi double [ 0.0, %entry ], [ %add, %after_inner_loop ]
+ %0 = insertelement <2 x double> <double 0.0, double 0.0>, double %d, i32 0
+ br i1 undef, label %after_inner_loop, label %inner_loop
+
+inner_loop:
+ br i1 true, label %after_inner_loop, label %inner_loop
+
+after_inner_loop:
+ %1 = phi <2 x double> [ %0, %outer_loop ], [ <double 0.0, double 0.0>,
+%inner_loop ]
+ %2 = extractelement <2 x double> %1, i32 1
+ %add = fadd double 1.0, %2
+ br i1 false, label %loop.end, label %outer_loop
+
+loop.end:
+ %d.end = phi double [ 0.0, %entry ], [ %add, %after_inner_loop ]
+ ret void
+}
Added: llvm/branches/R600/test/CodeGen/ARM/darwin-section-order.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/ARM/darwin-section-order.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/ARM/darwin-section-order.ll (added)
+++ llvm/branches/R600/test/CodeGen/ARM/darwin-section-order.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,21 @@
+; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
+
+; CHECK: .section __TEXT,__text,regular,pure_instructions
+; CHECK: .section __TEXT,myprecious
+; CHECK: .section __TEXT,__textcoal_nt,coalesced,pure_instructions
+; CHECK: .section __TEXT,__const_coal,coalesced
+; CHECK: .section __TEXT,__picsymbolstub4,symbol_stubs,none,16
+; CHECK: .section __TEXT,__StaticInit,regular,pure_instructions
+
+
+define void @normal() nounwind readnone {
+; CHECK: .section __TEXT,__text,regular,pure_instructions
+; CHECK: _normal:
+ ret void
+}
+
+define void @special() nounwind readnone section "__TEXT,myprecious" {
+; CHECK: .section __TEXT,myprecious
+; CHECK: _special:
+ ret void
+}
Added: llvm/branches/R600/test/CodeGen/ARM/deps-fix.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/ARM/deps-fix.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/ARM/deps-fix.ll (added)
+++ llvm/branches/R600/test/CodeGen/ARM/deps-fix.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,22 @@
+; RUN: llc < %s -march=arm -mcpu=cortex-a9 -mattr=+neon,+neonfp -float-abi=hard -mtriple armv7-linux-gnueabi | FileCheck %s
+
+;; This test checks that the ExecutionDepsFix pass performs the domain changes
+;; even when some dependencies are propagated through implicit definitions.
+
+; CHECK: fun_a
+define <4 x float> @fun_a(<4 x float> %in, <4 x float> %x, float %y) nounwind {
+; CHECK: vext
+; CHECK: vext
+; CHECK: vadd.f32
+ %1 = insertelement <4 x float> %in, float %y, i32 0
+ %2 = fadd <4 x float> %1, %x
+ ret <4 x float> %2
+}
+; CHECK: fun_b
+define <4 x i32> @fun_b(<4 x i32> %in, <4 x i32> %x, i32 %y) nounwind {
+; CHECK: vmov.32
+; CHECK: vadd.i32
+ %1 = insertelement <4 x i32> %in, i32 %y, i32 0
+ %2 = add <4 x i32> %1, %x
+ ret <4 x i32> %2
+}
Modified: llvm/branches/R600/test/CodeGen/CellSPU/icmp16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/CellSPU/icmp16.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/CodeGen/CellSPU/icmp16.ll (original)
+++ llvm/branches/R600/test/CodeGen/CellSPU/icmp16.ll Thu Oct 11 16:28:00 2012
@@ -534,7 +534,7 @@
define i16 @icmp_slt_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
; CHECK: icmp_slt_immed04_i16:
; CHECK: lr
-; CHECK-NETX: bi
+; CHECK-NEXT: bi
entry:
%A = icmp slt i16 %arg1, 32768
@@ -559,7 +559,7 @@
; CHECK: ilhu
; CHECK: xorhi
; CHECK: iohl
-; CHECK-NETX: bi
+; CHECK: bi
entry:
%A = icmp sle i16 %arg1, %arg2
Added: llvm/branches/R600/test/CodeGen/Mips/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/Mips/mul.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/Mips/mul.ll (added)
+++ llvm/branches/R600/test/CodeGen/Mips/mul.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,17 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+ at iiii = global i32 5, align 4
+ at jjjj = global i32 -6, align 4
+ at kkkk = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @iiii, align 4
+ %1 = load i32* @jjjj, align 4
+ %mul = mul nsw i32 %1, %0
+; 16: mult ${{[0-9]+}}, ${{[0-9]+}}
+; 16: mflo ${{[0-9]+}}
+
+ store i32 %mul, i32* @kkkk, align 4
+ ret void
+}
Added: llvm/branches/R600/test/CodeGen/Mips/mulll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/Mips/mulll.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/Mips/mulll.ll (added)
+++ llvm/branches/R600/test/CodeGen/Mips/mulll.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,21 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+ at iiii = global i64 5, align 8
+ at jjjj = global i64 -6, align 8
+ at kkkk = common global i64 0, align 8
+
+define void @test() nounwind {
+entry:
+ %0 = load i64* @iiii, align 8
+ %1 = load i64* @jjjj, align 8
+ %mul = mul nsw i64 %1, %0
+ store i64 %mul, i64* @kkkk, align 8
+; 16: multu ${{[0-9]+}}, ${{[0-9]+}}
+; 16: mfhi ${{[0-9]+}}
+; 16: mult ${{[0-9]+}}, ${{[0-9]+}}
+; 16: mflo ${{[0-9]+}}
+; 16: mult ${{[0-9]+}}, ${{[0-9]+}}
+; 16: mflo ${{[0-9]+}}
+
+ ret void
+}
Added: llvm/branches/R600/test/CodeGen/Mips/mulull.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/Mips/mulull.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/Mips/mulull.ll (added)
+++ llvm/branches/R600/test/CodeGen/Mips/mulull.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,21 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+ at iiii = global i64 5, align 8
+ at jjjj = global i64 6, align 8
+ at kkkk = common global i64 0, align 8
+ at .str = private unnamed_addr constant [20 x i8] c"%lld * %lld = %lld\0A\00", align 1
+
+define void @test() nounwind {
+entry:
+ %0 = load i64* @iiii, align 8
+ %1 = load i64* @jjjj, align 8
+ %mul = mul nsw i64 %1, %0
+ store i64 %mul, i64* @kkkk, align 8
+; 16: multu ${{[0-9]+}}, ${{[0-9]+}}
+; 16: mfhi ${{[0-9]+}}
+; 16: mult ${{[0-9]+}}, ${{[0-9]+}}
+; 16: mflo ${{[0-9]+}}
+; 16: mult ${{[0-9]+}}, ${{[0-9]+}}
+; 16: mflo ${{[0-9]+}}
+ ret void
+}
Added: llvm/branches/R600/test/CodeGen/Mips/return-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/Mips/return-vector.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/Mips/return-vector.ll (added)
+++ llvm/branches/R600/test/CodeGen/Mips/return-vector.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,244 @@
+; RUN: llc -march=mipsel < %s | FileCheck %s
+
+
+; Check that function accesses vector return value from stack in cases when
+; vector can't be returned in registers. Also check that caller passes in
+; register $4 stack address where the vector should be placed.
+
+
+declare <8 x i32> @i8(...)
+declare <4 x float> @f4(...)
+declare <4 x double> @d4(...)
+
+define i32 @call_i8() {
+entry:
+ %call = call <8 x i32> (...)* @i8()
+ %v0 = extractelement <8 x i32> %call, i32 0
+ %v1 = extractelement <8 x i32> %call, i32 1
+ %v2 = extractelement <8 x i32> %call, i32 2
+ %v3 = extractelement <8 x i32> %call, i32 3
+ %v4 = extractelement <8 x i32> %call, i32 4
+ %v5 = extractelement <8 x i32> %call, i32 5
+ %v6 = extractelement <8 x i32> %call, i32 6
+ %v7 = extractelement <8 x i32> %call, i32 7
+ %add1 = add i32 %v0, %v1
+ %add2 = add i32 %v2, %v3
+ %add3 = add i32 %v4, %v5
+ %add4 = add i32 %v6, %v7
+ %add5 = add i32 %add1, %add2
+ %add6 = add i32 %add3, %add4
+ %add7 = add i32 %add5, %add6
+ ret i32 %add7
+
+; CHECK: call_i8:
+; CHECK: call16(i8)
+; CHECK: addiu $4, $sp, 32
+; CHECK: lw $[[R0:[a-z0-9]+]], 60($sp)
+; CHECK: lw $[[R1:[a-z0-9]+]], 56($sp)
+; CHECK: lw $[[R2:[a-z0-9]+]], 52($sp)
+; CHECK: lw $[[R3:[a-z0-9]+]], 48($sp)
+; CHECK: lw $[[R4:[a-z0-9]+]], 44($sp)
+; CHECK: lw $[[R5:[a-z0-9]+]], 40($sp)
+; CHECK: lw $[[R6:[a-z0-9]+]], 36($sp)
+; CHECK: lw $[[R7:[a-z0-9]+]], 32($sp)
+}
+
+
+define float @call_f4() {
+entry:
+ %call = call <4 x float> (...)* @f4()
+ %v0 = extractelement <4 x float> %call, i32 0
+ %v1 = extractelement <4 x float> %call, i32 1
+ %v2 = extractelement <4 x float> %call, i32 2
+ %v3 = extractelement <4 x float> %call, i32 3
+ %add1 = fadd float %v0, %v1
+ %add2 = fadd float %v2, %v3
+ %add3 = fadd float %add1, %add2
+ ret float %add3
+
+; CHECK: call_f4:
+; CHECK: call16(f4)
+; CHECK: addiu $4, $sp, 16
+; CHECK: lwc1 $[[R0:[a-z0-9]+]], 28($sp)
+; CHECK: lwc1 $[[R1:[a-z0-9]+]], 24($sp)
+; CHECK: lwc1 $[[R3:[a-z0-9]+]], 20($sp)
+; CHECK: lwc1 $[[R4:[a-z0-9]+]], 16($sp)
+}
+
+
+define double @call_d4() {
+entry:
+ %call = call <4 x double> (...)* @d4()
+ %v0 = extractelement <4 x double> %call, i32 0
+ %v1 = extractelement <4 x double> %call, i32 1
+ %v2 = extractelement <4 x double> %call, i32 2
+ %v3 = extractelement <4 x double> %call, i32 3
+ %add1 = fadd double %v0, %v1
+ %add2 = fadd double %v2, %v3
+ %add3 = fadd double %add1, %add2
+ ret double %add3
+
+; CHECK: call_d4:
+; CHECK: call16(d4)
+; CHECK: addiu $4, $sp, 32
+; CHECK: ldc1 $[[R0:[a-z0-9]+]], 56($sp)
+; CHECK: ldc1 $[[R1:[a-z0-9]+]], 48($sp)
+; CHECK: ldc1 $[[R3:[a-z0-9]+]], 40($sp)
+; CHECK: ldc1 $[[R4:[a-z0-9]+]], 32($sp)
+}
+
+
+
+; Check that function accesses vector return value from registers in cases when
+; vector can be returned in registers
+
+
+declare <4 x i32> @i4(...)
+declare <2 x float> @f2(...)
+declare <2 x double> @d2(...)
+
+define i32 @call_i4() {
+entry:
+ %call = call <4 x i32> (...)* @i4()
+ %v0 = extractelement <4 x i32> %call, i32 0
+ %v1 = extractelement <4 x i32> %call, i32 1
+ %v2 = extractelement <4 x i32> %call, i32 2
+ %v3 = extractelement <4 x i32> %call, i32 3
+ %add1 = add i32 %v0, %v1
+ %add2 = add i32 %v2, %v3
+ %add3 = add i32 %add1, %add2
+ ret i32 %add3
+
+; CHECK: call_i4:
+; CHECK: call16(i4)
+; CHECK-NOT: lw
+; CHECK: addu $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
+; CHECK: addu $[[R5:[a-z0-9]+]], $[[R3:[a-z0-9]+]], $[[R4:[a-z0-9]+]]
+; CHECK: addu $[[R6:[a-z0-9]+]], $[[R5]], $[[R2]]
+}
+
+
+define float @call_f2() {
+entry:
+ %call = call <2 x float> (...)* @f2()
+ %v0 = extractelement <2 x float> %call, i32 0
+ %v1 = extractelement <2 x float> %call, i32 1
+ %add1 = fadd float %v0, %v1
+ ret float %add1
+
+; CHECK: call_f2:
+; CHECK: call16(f2)
+; CHECK-NOT: lwc1
+; CHECK: add.s $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
+}
+
+
+define double @call_d2() {
+entry:
+ %call = call <2 x double> (...)* @d2()
+ %v0 = extractelement <2 x double> %call, i32 0
+ %v1 = extractelement <2 x double> %call, i32 1
+ %add1 = fadd double %v0, %v1
+ ret double %add1
+
+; CHECK: call_d2:
+; CHECK: call16(d2)
+; CHECK-NOT: ldc1
+; CHECK: add.d $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
+}
+
+
+
+; Check that function returns vector on stack in cases when vector can't be
+; returned in registers. Also check that vector is placed on stack starting
+; from the address in register $4.
+
+
+define <8 x i32> @return_i8() {
+entry:
+ ret <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+
+; CHECK: return_i8:
+; CHECK: sw $[[R0:[a-z0-9]+]], 28($4)
+; CHECK: sw $[[R1:[a-z0-9]+]], 24($4)
+; CHECK: sw $[[R2:[a-z0-9]+]], 20($4)
+; CHECK: sw $[[R3:[a-z0-9]+]], 16($4)
+; CHECK: sw $[[R4:[a-z0-9]+]], 12($4)
+; CHECK: sw $[[R5:[a-z0-9]+]], 8($4)
+; CHECK: sw $[[R6:[a-z0-9]+]], 4($4)
+; CHECK: sw $[[R7:[a-z0-9]+]], 0($4)
+}
+
+
+define <4 x float> @return_f4(float %a, float %b, float %c, float %d) {
+entry:
+ %vecins1 = insertelement <4 x float> undef, float %a, i32 0
+ %vecins2 = insertelement <4 x float> %vecins1, float %b, i32 1
+ %vecins3 = insertelement <4 x float> %vecins2, float %c, i32 2
+ %vecins4 = insertelement <4 x float> %vecins3, float %d, i32 3
+ ret <4 x float> %vecins4
+
+; CHECK: return_f4:
+; CHECK: lwc1 $[[R0:[a-z0-9]+]], 16($sp)
+; CHECK: swc1 $[[R0]], 12($4)
+; CHECK: sw $7, 8($4)
+; CHECK: sw $6, 4($4)
+; CHECK: sw $5, 0($4)
+}
+
+
+define <4 x double> @return_d4(double %a, double %b, double %c, double %d) {
+entry:
+ %vecins1 = insertelement <4 x double> undef, double %a, i32 0
+ %vecins2 = insertelement <4 x double> %vecins1, double %b, i32 1
+ %vecins3 = insertelement <4 x double> %vecins2, double %c, i32 2
+ %vecins4 = insertelement <4 x double> %vecins3, double %d, i32 3
+ ret <4 x double> %vecins4
+
+; CHECK: return_d4:
+; CHECK: sdc1 $[[R0:[a-z0-9]+]], 24($4)
+; CHECK: sdc1 $[[R1:[a-z0-9]+]], 16($4)
+; CHECK: sdc1 $[[R2:[a-z0-9]+]], 8($4)
+; CHECK: sdc1 $[[R3:[a-z0-9]+]], 0($4)
+}
+
+
+
+; Check that function returns vector in registers in cases when vector can be
+; returned in registers.
+
+
+define <4 x i32> @return_i4() {
+entry:
+ ret <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+
+; CHECK: return_i4:
+; CHECK: addiu $2, $zero, 0
+; CHECK: addiu $3, $zero, 1
+; CHECK: addiu $4, $zero, 2
+; CHECK: addiu $5, $zero, 3
+}
+
+
+define <2 x float> @return_f2(float %a, float %b) {
+entry:
+ %vecins1 = insertelement <2 x float> undef, float %a, i32 0
+ %vecins2 = insertelement <2 x float> %vecins1, float %b, i32 1
+ ret <2 x float> %vecins2
+
+; CHECK: return_f2:
+; CHECK: mov.s $f0, $f12
+; CHECK: mov.s $f2, $f14
+}
+
+
+define <2 x double> @return_d2(double %a, double %b) {
+entry:
+ %vecins1 = insertelement <2 x double> undef, double %a, i32 0
+ %vecins2 = insertelement <2 x double> %vecins1, double %b, i32 1
+ ret <2 x double> %vecins2
+
+; CHECK: return_d2:
+; CHECK: mov.d $f0, $f12
+; CHECK: mov.d $f2, $f14
+}
Modified: llvm/branches/R600/test/CodeGen/PowerPC/ppc64-toc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/PowerPC/ppc64-toc.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/CodeGen/PowerPC/ppc64-toc.ll (original)
+++ llvm/branches/R600/test/CodeGen/PowerPC/ppc64-toc.ll Thu Oct 11 16:28:00 2012
@@ -1,68 +1,68 @@
-; RUN: llc < %s | FileCheck %s
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
- at double_array = global [32 x double] zeroinitializer, align 8
- at number64 = global i64 10, align 8
- at internal_static_var.x = internal unnamed_addr global i64 0, align 8
-
-define i64 @access_int64(i64 %a) nounwind readonly {
-entry:
-; CHECK: access_int64:
-; CHECK-NEXT: .align 3
-; CHECK-NEXT: .quad .L.access_int64
-; CHECK-NEXT: .quad .TOC. at tocbase
-; CHECK-NEXT: .quad 0
-; CHECK-NEXT: .text
- %0 = load i64* @number64, align 8
-; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
- %cmp = icmp eq i64 %0, %a
- %conv1 = zext i1 %cmp to i64
- ret i64 %conv1
-}
-
-define i64 @internal_static_var(i64 %a) nounwind {
-entry:
-; CHECK: internal_static_var:
-; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
- %0 = load i64* @internal_static_var.x, align 8
- %cmp = icmp eq i64 %0, %a
- %conv1 = zext i1 %cmp to i64
- ret i64 %conv1
-}
-
-define i32 @access_double(double %a) nounwind readnone {
-entry:
-; CHECK: access_double:
-; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
- %cmp = fcmp oeq double %a, 2.000000e+00
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-
-define i32 @access_double_array(double %a, i32 %i) nounwind readonly {
-entry:
-; CHECK: access_double_array:
- %idxprom = sext i32 %i to i64
- %arrayidx = getelementptr inbounds [32 x double]* @double_array, i64 0, i64 %idxprom
- %0 = load double* %arrayidx, align 8
-; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
- %cmp = fcmp oeq double %0, %a
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-; Check the creation of 4 .tc entries:
-; * int64_t global 'number64'
-; * double constant 2.0
-; * double array 'double_array'
-; * static int64_t 'x' accessed within '@internal_static_var'
-; CHECK: .LC{{[0-9]+}}:
-; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
-; CHECK-NEXT: .LC{{[0-9]+}}:
-; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
-; CHECK-NEXT: .LC{{[0-9]+}}:
-; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
-; CHECK-NEXT: .LC{{[0-9]+}}:
-; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+ at double_array = global [32 x double] zeroinitializer, align 8
+ at number64 = global i64 10, align 8
+ at internal_static_var.x = internal unnamed_addr global i64 0, align 8
+
+define i64 @access_int64(i64 %a) nounwind readonly {
+entry:
+; CHECK: access_int64:
+; CHECK-NEXT: .align 3
+; CHECK-NEXT: .quad .L.access_int64
+; CHECK-NEXT: .quad .TOC. at tocbase
+; CHECK-NEXT: .quad 0
+; CHECK-NEXT: .text
+ %0 = load i64* @number64, align 8
+; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
+ %cmp = icmp eq i64 %0, %a
+ %conv1 = zext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+define i64 @internal_static_var(i64 %a) nounwind {
+entry:
+; CHECK: internal_static_var:
+; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
+ %0 = load i64* @internal_static_var.x, align 8
+ %cmp = icmp eq i64 %0, %a
+ %conv1 = zext i1 %cmp to i64
+ ret i64 %conv1
+}
+
+define i32 @access_double(double %a) nounwind readnone {
+entry:
+; CHECK: access_double:
+; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
+ %cmp = fcmp oeq double %a, 2.000000e+00
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+
+define i32 @access_double_array(double %a, i32 %i) nounwind readonly {
+entry:
+; CHECK: access_double_array:
+ %idxprom = sext i32 %i to i64
+ %arrayidx = getelementptr inbounds [32 x double]* @double_array, i64 0, i64 %idxprom
+ %0 = load double* %arrayidx, align 8
+; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
+ %cmp = fcmp oeq double %0, %a
+ %conv = zext i1 %cmp to i32
+ ret i32 %conv
+}
+
+; Check the creation of 4 .tc entries:
+; * int64_t global 'number64'
+; * double constant 2.0
+; * double array 'double_array'
+; * static int64_t 'x' accessed within '@internal_static_var'
+; CHECK: .LC{{[0-9]+}}:
+; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
+; CHECK-NEXT: .LC{{[0-9]+}}:
+; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
+; CHECK-NEXT: .LC{{[0-9]+}}:
+; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
+; CHECK-NEXT: .LC{{[0-9]+}}:
+; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
Added: llvm/branches/R600/test/CodeGen/PowerPC/vec_cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/PowerPC/vec_cmp.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/PowerPC/vec_cmp.ll (added)
+++ llvm/branches/R600/test/CodeGen/PowerPC/vec_cmp.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,191 @@
+; RUN: llc -mattr=+altivec < %s | FileCheck %s
+
+; Check vector comparisons using altivec.
+
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define <2 x i8> @v2si8_cmp(<2 x i8> %x, <2 x i8> %y) nounwind readnone {
+ %cmp = icmp eq <2 x i8> %x, %y
+ %sext = sext <2 x i1> %cmp to <2 x i8>
+ ret <2 x i8> %sext
+}
+; CHECK: v2si8_cmp:
+; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <4 x i8> @v4si8_cmp(<4 x i8> %x, <4 x i8> %y) nounwind readnone {
+ %cmp = icmp eq <4 x i8> %x, %y
+ %sext = sext <4 x i1> %cmp to <4 x i8>
+ ret <4 x i8> %sext
+}
+; CHECK: v4si8_cmp:
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <8 x i8> @v8si8_cmp(<8 x i8> %x, <8 x i8> %y) nounwind readnone {
+ %cmp = icmp eq <8 x i8> %x, %y
+ %sext = sext <8 x i1> %cmp to <8 x i8>
+ ret <8 x i8> %sext
+}
+; CHECK: v8si8_cmp:
+; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <16 x i8> @v16si8_cmp(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
+ %cmp = icmp eq <16 x i8> %x, %y
+ %sext = sext <16 x i1> %cmp to <16 x i8>
+ ret <16 x i8> %sext
+}
+; CHECK: v16si8_cmp:
+; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <32 x i8> @v32si8_cmp(<32 x i8> %x, <32 x i8> %y) nounwind readnone {
+ %cmp = icmp eq <32 x i8> %x, %y
+ %sext = sext <32 x i1> %cmp to <32 x i8>
+ ret <32 x i8> %sext
+}
+; CHECK: v32si8_cmp:
+; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <2 x i16> @v2si16_cmp(<2 x i16> %x, <2 x i16> %y) nounwind readnone {
+ %cmp = icmp eq <2 x i16> %x, %y
+ %sext = sext <2 x i1> %cmp to <2 x i16>
+ ret <2 x i16> %sext
+}
+; CHECK: v2si16_cmp:
+; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <4 x i16> @v4si16_cmp(<4 x i16> %x, <4 x i16> %y) nounwind readnone {
+ %cmp = icmp eq <4 x i16> %x, %y
+ %sext = sext <4 x i1> %cmp to <4 x i16>
+ ret <4 x i16> %sext
+}
+; CHECK: v4si16_cmp:
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <8 x i16> @v8si16_cmp(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
+ %cmp = icmp eq <8 x i16> %x, %y
+ %sext = sext <8 x i1> %cmp to <8 x i16>
+ ret <8 x i16> %sext
+}
+; CHECK: v8si16_cmp:
+; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <16 x i16> @v16si16_cmp(<16 x i16> %x, <16 x i16> %y) nounwind readnone {
+ %cmp = icmp eq <16 x i16> %x, %y
+ %sext = sext <16 x i1> %cmp to <16 x i16>
+ ret <16 x i16> %sext
+}
+; CHECK: v16si16_cmp:
+; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <32 x i16> @v32si16_cmp(<32 x i16> %x, <32 x i16> %y) nounwind readnone {
+ %cmp = icmp eq <32 x i16> %x, %y
+ %sext = sext <32 x i1> %cmp to <32 x i16>
+ ret <32 x i16> %sext
+}
+; CHECK: v32si16_cmp:
+; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <2 x i32> @v2si32_cmp(<2 x i32> %x, <2 x i32> %y) nounwind readnone {
+ %cmp = icmp eq <2 x i32> %x, %y
+ %sext = sext <2 x i1> %cmp to <2 x i32>
+ ret <2 x i32> %sext
+}
+; CHECK: v2si32_cmp:
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <4 x i32> @v4si32_cmp(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
+ %cmp = icmp eq <4 x i32> %x, %y
+ %sext = sext <4 x i1> %cmp to <4 x i32>
+ ret <4 x i32> %sext
+}
+; CHECK: v4si32_cmp:
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <8 x i32> @v8si32_cmp(<8 x i32> %x, <8 x i32> %y) nounwind readnone {
+ %cmp = icmp eq <8 x i32> %x, %y
+ %sext = sext <8 x i1> %cmp to <8 x i32>
+ ret <8 x i32> %sext
+}
+; CHECK: v8si32_cmp:
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <16 x i32> @v16si32_cmp(<16 x i32> %x, <16 x i32> %y) nounwind readnone {
+ %cmp = icmp eq <16 x i32> %x, %y
+ %sext = sext <16 x i1> %cmp to <16 x i32>
+ ret <16 x i32> %sext
+}
+; CHECK: v16si32_cmp:
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <32 x i32> @v32si32_cmp(<32 x i32> %x, <32 x i32> %y) nounwind readnone {
+ %cmp = icmp eq <32 x i32> %x, %y
+ %sext = sext <32 x i1> %cmp to <32 x i32>
+ ret <32 x i32> %sext
+}
+; CHECK: v32si32_cmp:
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <2 x float> @v2f32_cmp(<2 x float> %x, <2 x float> %y) nounwind readnone {
+entry:
+ %cmp = fcmp oeq <2 x float> %x, %y
+ %sext = sext <2 x i1> %cmp to <2 x i32>
+ %0 = bitcast <2 x i32> %sext to <2 x float>
+ ret <2 x float> %0
+}
+; CHECK: v2f32_cmp:
+; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <4 x float> @v4f32_cmp(<4 x float> %x, <4 x float> %y) nounwind readnone {
+entry:
+ %cmp = fcmp oeq <4 x float> %x, %y
+ %sext = sext <4 x i1> %cmp to <4 x i32>
+ %0 = bitcast <4 x i32> %sext to <4 x float>
+ ret <4 x float> %0
+}
+; CHECK: v4f32_cmp:
+; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+
+define <8 x float> @v8f32_cmp(<8 x float> %x, <8 x float> %y) nounwind readnone {
+entry:
+ %cmp = fcmp oeq <8 x float> %x, %y
+ %sext = sext <8 x i1> %cmp to <8 x i32>
+ %0 = bitcast <8 x i32> %sext to <8 x float>
+ ret <8 x float> %0
+}
+; CHECK: v8f32_cmp:
+; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
Added: llvm/branches/R600/test/CodeGen/PowerPC/vec_conv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/PowerPC/vec_conv.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/PowerPC/vec_conv.ll (added)
+++ llvm/branches/R600/test/CodeGen/PowerPC/vec_conv.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,57 @@
+; RUN: llc -mattr=+altivec < %s | FileCheck %s
+
+; Check vector float/int conversion using altivec.
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+ at cte_float = global <4 x float> <float 6.5e+00, float 6.5e+00, float 6.5e+00, float 6.5e+00>, align 16
+ at cte_int = global <4 x i32> <i32 6, i32 6, i32 6, i32 6>, align 16
+
+
+define void @v4f32_to_v4i32(<4 x float> %x, <4 x i32>* nocapture %y) nounwind {
+entry:
+ %0 = load <4 x float>* @cte_float, align 16
+ %mul = fmul <4 x float> %0, %x
+ %1 = fptosi <4 x float> %mul to <4 x i32>
+ store <4 x i32> %1, <4 x i32>* %y, align 16
+ ret void
+}
+;CHECK: v4f32_to_v4i32:
+;CHECK: vctsxs {{[0-9]+}}, {{[0-9]+}}, 0
+
+
+define void @v4f32_to_v4u32(<4 x float> %x, <4 x i32>* nocapture %y) nounwind {
+entry:
+ %0 = load <4 x float>* @cte_float, align 16
+ %mul = fmul <4 x float> %0, %x
+ %1 = fptoui <4 x float> %mul to <4 x i32>
+ store <4 x i32> %1, <4 x i32>* %y, align 16
+ ret void
+}
+;CHECK: v4f32_to_v4u32:
+;CHECK: vctuxs {{[0-9]+}}, {{[0-9]+}}, 0
+
+
+define void @v4i32_to_v4f32(<4 x i32> %x, <4 x float>* nocapture %y) nounwind {
+entry:
+ %0 = load <4 x i32>* @cte_int, align 16
+ %mul = mul <4 x i32> %0, %x
+ %1 = sitofp <4 x i32> %mul to <4 x float>
+ store <4 x float> %1, <4 x float>* %y, align 16
+ ret void
+}
+;CHECK: v4i32_to_v4f32:
+;CHECK: vcfsx {{[0-9]+}}, {{[0-9]+}}, 0
+
+
+define void @v4u32_to_v4f32(<4 x i32> %x, <4 x float>* nocapture %y) nounwind {
+entry:
+ %0 = load <4 x i32>* @cte_int, align 16
+ %mul = mul <4 x i32> %0, %x
+ %1 = uitofp <4 x i32> %mul to <4 x float>
+ store <4 x float> %1, <4 x float>* %y, align 16
+ ret void
+}
+;CHECK: v4u32_to_v4f32:
+;CHECK: vcfux {{[0-9]+}}, {{[0-9]+}}, 0
Modified: llvm/branches/R600/test/CodeGen/SPARC/2011-01-11-CC.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/SPARC/2011-01-11-CC.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/CodeGen/SPARC/2011-01-11-CC.ll (original)
+++ llvm/branches/R600/test/CodeGen/SPARC/2011-01-11-CC.ll Thu Oct 11 16:28:00 2012
@@ -54,7 +54,7 @@
; V8: {{be|bne}}
; V9: test_select_dfp_icc
; V9: subcc
-; V9=NOT: {{be|bne}}
+; V9-NOT: {{be|bne}}
; V9: fmovd{{e|ne}} %icc
%0 = icmp eq i32 %a, 0
%1 = select i1 %0, double %f1, double %f2
Added: llvm/branches/R600/test/CodeGen/X86/2012-10-02-DAGCycle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/X86/2012-10-02-DAGCycle.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/X86/2012-10-02-DAGCycle.ll (added)
+++ llvm/branches/R600/test/CodeGen/X86/2012-10-02-DAGCycle.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,52 @@
+; RUN: llc -mtriple=i386-apple-macosx -relocation-model=pic < %s
+; RUN: llc -mtriple=x86_64-apple-macosx -relocation-model=pic < %s
+
+; rdar://12393897
+
+%TRp = type { i32, %TRH*, i32, i32 }
+%TRH = type { i8*, i8*, i8*, i8*, {}* }
+
+define i32 @t(%TRp* inreg %rp) nounwind optsize ssp {
+entry:
+ %handler = getelementptr inbounds %TRp* %rp, i32 0, i32 1
+ %0 = load %TRH** %handler, align 4
+ %sync = getelementptr inbounds %TRH* %0, i32 0, i32 4
+ %sync12 = load {}** %sync, align 4
+ %1 = bitcast {}* %sync12 to i32 (%TRp*)*
+ %call = tail call i32 %1(%TRp* inreg %rp) nounwind optsize
+ ret i32 %call
+}
+
+%btConeShape = type { %btConvexInternalShape, float, float, float, [3 x i32] }
+%btConvexInternalShape = type { %btConvexShape, %btVector, %btVector, float, float }
+%btConvexShape = type { %btCollisionShape }
+%btCollisionShape = type { i32 (...)**, i32, i8* }
+%btVector = type { [4 x float] }
+
+define { <2 x float>, <2 x float> } @t2(%btConeShape* %this) unnamed_addr uwtable ssp align 2 {
+entry:
+ %0 = getelementptr inbounds %btConeShape* %this, i64 0, i32 0
+ br i1 undef, label %if.then, label %if.end17
+
+if.then: ; preds = %entry
+ %vecnorm.sroa.2.8.copyload = load float* undef, align 4
+ %cmp4 = fcmp olt float undef, 0x3D10000000000000
+ %vecnorm.sroa.2.8.copyload36 = select i1 %cmp4, float -1.000000e+00, float %vecnorm.sroa.2.8.copyload
+ %call.i.i.i = tail call float @sqrtf(float 0.000000e+00) nounwind readnone
+ %div.i.i = fdiv float 1.000000e+00, %call.i.i.i
+ %mul7.i.i.i = fmul float %div.i.i, %vecnorm.sroa.2.8.copyload36
+ %1 = load float (%btConvexInternalShape*)** undef, align 8
+ %call12 = tail call float %1(%btConvexInternalShape* %0)
+ %mul7.i.i = fmul float %call12, %mul7.i.i.i
+ %retval.sroa.0.4.insert = insertelement <2 x float> zeroinitializer, float undef, i32 1
+ %add13.i = fadd float undef, %mul7.i.i
+ %retval.sroa.1.8.insert = insertelement <2 x float> undef, float %add13.i, i32 0
+ br label %if.end17
+
+if.end17: ; preds = %if.then, %entry
+ %retval.sroa.1.8.load3338 = phi <2 x float> [ %retval.sroa.1.8.insert, %if.then ], [ undef, %entry ]
+ %retval.sroa.0.0.load3137 = phi <2 x float> [ %retval.sroa.0.4.insert, %if.then ], [ undef, %entry ]
+ ret { <2 x float>, <2 x float> } undef
+}
+
+declare float @sqrtf(float) nounwind readnone
Added: llvm/branches/R600/test/CodeGen/X86/2012-10-03-DAGCycle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/X86/2012-10-03-DAGCycle.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/X86/2012-10-03-DAGCycle.ll (added)
+++ llvm/branches/R600/test/CodeGen/X86/2012-10-03-DAGCycle.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,31 @@
+; RUN: llc -mtriple=x86_64-apple-macosx -mcpu=corei7 < %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+%struct.pluto.0 = type { %struct.bar.1, %struct.hoge.368* }
+%struct.bar.1 = type { %i8* }
+%i8 = type { i8 }
+%struct.hoge.368 = type { i32, i32 }
+%struct.widget.375 = type { i32, i32, %i8*, %struct.hoge.368* }
+
+define fastcc void @bar(%struct.pluto.0* %arg) nounwind uwtable ssp align 2 {
+bb:
+ %tmp1 = alloca %struct.widget.375, align 8
+ %tmp2 = getelementptr inbounds %struct.pluto.0* %arg, i64 0, i32 1
+ %tmp3 = load %struct.hoge.368** %tmp2, align 8
+ store %struct.pluto.0* %arg, %struct.pluto.0** undef, align 8
+ %tmp = getelementptr inbounds %struct.widget.375* %tmp1, i64 0, i32 2
+ %tmp4 = getelementptr %struct.pluto.0* %arg, i64 0, i32 0, i32 0
+ %tmp5 = load %i8** %tmp4, align 8
+ store %i8* %tmp5, %i8** %tmp, align 8
+ %tmp6 = getelementptr inbounds %struct.widget.375* %tmp1, i64 0, i32 3
+ store %struct.hoge.368* %tmp3, %struct.hoge.368** %tmp6, align 8
+ br i1 undef, label %bb8, label %bb7
+
+bb7: ; preds = %bb
+ unreachable
+
+bb8: ; preds = %bb
+ unreachable
+}
Added: llvm/branches/R600/test/CodeGen/X86/MergeConsecutiveStores.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/X86/MergeConsecutiveStores.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/X86/MergeConsecutiveStores.ll (added)
+++ llvm/branches/R600/test/CodeGen/X86/MergeConsecutiveStores.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,305 @@
+; RUN: llc -march=x86-64 -mcpu=corei7 -mattr=+avx < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+%struct.A = type { i8, i8, i8, i8, i8, i8, i8, i8 }
+%struct.B = type { i32, i32, i32, i32, i32, i32, i32, i32 }
+
+; CHECK: merge_const_store
+; save 1,2,3 ... as one big integer.
+; CHECK: movabsq $578437695752307201
+; CHECK: ret
+define void @merge_const_store(i32 %count, %struct.A* nocapture %p) nounwind uwtable noinline ssp {
+ %1 = icmp sgt i32 %count, 0
+ br i1 %1, label %.lr.ph, label %._crit_edge
+.lr.ph:
+ %i.02 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ]
+ %.01 = phi %struct.A* [ %11, %.lr.ph ], [ %p, %0 ]
+ %2 = getelementptr inbounds %struct.A* %.01, i64 0, i32 0
+ store i8 1, i8* %2, align 1
+ %3 = getelementptr inbounds %struct.A* %.01, i64 0, i32 1
+ store i8 2, i8* %3, align 1
+ %4 = getelementptr inbounds %struct.A* %.01, i64 0, i32 2
+ store i8 3, i8* %4, align 1
+ %5 = getelementptr inbounds %struct.A* %.01, i64 0, i32 3
+ store i8 4, i8* %5, align 1
+ %6 = getelementptr inbounds %struct.A* %.01, i64 0, i32 4
+ store i8 5, i8* %6, align 1
+ %7 = getelementptr inbounds %struct.A* %.01, i64 0, i32 5
+ store i8 6, i8* %7, align 1
+ %8 = getelementptr inbounds %struct.A* %.01, i64 0, i32 6
+ store i8 7, i8* %8, align 1
+ %9 = getelementptr inbounds %struct.A* %.01, i64 0, i32 7
+ store i8 8, i8* %9, align 1
+ %10 = add nsw i32 %i.02, 1
+ %11 = getelementptr inbounds %struct.A* %.01, i64 1
+ %exitcond = icmp eq i32 %10, %count
+ br i1 %exitcond, label %._crit_edge, label %.lr.ph
+._crit_edge:
+ ret void
+}
+
+; Move the constants using a single vector store.
+; CHECK: merge_const_store_vec
+; CHECK: vmovups %ymm0, (%rsi)
+; CHECK: ret
+define void @merge_const_store_vec(i32 %count, %struct.B* nocapture %p) nounwind uwtable noinline ssp {
+ %1 = icmp sgt i32 %count, 0
+ br i1 %1, label %.lr.ph, label %._crit_edge
+.lr.ph:
+ %i.02 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ]
+ %.01 = phi %struct.B* [ %11, %.lr.ph ], [ %p, %0 ]
+ %2 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0
+ store i32 0, i32* %2, align 4
+ %3 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1
+ store i32 0, i32* %3, align 4
+ %4 = getelementptr inbounds %struct.B* %.01, i64 0, i32 2
+ store i32 0, i32* %4, align 4
+ %5 = getelementptr inbounds %struct.B* %.01, i64 0, i32 3
+ store i32 0, i32* %5, align 4
+ %6 = getelementptr inbounds %struct.B* %.01, i64 0, i32 4
+ store i32 0, i32* %6, align 4
+ %7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 5
+ store i32 0, i32* %7, align 4
+ %8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 6
+ store i32 0, i32* %8, align 4
+ %9 = getelementptr inbounds %struct.B* %.01, i64 0, i32 7
+ store i32 0, i32* %9, align 4
+ %10 = add nsw i32 %i.02, 1
+ %11 = getelementptr inbounds %struct.B* %.01, i64 1
+ %exitcond = icmp eq i32 %10, %count
+ br i1 %exitcond, label %._crit_edge, label %.lr.ph
+._crit_edge:
+ ret void
+}
+
+; Move the first 4 constants as a single vector. Move the rest as scalars.
+; CHECK: merge_nonconst_store
+; CHECK: movl $67305985
+; CHECK: movb
+; CHECK: movb
+; CHECK: movb
+; CHECK: movb
+; CHECK: ret
+define void @merge_nonconst_store(i32 %count, i8 %zz, %struct.A* nocapture %p) nounwind uwtable noinline ssp {
+ %1 = icmp sgt i32 %count, 0
+ br i1 %1, label %.lr.ph, label %._crit_edge
+.lr.ph:
+ %i.02 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ]
+ %.01 = phi %struct.A* [ %11, %.lr.ph ], [ %p, %0 ]
+ %2 = getelementptr inbounds %struct.A* %.01, i64 0, i32 0
+ store i8 1, i8* %2, align 1
+ %3 = getelementptr inbounds %struct.A* %.01, i64 0, i32 1
+ store i8 2, i8* %3, align 1
+ %4 = getelementptr inbounds %struct.A* %.01, i64 0, i32 2
+ store i8 3, i8* %4, align 1
+ %5 = getelementptr inbounds %struct.A* %.01, i64 0, i32 3
+ store i8 4, i8* %5, align 1
+ %6 = getelementptr inbounds %struct.A* %.01, i64 0, i32 4
+ store i8 %zz, i8* %6, align 1 ; <----------- Not a const;
+ %7 = getelementptr inbounds %struct.A* %.01, i64 0, i32 5
+ store i8 6, i8* %7, align 1
+ %8 = getelementptr inbounds %struct.A* %.01, i64 0, i32 6
+ store i8 7, i8* %8, align 1
+ %9 = getelementptr inbounds %struct.A* %.01, i64 0, i32 7
+ store i8 8, i8* %9, align 1
+ %10 = add nsw i32 %i.02, 1
+ %11 = getelementptr inbounds %struct.A* %.01, i64 1
+ %exitcond = icmp eq i32 %10, %count
+ br i1 %exitcond, label %._crit_edge, label %.lr.ph
+._crit_edge:
+ ret void
+}
+
+
+;CHECK: merge_loads_i16
+; load:
+;CHECK: movw
+; store:
+;CHECK: movw
+;CHECK: ret
+define void @merge_loads_i16(i32 %count, %struct.A* noalias nocapture %q, %struct.A* noalias nocapture %p) nounwind uwtable noinline ssp {
+ %1 = icmp sgt i32 %count, 0
+ br i1 %1, label %.lr.ph, label %._crit_edge
+
+.lr.ph: ; preds = %0
+ %2 = getelementptr inbounds %struct.A* %q, i64 0, i32 0
+ %3 = getelementptr inbounds %struct.A* %q, i64 0, i32 1
+ br label %4
+
+; <label>:4 ; preds = %4, %.lr.ph
+ %i.02 = phi i32 [ 0, %.lr.ph ], [ %9, %4 ]
+ %.01 = phi %struct.A* [ %p, %.lr.ph ], [ %10, %4 ]
+ %5 = load i8* %2, align 1
+ %6 = load i8* %3, align 1
+ %7 = getelementptr inbounds %struct.A* %.01, i64 0, i32 0
+ store i8 %5, i8* %7, align 1
+ %8 = getelementptr inbounds %struct.A* %.01, i64 0, i32 1
+ store i8 %6, i8* %8, align 1
+ %9 = add nsw i32 %i.02, 1
+ %10 = getelementptr inbounds %struct.A* %.01, i64 1
+ %exitcond = icmp eq i32 %9, %count
+ br i1 %exitcond, label %._crit_edge, label %4
+
+._crit_edge: ; preds = %4, %0
+ ret void
+}
+
+; The loads and the stores are interleved. Can't merge them.
+;CHECK: no_merge_loads
+;CHECK: movb
+;CHECK: movb
+;CHECK: movb
+;CHECK: movb
+;CHECK: ret
+define void @no_merge_loads(i32 %count, %struct.A* noalias nocapture %q, %struct.A* noalias nocapture %p) nounwind uwtable noinline ssp {
+ %1 = icmp sgt i32 %count, 0
+ br i1 %1, label %.lr.ph, label %._crit_edge
+
+.lr.ph: ; preds = %0
+ %2 = getelementptr inbounds %struct.A* %q, i64 0, i32 0
+ %3 = getelementptr inbounds %struct.A* %q, i64 0, i32 1
+ br label %a4
+
+a4: ; preds = %4, %.lr.ph
+ %i.02 = phi i32 [ 0, %.lr.ph ], [ %a9, %a4 ]
+ %.01 = phi %struct.A* [ %p, %.lr.ph ], [ %a10, %a4 ]
+ %a5 = load i8* %2, align 1
+ %a7 = getelementptr inbounds %struct.A* %.01, i64 0, i32 0
+ store i8 %a5, i8* %a7, align 1
+ %a8 = getelementptr inbounds %struct.A* %.01, i64 0, i32 1
+ %a6 = load i8* %3, align 1
+ store i8 %a6, i8* %a8, align 1
+ %a9 = add nsw i32 %i.02, 1
+ %a10 = getelementptr inbounds %struct.A* %.01, i64 1
+ %exitcond = icmp eq i32 %a9, %count
+ br i1 %exitcond, label %._crit_edge, label %a4
+
+._crit_edge: ; preds = %4, %0
+ ret void
+}
+
+
+;CHECK: merge_loads_integer
+; load:
+;CHECK: movq
+; store:
+;CHECK: movq
+;CHECK: ret
+define void @merge_loads_integer(i32 %count, %struct.B* noalias nocapture %q, %struct.B* noalias nocapture %p) nounwind uwtable noinline ssp {
+ %1 = icmp sgt i32 %count, 0
+ br i1 %1, label %.lr.ph, label %._crit_edge
+
+.lr.ph: ; preds = %0
+ %2 = getelementptr inbounds %struct.B* %q, i64 0, i32 0
+ %3 = getelementptr inbounds %struct.B* %q, i64 0, i32 1
+ br label %4
+
+; <label>:4 ; preds = %4, %.lr.ph
+ %i.02 = phi i32 [ 0, %.lr.ph ], [ %9, %4 ]
+ %.01 = phi %struct.B* [ %p, %.lr.ph ], [ %10, %4 ]
+ %5 = load i32* %2
+ %6 = load i32* %3
+ %7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0
+ store i32 %5, i32* %7
+ %8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1
+ store i32 %6, i32* %8
+ %9 = add nsw i32 %i.02, 1
+ %10 = getelementptr inbounds %struct.B* %.01, i64 1
+ %exitcond = icmp eq i32 %9, %count
+ br i1 %exitcond, label %._crit_edge, label %4
+
+._crit_edge: ; preds = %4, %0
+ ret void
+}
+
+
+;CHECK: merge_loads_vector
+; load:
+;CHECK: movups
+; store:
+;CHECK: movups
+;CHECK: ret
+define void @merge_loads_vector(i32 %count, %struct.B* noalias nocapture %q, %struct.B* noalias nocapture %p) nounwind uwtable noinline ssp {
+ %a1 = icmp sgt i32 %count, 0
+ br i1 %a1, label %.lr.ph, label %._crit_edge
+
+.lr.ph: ; preds = %0
+ %a2 = getelementptr inbounds %struct.B* %q, i64 0, i32 0
+ %a3 = getelementptr inbounds %struct.B* %q, i64 0, i32 1
+ %a4 = getelementptr inbounds %struct.B* %q, i64 0, i32 2
+ %a5 = getelementptr inbounds %struct.B* %q, i64 0, i32 3
+ br label %block4
+
+block4: ; preds = %4, %.lr.ph
+ %i.02 = phi i32 [ 0, %.lr.ph ], [ %c9, %block4 ]
+ %.01 = phi %struct.B* [ %p, %.lr.ph ], [ %c10, %block4 ]
+ %a7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0
+ %a8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1
+ %a9 = getelementptr inbounds %struct.B* %.01, i64 0, i32 2
+ %a10 = getelementptr inbounds %struct.B* %.01, i64 0, i32 3
+ %b1 = load i32* %a2
+ %b2 = load i32* %a3
+ %b3 = load i32* %a4
+ %b4 = load i32* %a5
+ store i32 %b1, i32* %a7
+ store i32 %b2, i32* %a8
+ store i32 %b3, i32* %a9
+ store i32 %b4, i32* %a10
+ %c9 = add nsw i32 %i.02, 1
+ %c10 = getelementptr inbounds %struct.B* %.01, i64 1
+ %exitcond = icmp eq i32 %c9, %count
+ br i1 %exitcond, label %._crit_edge, label %block4
+
+._crit_edge: ; preds = %4, %0
+ ret void
+}
+
+;CHECK: merge_loads_no_align
+; load:
+;CHECK: movl
+;CHECK: movl
+;CHECK: movl
+;CHECK: movl
+; store:
+;CHECK: movl
+;CHECK: movl
+;CHECK: movl
+;CHECK: movl
+;CHECK: ret
+define void @merge_loads_no_align(i32 %count, %struct.B* noalias nocapture %q, %struct.B* noalias nocapture %p) nounwind uwtable noinline ssp {
+ %a1 = icmp sgt i32 %count, 0
+ br i1 %a1, label %.lr.ph, label %._crit_edge
+
+.lr.ph: ; preds = %0
+ %a2 = getelementptr inbounds %struct.B* %q, i64 0, i32 0
+ %a3 = getelementptr inbounds %struct.B* %q, i64 0, i32 1
+ %a4 = getelementptr inbounds %struct.B* %q, i64 0, i32 2
+ %a5 = getelementptr inbounds %struct.B* %q, i64 0, i32 3
+ br label %block4
+
+block4: ; preds = %4, %.lr.ph
+ %i.02 = phi i32 [ 0, %.lr.ph ], [ %c9, %block4 ]
+ %.01 = phi %struct.B* [ %p, %.lr.ph ], [ %c10, %block4 ]
+ %a7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0
+ %a8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1
+ %a9 = getelementptr inbounds %struct.B* %.01, i64 0, i32 2
+ %a10 = getelementptr inbounds %struct.B* %.01, i64 0, i32 3
+ %b1 = load i32* %a2, align 1
+ %b2 = load i32* %a3, align 1
+ %b3 = load i32* %a4, align 1
+ %b4 = load i32* %a5, align 1
+ store i32 %b1, i32* %a7, align 1
+ store i32 %b2, i32* %a8, align 1
+ store i32 %b3, i32* %a9, align 1
+ store i32 %b4, i32* %a10, align 1
+ %c9 = add nsw i32 %i.02, 1
+ %c10 = getelementptr inbounds %struct.B* %.01, i64 1
+ %exitcond = icmp eq i32 %c9, %count
+ br i1 %exitcond, label %._crit_edge, label %block4
+
+._crit_edge: ; preds = %4, %0
+ ret void
+}
+
Modified: llvm/branches/R600/test/CodeGen/X86/atomic-minmax-i6432.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/X86/atomic-minmax-i6432.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/CodeGen/X86/atomic-minmax-i6432.ll (original)
+++ llvm/branches/R600/test/CodeGen/X86/atomic-minmax-i6432.ll Thu Oct 11 16:28:00 2012
@@ -1,51 +1,67 @@
-; RUN: llc -march=x86 -mattr=+cmov -mtriple=i386-pc-linux < %s | FileCheck %s
+; RUN: llc -march=x86 -mattr=+cmov -mtriple=i386-pc-linux < %s | FileCheck %s -check-prefix=LINUX
+; RUN: llc -march=x86 -mtriple=i386-macosx -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC
+
@sc64 = external global i64
define void @atomic_maxmin_i6432() {
-; CHECK: atomic_maxmin_i6432
+; LINUX: atomic_maxmin_i6432
%1 = atomicrmw max i64* @sc64, i64 5 acquire
-; CHECK: [[LABEL:.LBB[0-9]+_[0-9]+]]
-; CHECK: cmpl
-; CHECK: setl
-; CHECK: cmpl
-; CHECK: setl
-; CHECK: cmovne
-; CHECK: cmovne
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b
-; CHECK: jne [[LABEL]]
+; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]]
+; LINUX: cmpl
+; LINUX: setl
+; LINUX: cmpl
+; LINUX: setl
+; LINUX: cmovne
+; LINUX: cmovne
+; LINUX: lock
+; LINUX-NEXT: cmpxchg8b
+; LINUX: jne [[LABEL]]
%2 = atomicrmw min i64* @sc64, i64 6 acquire
-; CHECK: [[LABEL:.LBB[0-9]+_[0-9]+]]
-; CHECK: cmpl
-; CHECK: setg
-; CHECK: cmpl
-; CHECK: setg
-; CHECK: cmovne
-; CHECK: cmovne
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b
-; CHECK: jne [[LABEL]]
+; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]]
+; LINUX: cmpl
+; LINUX: setg
+; LINUX: cmpl
+; LINUX: setg
+; LINUX: cmovne
+; LINUX: cmovne
+; LINUX: lock
+; LINUX-NEXT: cmpxchg8b
+; LINUX: jne [[LABEL]]
%3 = atomicrmw umax i64* @sc64, i64 7 acquire
-; CHECK: [[LABEL:.LBB[0-9]+_[0-9]+]]
-; CHECK: cmpl
-; CHECK: setb
-; CHECK: cmpl
-; CHECK: setb
-; CHECK: cmovne
-; CHECK: cmovne
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b
-; CHECK: jne [[LABEL]]
+; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]]
+; LINUX: cmpl
+; LINUX: setb
+; LINUX: cmpl
+; LINUX: setb
+; LINUX: cmovne
+; LINUX: cmovne
+; LINUX: lock
+; LINUX-NEXT: cmpxchg8b
+; LINUX: jne [[LABEL]]
%4 = atomicrmw umin i64* @sc64, i64 8 acquire
-; CHECK: [[LABEL:.LBB[0-9]+_[0-9]+]]
-; CHECK: cmpl
-; CHECK: seta
-; CHECK: cmpl
-; CHECK: seta
-; CHECK: cmovne
-; CHECK: cmovne
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b
-; CHECK: jne [[LABEL]]
+; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]]
+; LINUX: cmpl
+; LINUX: seta
+; LINUX: cmpl
+; LINUX: seta
+; LINUX: cmovne
+; LINUX: cmovne
+; LINUX: lock
+; LINUX-NEXT: cmpxchg8b
+; LINUX: jne [[LABEL]]
+ ret void
+}
+
+; rdar://12453106
+ at id = internal global i64 0, align 8
+
+define void @tf_bug(i8* %ptr) nounwind {
+; PIC: tf_bug:
+; PIC: movl _id-L1$pb(
+; PIC: movl (_id-L1$pb)+4(
+ %tmp1 = atomicrmw add i64* @id, i64 1 seq_cst
+ %tmp2 = add i64 %tmp1, 1
+ %tmp3 = bitcast i8* %ptr to i64*
+ store i64 %tmp2, i64* %tmp3, align 4
ret void
}
Added: llvm/branches/R600/test/CodeGen/X86/cmov-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/X86/cmov-fp.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/CodeGen/X86/cmov-fp.ll (added)
+++ llvm/branches/R600/test/CodeGen/X86/cmov-fp.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,451 @@
+; RUN: llc -march x86 -mcpu pentium4 < %s | FileCheck %s -check-prefix=SSE
+; RUN: llc -march x86 -mcpu pentium3 < %s | FileCheck %s -check-prefix=NOSSE2
+; RUN: llc -march x86 -mcpu pentium2 < %s | FileCheck %s -check-prefix=NOSSE1
+; RUN: llc -march x86 -mcpu pentium < %s | FileCheck %s -check-prefix=NOCMOV
+; PR14035
+
+define double @test1(i32 %a, i32 %b, double %x) nounwind {
+ %cmp = icmp ugt i32 %a, %b
+ %sel = select i1 %cmp, double 99.0, double %x
+ ret double %sel
+
+; SSE: test1:
+; SSE: movsd
+
+; NOSSE2: test1:
+; NOSSE2: fcmovnbe
+
+; NOSSE1: test1:
+; NOSSE1: fcmovnbe
+
+; NOCMOV: test1:
+; NOCMOV: fstp
+
+}
+
+define double @test2(i32 %a, i32 %b, double %x) nounwind {
+ %cmp = icmp uge i32 %a, %b
+ %sel = select i1 %cmp, double 99.0, double %x
+ ret double %sel
+
+; SSE: test2:
+; SSE: movsd
+
+; NOSSE2: test2:
+; NOSSE2: fcmovnb
+
+; NOSSE1: test2:
+; NOSSE1: fcmovnb
+
+; NOCMOV: test2:
+; NOCMOV: fstp
+}
+
+define double @test3(i32 %a, i32 %b, double %x) nounwind {
+ %cmp = icmp ult i32 %a, %b
+ %sel = select i1 %cmp, double 99.0, double %x
+ ret double %sel
+
+; SSE: test3:
+; SSE: movsd
+
+; NOSSE2: test3:
+; NOSSE2: fcmovb
+
+; NOSSE1: test3:
+; NOSSE1: fcmovb
+
+; NOCMOV: test3:
+; NOCMOV: fstp
+}
+
+define double @test4(i32 %a, i32 %b, double %x) nounwind {
+ %cmp = icmp ule i32 %a, %b
+ %sel = select i1 %cmp, double 99.0, double %x
+ ret double %sel
+
+; SSE: test4:
+; SSE: movsd
+
+; NOSSE2: test4:
+; NOSSE2: fcmovbe
+
+; NOSSE1: test4:
+; NOSSE1: fcmovbe
+
+; NOCMOV: test4:
+; NOCMOV: fstp
+}
+
+define double @test5(i32 %a, i32 %b, double %x) nounwind {
+ %cmp = icmp sgt i32 %a, %b
+ %sel = select i1 %cmp, double 99.0, double %x
+ ret double %sel
+
+; SSE: test5:
+; SSE: movsd
+
+; NOSSE2: test5:
+; NOSSE2: fstp
+
+; NOSSE1: test5:
+; NOSSE1: fstp
+
+; NOCMOV: test5:
+; NOCMOV: fstp
+}
+
+define double @test6(i32 %a, i32 %b, double %x) nounwind {
+ %cmp = icmp sge i32 %a, %b
+ %sel = select i1 %cmp, double 99.0, double %x
+ ret double %sel
+
+; SSE: test6:
+; SSE: movsd
+
+; NOSSE2: test6:
+; NOSSE2: fstp
+
+; NOSSE1: test6:
+; NOSSE1: fstp
+
+; NOCMOV: test6:
+; NOCMOV: fstp
+}
+
+define double @test7(i32 %a, i32 %b, double %x) nounwind {
+ %cmp = icmp slt i32 %a, %b
+ %sel = select i1 %cmp, double 99.0, double %x
+ ret double %sel
+
+; SSE: test7:
+; SSE: movsd
+
+; NOSSE2: test7:
+; NOSSE2: fstp
+
+; NOSSE1: test7:
+; NOSSE1: fstp
+
+; NOCMOV: test7:
+; NOCMOV: fstp
+}
+
+define double @test8(i32 %a, i32 %b, double %x) nounwind {
+ %cmp = icmp sle i32 %a, %b
+ %sel = select i1 %cmp, double 99.0, double %x
+ ret double %sel
+
+; SSE: test8:
+; SSE: movsd
+
+; NOSSE2: test8:
+; NOSSE2: fstp
+
+; NOSSE1: test8:
+; NOSSE1: fstp
+
+; NOCMOV: test8:
+; NOCMOV: fstp
+}
+
+define float @test9(i32 %a, i32 %b, float %x) nounwind {
+ %cmp = icmp ugt i32 %a, %b
+ %sel = select i1 %cmp, float 99.0, float %x
+ ret float %sel
+
+; SSE: test9:
+; SSE: movss
+
+; NOSSE2: test9:
+; NOSSE2: movss
+
+; NOSSE1: test9:
+; NOSSE1: fcmovnbe
+
+; NOCMOV: test9:
+; NOCMOV: fstp
+}
+
+define float @test10(i32 %a, i32 %b, float %x) nounwind {
+ %cmp = icmp uge i32 %a, %b
+ %sel = select i1 %cmp, float 99.0, float %x
+ ret float %sel
+
+; SSE: test10:
+; SSE: movss
+
+; NOSSE2: test10:
+; NOSSE2: movss
+
+; NOSSE1: test10:
+; NOSSE1: fcmovnb
+
+; NOCMOV: test10:
+; NOCMOV: fstp
+}
+
+define float @test11(i32 %a, i32 %b, float %x) nounwind {
+ %cmp = icmp ult i32 %a, %b
+ %sel = select i1 %cmp, float 99.0, float %x
+ ret float %sel
+
+; SSE: test11:
+; SSE: movss
+
+; NOSSE2: test11:
+; NOSSE2: movss
+
+; NOSSE1: test11:
+; NOSSE1: fcmovb
+
+; NOCMOV: test11:
+; NOCMOV: fstp
+}
+
+define float @test12(i32 %a, i32 %b, float %x) nounwind {
+ %cmp = icmp ule i32 %a, %b
+ %sel = select i1 %cmp, float 99.0, float %x
+ ret float %sel
+
+; SSE: test12:
+; SSE: movss
+
+; NOSSE2: test12:
+; NOSSE2: movss
+
+; NOSSE1: test12:
+; NOSSE1: fcmovbe
+
+; NOCMOV: test12:
+; NOCMOV: fstp
+}
+
+define float @test13(i32 %a, i32 %b, float %x) nounwind {
+ %cmp = icmp sgt i32 %a, %b
+ %sel = select i1 %cmp, float 99.0, float %x
+ ret float %sel
+
+; SSE: test13:
+; SSE: movss
+
+; NOSSE2: test13:
+; NOSSE2: movss
+
+; NOSSE1: test13:
+; NOSSE1: fstp
+
+; NOCMOV: test13:
+; NOCMOV: fstp
+}
+
+define float @test14(i32 %a, i32 %b, float %x) nounwind {
+ %cmp = icmp sge i32 %a, %b
+ %sel = select i1 %cmp, float 99.0, float %x
+ ret float %sel
+
+; SSE: test14:
+; SSE: movss
+
+; NOSSE2: test14:
+; NOSSE2: movss
+
+; NOSSE1: test14:
+; NOSSE1: fstp
+
+; NOCMOV: test14:
+; NOCMOV: fstp
+}
+
+define float @test15(i32 %a, i32 %b, float %x) nounwind {
+ %cmp = icmp slt i32 %a, %b
+ %sel = select i1 %cmp, float 99.0, float %x
+ ret float %sel
+
+; SSE: test15:
+; SSE: movss
+
+; NOSSE2: test15:
+; NOSSE2: movss
+
+; NOSSE1: test15:
+; NOSSE1: fstp
+
+; NOCMOV: test15:
+; NOCMOV: fstp
+}
+
+define float @test16(i32 %a, i32 %b, float %x) nounwind {
+ %cmp = icmp sle i32 %a, %b
+ %sel = select i1 %cmp, float 99.0, float %x
+ ret float %sel
+
+; SSE: test16:
+; SSE: movss
+
+; NOSSE2: test16:
+; NOSSE2: movss
+
+; NOSSE1: test16:
+; NOSSE1: fstp
+
+; NOCMOV: test16:
+; NOCMOV: fstp
+}
+
+define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind {
+ %cmp = icmp ugt i32 %a, %b
+ %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
+ ret x86_fp80 %sel
+
+; SSE: test17:
+; SSE: fcmovnbe
+
+; NOSSE2: test17:
+; NOSSE2: fcmovnbe
+
+; NOSSE1: test17:
+; NOSSE1: fcmovnbe
+
+; NOCMOV: test17:
+; NOCMOV: fstp
+}
+
+define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind {
+ %cmp = icmp uge i32 %a, %b
+ %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
+ ret x86_fp80 %sel
+
+; SSE: test18:
+; SSE: fcmovnb
+
+; NOSSE2: test18:
+; NOSSE2: fcmovnb
+
+; NOSSE1: test18:
+; NOSSE1: fcmovnb
+
+; NOCMOV: test18:
+; NOCMOV: fstp
+}
+
+define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind {
+ %cmp = icmp ult i32 %a, %b
+ %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
+ ret x86_fp80 %sel
+
+; SSE: test19:
+; SSE: fcmovb
+
+; NOSSE2: test19:
+; NOSSE2: fcmovb
+
+; NOSSE1: test19:
+; NOSSE1: fcmovb
+
+; NOCMOV: test19:
+; NOCMOV: fstp
+}
+
+define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind {
+ %cmp = icmp ule i32 %a, %b
+ %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
+ ret x86_fp80 %sel
+
+; SSE: test20:
+; SSE: fcmovbe
+
+; NOSSE2: test20:
+; NOSSE2: fcmovbe
+
+; NOSSE1: test20:
+; NOSSE1: fcmovbe
+
+; NOCMOV: test20:
+; NOCMOV: fstp
+}
+
+define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
+ %cmp = icmp sgt i32 %a, %b
+ %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
+ ret x86_fp80 %sel
+
+; We don't emit a branch for fp80, why?
+; SSE: test21:
+; SSE: testb
+; SSE: fcmovne
+
+; NOSSE2: test21:
+; NOSSE2: testb
+; NOSSE2: fcmovne
+
+; NOSSE1: test21:
+; NOSSE1: testb
+; NOSSE1: fcmovne
+
+; NOCMOV: test21:
+; NOCMOV: fstp
+}
+
+define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind {
+ %cmp = icmp sge i32 %a, %b
+ %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
+ ret x86_fp80 %sel
+
+; SSE: test22:
+; SSE: testb
+; SSE: fcmovne
+
+; NOSSE2: test22:
+; NOSSE2: testb
+; NOSSE2: fcmovne
+
+; NOSSE1: test22:
+; NOSSE1: testb
+; NOSSE1: fcmovne
+
+; NOCMOV: test22:
+; NOCMOV: fstp
+}
+
+define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind {
+ %cmp = icmp slt i32 %a, %b
+ %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
+ ret x86_fp80 %sel
+
+; SSE: test23:
+; SSE: testb
+; SSE: fcmovne
+
+; NOSSE2: test23:
+; NOSSE2: testb
+; NOSSE2: fcmovne
+
+; NOSSE1: test23:
+; NOSSE1: testb
+; NOSSE1: fcmovne
+
+; NOCMOV: test23:
+; NOCMOV: fstp
+}
+
+define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind {
+ %cmp = icmp sle i32 %a, %b
+ %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
+ ret x86_fp80 %sel
+
+; SSE: test24:
+; SSE: testb
+; SSE: fcmovne
+
+; NOSSE2: test24:
+; NOSSE2: testb
+; NOSSE2: fcmovne
+
+; NOSSE1: test24:
+; NOSSE1: testb
+; NOSSE1: fcmovne
+
+; NOCMOV: test24:
+; NOCMOV: fstp
+}
Modified: llvm/branches/R600/test/CodeGen/X86/early-ifcvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/X86/early-ifcvt.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/CodeGen/X86/early-ifcvt.ll (original)
+++ llvm/branches/R600/test/CodeGen/X86/early-ifcvt.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: llc < %s -enable-early-ifcvt -stress-early-ifcvt | FileCheck %s
+; RUN: llc < %s -x86-early-ifcvt -stress-early-ifcvt | FileCheck %s
target triple = "x86_64-apple-macosx10.8.0"
; CHECK: mm2
@@ -67,3 +67,78 @@
}
declare void @fprintf(...) nounwind
+
+; CHECK: BZ2_decompress
+; This test case contains irreducible control flow, so MachineLoopInfo doesn't
+; recognize the cycle in the CFG. This would confuse MachineTraceMetrics.
+define void @BZ2_decompress(i8* %s) nounwind ssp {
+entry:
+ switch i32 undef, label %sw.default [
+ i32 39, label %if.end.sw.bb2050_crit_edge
+ i32 36, label %sw.bb1788
+ i32 37, label %if.end.sw.bb1855_crit_edge
+ i32 40, label %sw.bb2409
+ i32 38, label %sw.bb1983
+ i32 44, label %if.end.sw.bb3058_crit_edge
+ ]
+
+if.end.sw.bb3058_crit_edge: ; preds = %entry
+ br label %save_state_and_return
+
+if.end.sw.bb1855_crit_edge: ; preds = %entry
+ br label %save_state_and_return
+
+if.end.sw.bb2050_crit_edge: ; preds = %entry
+ br label %sw.bb2050
+
+sw.bb1788: ; preds = %entry
+ br label %save_state_and_return
+
+sw.bb1983: ; preds = %entry
+ br i1 undef, label %save_state_and_return, label %if.then1990
+
+if.then1990: ; preds = %sw.bb1983
+ br label %while.body2038
+
+while.body2038: ; preds = %sw.bb2050, %if.then1990
+ %groupPos.8 = phi i32 [ 0, %if.then1990 ], [ %groupPos.9, %sw.bb2050 ]
+ br i1 undef, label %save_state_and_return, label %if.end2042
+
+if.end2042: ; preds = %while.body2038
+ br i1 undef, label %if.end2048, label %while.end2104
+
+if.end2048: ; preds = %if.end2042
+ %bsLive2054.pre = getelementptr inbounds i8* %s, i32 8
+ br label %sw.bb2050
+
+sw.bb2050: ; preds = %if.end2048, %if.end.sw.bb2050_crit_edge
+ %groupPos.9 = phi i32 [ 0, %if.end.sw.bb2050_crit_edge ], [ %groupPos.8, %if.end2048 ]
+ %and2064 = and i32 undef, 1
+ br label %while.body2038
+
+while.end2104: ; preds = %if.end2042
+ br i1 undef, label %save_state_and_return, label %if.end2117
+
+if.end2117: ; preds = %while.end2104
+ br i1 undef, label %while.body2161.lr.ph, label %while.body2145.lr.ph
+
+while.body2145.lr.ph: ; preds = %if.end2117
+ br label %save_state_and_return
+
+while.body2161.lr.ph: ; preds = %if.end2117
+ br label %save_state_and_return
+
+sw.bb2409: ; preds = %entry
+ br label %save_state_and_return
+
+sw.default: ; preds = %entry
+ call void @BZ2_bz__AssertH__fail() nounwind
+ br label %save_state_and_return
+
+save_state_and_return:
+ %groupPos.14 = phi i32 [ 0, %sw.default ], [ %groupPos.8, %while.body2038 ], [ %groupPos.8, %while.end2104 ], [ 0, %if.end.sw.bb3058_crit_edge ], [ 0, %if.end.sw.bb1855_crit_edge ], [ %groupPos.8, %while.body2161.lr.ph ], [ %groupPos.8, %while.body2145.lr.ph ], [ 0, %sw.bb2409 ], [ 0, %sw.bb1788 ], [ 0, %sw.bb1983 ]
+ store i32 %groupPos.14, i32* undef, align 4
+ ret void
+}
+
+declare void @BZ2_bz__AssertH__fail()
Modified: llvm/branches/R600/test/CodeGen/X86/fast-isel-x86-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/X86/fast-isel-x86-64.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/CodeGen/X86/fast-isel-x86-64.ll (original)
+++ llvm/branches/R600/test/CodeGen/X86/fast-isel-x86-64.ll Thu Oct 11 16:28:00 2012
@@ -291,3 +291,16 @@
}
declare void @foo22(i32)
+
+; PR13563
+define void @test23(i8* noalias sret %result) {
+ %a = alloca i8
+ %b = call i8* @foo23()
+ ret void
+; CHECK: test23:
+; CHECK: call
+; CHECK: movq %rdi, %rax
+; CHECK: ret
+}
+
+declare i8* @foo23()
Modified: llvm/branches/R600/test/CodeGen/X86/ms-inline-asm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/X86/ms-inline-asm.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/CodeGen/X86/ms-inline-asm.ll (original)
+++ llvm/branches/R600/test/CodeGen/X86/ms-inline-asm.ll Thu Oct 11 16:28:00 2012
@@ -24,3 +24,17 @@
; CHECK: .att_syntax
; CHECK: {{## InlineAsm End|#NO_APP}}
}
+
+define void @t3(i32 %V) nounwind {
+entry:
+ %V.addr = alloca i32, align 4
+ store i32 %V, i32* %V.addr, align 4
+ call void asm sideeffect inteldialect "mov eax, DWORD PTR [$0]", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %V.addr) nounwind
+ ret void
+; CHECK: t3
+; CHECK: {{## InlineAsm Start|#APP}}
+; CHECK: .intel_syntax
+; CHECK: mov eax, DWORD PTR {{[[esp]}}
+; CHECK: .att_syntax
+; CHECK: {{## InlineAsm End|#NO_APP}}
+}
Modified: llvm/branches/R600/test/CodeGen/X86/smul-with-overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/CodeGen/X86/smul-with-overflow.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/CodeGen/X86/smul-with-overflow.ll (original)
+++ llvm/branches/R600/test/CodeGen/X86/smul-with-overflow.ll Thu Oct 11 16:28:00 2012
@@ -67,3 +67,17 @@
; CHECK: mull
; CHECK-NEXT: ret
}
+
+declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone
+
+define i1 @test5() nounwind {
+entry:
+ %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903)
+ %sum = extractvalue { i63, i1 } %res, 0
+ %overflow = extractvalue { i63, i1 } %res, 1
+ ret i1 %overflow
+; Was returning false, should return true (not constant folded yet though).
+; PR13991
+; CHECK: test5:
+; CHECK-NOT: xorb
+}
Modified: llvm/branches/R600/test/DebugInfo/X86/DW_AT_byte_size.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/DebugInfo/X86/DW_AT_byte_size.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/DebugInfo/X86/DW_AT_byte_size.ll (original)
+++ llvm/branches/R600/test/DebugInfo/X86/DW_AT_byte_size.ll Thu Oct 11 16:28:00 2012
@@ -4,7 +4,8 @@
; Checks that we don't emit a size for a pointer type.
; CHECK: DW_TAG_pointer_type
; CHECK-NEXT: DW_AT_type
-; CHECK-NOT-NEXT: DW_AT_byte_size
+; CHECK-NOT: DW_AT_byte_size
+; CHECK: .debug_info contents
%struct.A = type { i32 }
Modified: llvm/branches/R600/test/DebugInfo/X86/enum-fwd-decl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/DebugInfo/X86/enum-fwd-decl.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/DebugInfo/X86/enum-fwd-decl.ll (original)
+++ llvm/branches/R600/test/DebugInfo/X86/enum-fwd-decl.ll Thu Oct 11 16:28:00 2012
@@ -5,16 +5,14 @@
!llvm.dbg.cu = !{!0}
-!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"foo.cpp", metadata !"/Users/echristo/tmp", metadata !"clang version 3.2 (trunk 157772) (llvm/trunk 157761)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !6, metadata !6, metadata !7} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"foo.cpp", metadata !"/tmp", metadata !"clang version 3.2 (trunk 165274) (llvm/trunk 165272)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3} ; [ DW_TAG_compile_unit ] [/tmp/foo.cpp] [DW_LANG_C_plus_plus]
!1 = metadata !{metadata !2}
-!2 = metadata !{metadata !3}
-!3 = metadata !{i32 786436, null, metadata !"E", metadata !4, i32 1, i64 16, i64 16, i32 0, i32 4, null, metadata !5, i32 0, i32 0} ; [ DW_TAG_enumeration_type ]
-!4 = metadata !{i32 786473, metadata !"foo.cpp", metadata !"/Users/echristo/tmp", null} ; [ DW_TAG_file_type ]
-!5 = metadata !{i32 0}
-!6 = metadata !{metadata !5}
-!7 = metadata !{metadata !8}
-!8 = metadata !{metadata !9}
-!9 = metadata !{i32 786484, i32 0, null, metadata !"e", metadata !"e", metadata !"", metadata !4, i32 2, metadata !3, i32 0, i32 1, i16* @e} ; [ DW_TAG_variable ]
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{metadata !5}
+!5 = metadata !{i32 786484, i32 0, null, metadata !"e", metadata !"e", metadata !"", metadata !6, i32 2, metadata !7, i32 0, i32 1, i16* @e} ; [ DW_TAG_variable ] [e] [line 2] [def]
+!6 = metadata !{i32 786473, metadata !"foo.cpp", metadata !"/tmp", null} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 786436, null, metadata !"E", metadata !6, i32 1, i64 16, i64 16, i32 0, i32 4, null, null, i32 0} ; [ DW_TAG_enumeration_type ] [E] [line 1, size 16, align 16, offset 0] [fwd] [from ]
; CHECK: DW_TAG_enumeration_type
; CHECK-NEXT: DW_AT_name
Added: llvm/branches/R600/test/DebugInfo/X86/prologue-stack.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/DebugInfo/X86/prologue-stack.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/DebugInfo/X86/prologue-stack.ll (added)
+++ llvm/branches/R600/test/DebugInfo/X86/prologue-stack.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,35 @@
+; RUN: llc -disable-fp-elim -O0 %s -mtriple x86_64-unknown-linux-gnu -o - | FileCheck %s
+
+; int callme(int);
+; int isel_line_test2() {
+; callme(400);
+; return 0;
+; }
+
+define i32 @isel_line_test2() nounwind uwtable {
+ ; The stack adjustment should be part of the prologue.
+ ; CHECK: isel_line_test2:
+ ; CHECK: {{subq|leaq}} {{.*}}, %rsp
+ ; CHECK: .loc 1 5 3 prologue_end
+entry:
+ %call = call i32 @callme(i32 400), !dbg !10
+ ret i32 0, !dbg !12
+}
+
+declare i32 @callme(i32)
+
+!llvm.dbg.cu = !{!0}
+
+!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"bar.c", metadata !"/usr/local/google/home/echristo/tmp", metadata !"clang version 3.2 (trunk 164980) (llvm/trunk 164979)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/bar.c] [DW_LANG_C99]
+!1 = metadata !{metadata !2}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{metadata !5}
+!5 = metadata !{i32 786478, i32 0, metadata !6, metadata !"isel_line_test2", metadata !"isel_line_test2", metadata !"", metadata !6, i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @isel_line_test2, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 4] [isel_line_test2]
+!6 = metadata !{i32 786473, metadata !"bar.c", metadata !"/usr/local/google/home/echristo/tmp", null} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = metadata !{metadata !9}
+!9 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!10 = metadata !{i32 5, i32 3, metadata !11, null}
+!11 = metadata !{i32 786443, metadata !5, i32 4, i32 1, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/bar.c]
+!12 = metadata !{i32 6, i32 3, metadata !11, null}
Modified: llvm/branches/R600/test/ExecutionEngine/2002-12-16-ArgTest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/2002-12-16-ArgTest.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/2002-12-16-ArgTest.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/2002-12-16-ArgTest.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,5 @@
; RUN: %lli %s > /dev/null
+; XFAIL: arm
@.LC0 = internal global [10 x i8] c"argc: %d\0A\00" ; <[10 x i8]*> [#uses=1]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
@.LC0 = internal global [10 x i8] c"argc: %d\0A\00" ; <[10 x i8]*> [#uses=1]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-04-ArgumentBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-04-ArgumentBug.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-04-ArgumentBug.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-04-ArgumentBug.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @foo(i32 %X, i32 %Y, double %A) {
%cond212 = fcmp une double %A, 1.000000e+00 ; <i1> [#uses=1]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-04-LoopTest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-04-LoopTest.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-04-LoopTest.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-04-LoopTest.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @main() {
call i32 @mylog( i32 4 ) ; <i32>:1 [#uses=0]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-04-PhiTest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-04-PhiTest.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-04-PhiTest.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-04-PhiTest.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @main() {
; <label>:0
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-09-SARTest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-09-SARTest.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-09-SARTest.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-09-SARTest.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
; We were accidentally inverting the signedness of right shifts. Whoops.
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-10-FUCOM.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-10-FUCOM.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-10-FUCOM.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-10-FUCOM.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @main() {
%X = fadd double 0.000000e+00, 1.000000e+00 ; <double> [#uses=1]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-15-AlignmentTest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-15-AlignmentTest.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-15-AlignmentTest.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-01-15-AlignmentTest.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @bar(i8* %X) {
; pointer should be 4 byte aligned!
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll Thu Oct 11 16:28:00 2012
@@ -1,6 +1,6 @@
; This testcase should return with an exit code of 1.
;
-; RUN: not %lli -use-mcjit %s
+; RUN: not %lli -mtriple=%mcjit_triple -use-mcjit %s
@test = global i64 0 ; <i64*> [#uses=1]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s test
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s test
declare i32 @puts(i8*)
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-05-11-PHIRegAllocBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-05-11-PHIRegAllocBug.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-05-11-PHIRegAllocBug.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-05-11-PHIRegAllocBug.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
target datalayout = "e-p:32:32"
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-06-04-bzip2-bug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-06-04-bzip2-bug.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-06-04-bzip2-bug.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-06-04-bzip2-bug.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
; Testcase distilled from 256.bzip2.
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-06-05-PHIBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-06-05-PHIBug.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-06-05-PHIBug.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-06-05-PHIBug.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
; Testcase distilled from 256.bzip2.
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-08-15-AllocaAssertion.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-08-15-AllocaAssertion.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-08-15-AllocaAssertion.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-08-15-AllocaAssertion.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
; This testcase failed to work because two variable sized allocas confused the
; local register allocator.
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
;
; Regression Test: EnvironmentTest.ll
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-08-23-RegisterAllocatePhysReg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-08-23-RegisterAllocatePhysReg.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-08-23-RegisterAllocatePhysReg.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-08-23-RegisterAllocatePhysReg.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
; This testcase exposes a bug in the local register allocator where it runs out
; of registers (due to too many overlapping live ranges), but then attempts to
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
@A = global i32 0 ; <i32*> [#uses=1]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2005-12-02-TailCallBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2005-12-02-TailCallBug.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2005-12-02-TailCallBug.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2005-12-02-TailCallBug.ll Thu Oct 11 16:28:00 2012
@@ -1,5 +1,5 @@
; PR672
-; RUN: %lli -use-mcjit %s
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s
; XFAIL: mcjit-ia32
define i32 @main() {
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit -force-interpreter %s
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -force-interpreter %s
; PR1836
define i32 @main() {
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit -force-interpreter=true %s | grep 1
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -force-interpreter=true %s | grep 1
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i686-pc-linux-gnu"
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/2010-01-15-UndefValue.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/2010-01-15-UndefValue.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/2010-01-15-UndefValue.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/2010-01-15-UndefValue.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit -force-interpreter=true %s
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -force-interpreter=true %s > /dev/null
define i32 @main() {
%a = add i32 0, undef
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/fpbitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/fpbitcast.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/fpbitcast.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/fpbitcast.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit -force-interpreter=true %s | grep 40091eb8
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -force-interpreter=true %s | grep 40091eb8
;
define i32 @test(double %x) {
entry:
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/hello.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/hello.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/hello.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/hello.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
@.LC0 = internal global [12 x i8] c"Hello World\00" ; <[12 x i8]*> [#uses=1]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/hello2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/hello2.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/hello2.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/hello2.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
@X = global i32 7 ; <i32*> [#uses=0]
@msg = internal global [13 x i8] c"Hello World\0A\00" ; <[13 x i8]*> [#uses=1]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/lit.local.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/lit.local.cfg?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/lit.local.cfg (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/lit.local.cfg Thu Oct 11 16:28:00 2012
@@ -16,5 +16,5 @@
if root.host_arch not in ['x86', 'x86_64', 'ARM', 'Mips']:
config.unsupported = True
-if root.host_os in ['Win32', 'Cygwin', 'MingW', 'Windows', 'Darwin']:
+if root.host_os in ['Darwin']:
config.unsupported = True
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/pr13727.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/pr13727.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/pr13727.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/pr13727.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit -O0 -disable-lazy-compilation=false %s
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -O0 -disable-lazy-compilation=false %s
; The intention of this test is to verify that symbols mapped to COMMON in ELF
; work as expected.
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/simplesttest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/simplesttest.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/simplesttest.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/simplesttest.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @main() {
ret i32 0
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/simpletest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/simpletest.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/simpletest.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/simpletest.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @bar() {
ret i32 0
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/stubs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/stubs.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/stubs.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/stubs.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit -disable-lazy-compilation=false %s
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -disable-lazy-compilation=false %s
define i32 @main() nounwind {
entry:
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-arith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-arith.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-arith.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-arith.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @main() {
%A = add i8 0, 12 ; <i8> [#uses=1]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-branch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-branch.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-branch.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-branch.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
; test unconditional branch
define i32 @main() {
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-call-no-external-funcs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-call-no-external-funcs.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-call-no-external-funcs.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-call-no-external-funcs.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @_Z14func_exit_codev() nounwind uwtable {
entry:
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-call.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-call.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-call.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
declare void @exit(i32)
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-cast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-cast.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-cast.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-cast.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @foo() {
ret i32 0
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-common-symbols.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-common-symbols.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-common-symbols.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-common-symbols.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit -O0 -disable-lazy-compilation=false %s
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -O0 -disable-lazy-compilation=false %s
; The intention of this test is to verify that symbols mapped to COMMON in ELF
; work as expected.
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-constantexpr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-constantexpr.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-constantexpr.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-constantexpr.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
; This tests to make sure that we can evaluate weird constant expressions
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define double @test(double* %DP, double %Arg) {
%D = load double* %DP ; <double> [#uses=1]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-fp.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-fp.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-fp.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define double @test(double* %DP, double %Arg) {
%D = load double* %DP ; <double> [#uses=1]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
@count = global i32 1, align 4
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-global.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-global.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-global.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-global.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
@count = global i32 0, align 4
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-loadstore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-loadstore.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-loadstore.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-loadstore.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define void @test(i8* %P, i16* %P.upgrd.1, i32* %P.upgrd.2, i64* %P.upgrd.3) {
%V = load i8* %P ; <i8> [#uses=1]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-local.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-local.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-local.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-local.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @main() nounwind uwtable {
entry:
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-logical.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-logical.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-logical.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-logical.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @main() {
%A = and i8 4, 8 ; <i8> [#uses=2]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-loop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-loop.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-loop.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-loop.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @main() {
; <label>:0
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-phi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-phi.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-phi.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-phi.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
; test phi node
@Y = global i32 6 ; <i32*> [#uses=1]
Added: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-ptr-reloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-ptr-reloc.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-ptr-reloc.ll (added)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-ptr-reloc.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,16 @@
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -O0 %s
+
+ at .str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
+ at ptr = global i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), align 4
+ at .str1 = private unnamed_addr constant [6 x i8] c"data2\00", align 1
+ at ptr2 = global i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0), align 4
+
+define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly {
+entry:
+ %0 = load i8** @ptr, align 4
+ %1 = load i8** @ptr2, align 4
+ %cmp = icmp eq i8* %0, %1
+ %. = zext i1 %cmp to i32
+ ret i32 %.
+}
+
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-ret.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-ret.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-ret.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-ret.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
; test return instructions
define void @test1() {
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-return.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-return.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-return.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-return.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @main() nounwind uwtable {
entry:
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-setcond-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-setcond-fp.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-setcond-fp.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-setcond-fp.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @main() {
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-setcond-int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-setcond-int.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-setcond-int.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-setcond-int.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @main() {
%int1 = add i32 0, 0 ; <i32> [#uses=6]
Modified: llvm/branches/R600/test/ExecutionEngine/MCJIT/test-shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/MCJIT/test-shift.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/MCJIT/test-shift.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/MCJIT/test-shift.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-; RUN: %lli -use-mcjit %s > /dev/null
+; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null
define i32 @main() {
%shamt = add i8 0, 1 ; <i8> [#uses=8]
Modified: llvm/branches/R600/test/ExecutionEngine/test-fp-no-external-funcs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/test-fp-no-external-funcs.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/test-fp-no-external-funcs.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/test-fp-no-external-funcs.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,5 @@
; RUN: %lli %s > /dev/null
+; XFAIL: arm
define double @test(double* %DP, double %Arg) {
%D = load double* %DP ; <double> [#uses=1]
Modified: llvm/branches/R600/test/ExecutionEngine/test-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/ExecutionEngine/test-fp.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/ExecutionEngine/test-fp.ll (original)
+++ llvm/branches/R600/test/ExecutionEngine/test-fp.ll Thu Oct 11 16:28:00 2012
@@ -1,4 +1,5 @@
; RUN: %lli %s > /dev/null
+; XFAIL: arm
define double @test(double* %DP, double %Arg) {
%D = load double* %DP ; <double> [#uses=1]
Modified: llvm/branches/R600/test/Instrumentation/ThreadSanitizer/atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Instrumentation/ThreadSanitizer/atomic.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Instrumentation/ThreadSanitizer/atomic.ll (original)
+++ llvm/branches/R600/test/Instrumentation/ThreadSanitizer/atomic.ll Thu Oct 11 16:28:00 2012
@@ -8,7 +8,7 @@
ret i8 %0
}
; CHECK: atomic8_load_unordered
-; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 1)
+; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 100501)
define i8 @atomic8_load_monotonic(i8* %a) nounwind uwtable {
entry:
@@ -16,7 +16,7 @@
ret i8 %0
}
; CHECK: atomic8_load_monotonic
-; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 1)
+; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 100501)
define i8 @atomic8_load_acquire(i8* %a) nounwind uwtable {
entry:
@@ -24,7 +24,7 @@
ret i8 %0
}
; CHECK: atomic8_load_acquire
-; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 4)
+; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 100504)
define i8 @atomic8_load_seq_cst(i8* %a) nounwind uwtable {
entry:
@@ -32,7 +32,7 @@
ret i8 %0
}
; CHECK: atomic8_load_seq_cst
-; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 32)
+; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 100532)
define void @atomic8_store_unordered(i8* %a) nounwind uwtable {
entry:
@@ -40,7 +40,7 @@
ret void
}
; CHECK: atomic8_store_unordered
-; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 1)
+; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 100501)
define void @atomic8_store_monotonic(i8* %a) nounwind uwtable {
entry:
@@ -48,7 +48,7 @@
ret void
}
; CHECK: atomic8_store_monotonic
-; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 1)
+; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 100501)
define void @atomic8_store_release(i8* %a) nounwind uwtable {
entry:
@@ -56,7 +56,7 @@
ret void
}
; CHECK: atomic8_store_release
-; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 8)
+; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 100508)
define void @atomic8_store_seq_cst(i8* %a) nounwind uwtable {
entry:
@@ -64,7 +64,7 @@
ret void
}
; CHECK: atomic8_store_seq_cst
-; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 32)
+; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 100532)
define i16 @atomic16_load_unordered(i16* %a) nounwind uwtable {
entry:
@@ -72,7 +72,7 @@
ret i16 %0
}
; CHECK: atomic16_load_unordered
-; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 1)
+; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 100501)
define i16 @atomic16_load_monotonic(i16* %a) nounwind uwtable {
entry:
@@ -80,7 +80,7 @@
ret i16 %0
}
; CHECK: atomic16_load_monotonic
-; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 1)
+; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 100501)
define i16 @atomic16_load_acquire(i16* %a) nounwind uwtable {
entry:
@@ -88,7 +88,7 @@
ret i16 %0
}
; CHECK: atomic16_load_acquire
-; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 4)
+; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 100504)
define i16 @atomic16_load_seq_cst(i16* %a) nounwind uwtable {
entry:
@@ -96,7 +96,7 @@
ret i16 %0
}
; CHECK: atomic16_load_seq_cst
-; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 32)
+; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 100532)
define void @atomic16_store_unordered(i16* %a) nounwind uwtable {
entry:
@@ -104,7 +104,7 @@
ret void
}
; CHECK: atomic16_store_unordered
-; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 1)
+; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 100501)
define void @atomic16_store_monotonic(i16* %a) nounwind uwtable {
entry:
@@ -112,7 +112,7 @@
ret void
}
; CHECK: atomic16_store_monotonic
-; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 1)
+; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 100501)
define void @atomic16_store_release(i16* %a) nounwind uwtable {
entry:
@@ -120,7 +120,7 @@
ret void
}
; CHECK: atomic16_store_release
-; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 8)
+; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 100508)
define void @atomic16_store_seq_cst(i16* %a) nounwind uwtable {
entry:
@@ -128,7 +128,7 @@
ret void
}
; CHECK: atomic16_store_seq_cst
-; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 32)
+; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 100532)
define i32 @atomic32_load_unordered(i32* %a) nounwind uwtable {
entry:
@@ -136,7 +136,7 @@
ret i32 %0
}
; CHECK: atomic32_load_unordered
-; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 1)
+; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 100501)
define i32 @atomic32_load_monotonic(i32* %a) nounwind uwtable {
entry:
@@ -144,7 +144,7 @@
ret i32 %0
}
; CHECK: atomic32_load_monotonic
-; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 1)
+; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 100501)
define i32 @atomic32_load_acquire(i32* %a) nounwind uwtable {
entry:
@@ -152,7 +152,7 @@
ret i32 %0
}
; CHECK: atomic32_load_acquire
-; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 4)
+; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 100504)
define i32 @atomic32_load_seq_cst(i32* %a) nounwind uwtable {
entry:
@@ -160,7 +160,7 @@
ret i32 %0
}
; CHECK: atomic32_load_seq_cst
-; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 32)
+; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 100532)
define void @atomic32_store_unordered(i32* %a) nounwind uwtable {
entry:
@@ -168,7 +168,7 @@
ret void
}
; CHECK: atomic32_store_unordered
-; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 1)
+; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 100501)
define void @atomic32_store_monotonic(i32* %a) nounwind uwtable {
entry:
@@ -176,7 +176,7 @@
ret void
}
; CHECK: atomic32_store_monotonic
-; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 1)
+; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 100501)
define void @atomic32_store_release(i32* %a) nounwind uwtable {
entry:
@@ -184,7 +184,7 @@
ret void
}
; CHECK: atomic32_store_release
-; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 8)
+; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 100508)
define void @atomic32_store_seq_cst(i32* %a) nounwind uwtable {
entry:
@@ -192,7 +192,7 @@
ret void
}
; CHECK: atomic32_store_seq_cst
-; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 32)
+; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 100532)
define i64 @atomic64_load_unordered(i64* %a) nounwind uwtable {
entry:
@@ -200,7 +200,7 @@
ret i64 %0
}
; CHECK: atomic64_load_unordered
-; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 1)
+; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 100501)
define i64 @atomic64_load_monotonic(i64* %a) nounwind uwtable {
entry:
@@ -208,7 +208,7 @@
ret i64 %0
}
; CHECK: atomic64_load_monotonic
-; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 1)
+; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 100501)
define i64 @atomic64_load_acquire(i64* %a) nounwind uwtable {
entry:
@@ -216,7 +216,7 @@
ret i64 %0
}
; CHECK: atomic64_load_acquire
-; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 4)
+; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 100504)
define i64 @atomic64_load_seq_cst(i64* %a) nounwind uwtable {
entry:
@@ -224,7 +224,7 @@
ret i64 %0
}
; CHECK: atomic64_load_seq_cst
-; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 32)
+; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 100532)
define void @atomic64_store_unordered(i64* %a) nounwind uwtable {
entry:
@@ -232,7 +232,7 @@
ret void
}
; CHECK: atomic64_store_unordered
-; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 1)
+; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 100501)
define void @atomic64_store_monotonic(i64* %a) nounwind uwtable {
entry:
@@ -240,7 +240,7 @@
ret void
}
; CHECK: atomic64_store_monotonic
-; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 1)
+; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 100501)
define void @atomic64_store_release(i64* %a) nounwind uwtable {
entry:
@@ -248,7 +248,7 @@
ret void
}
; CHECK: atomic64_store_release
-; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 8)
+; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 100508)
define void @atomic64_store_seq_cst(i64* %a) nounwind uwtable {
entry:
@@ -256,7 +256,7 @@
ret void
}
; CHECK: atomic64_store_seq_cst
-; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 32)
+; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 100532)
define i128 @atomic128_load_unordered(i128* %a) nounwind uwtable {
entry:
@@ -264,7 +264,7 @@
ret i128 %0
}
; CHECK: atomic128_load_unordered
-; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 1)
+; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 100501)
define i128 @atomic128_load_monotonic(i128* %a) nounwind uwtable {
entry:
@@ -272,7 +272,7 @@
ret i128 %0
}
; CHECK: atomic128_load_monotonic
-; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 1)
+; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 100501)
define i128 @atomic128_load_acquire(i128* %a) nounwind uwtable {
entry:
@@ -280,7 +280,7 @@
ret i128 %0
}
; CHECK: atomic128_load_acquire
-; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 4)
+; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 100504)
define i128 @atomic128_load_seq_cst(i128* %a) nounwind uwtable {
entry:
@@ -288,7 +288,7 @@
ret i128 %0
}
; CHECK: atomic128_load_seq_cst
-; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 32)
+; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 100532)
define void @atomic128_store_unordered(i128* %a) nounwind uwtable {
entry:
@@ -296,7 +296,7 @@
ret void
}
; CHECK: atomic128_store_unordered
-; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 1)
+; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 100501)
define void @atomic128_store_monotonic(i128* %a) nounwind uwtable {
entry:
@@ -304,7 +304,7 @@
ret void
}
; CHECK: atomic128_store_monotonic
-; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 1)
+; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 100501)
define void @atomic128_store_release(i128* %a) nounwind uwtable {
entry:
@@ -312,7 +312,7 @@
ret void
}
; CHECK: atomic128_store_release
-; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 8)
+; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 100508)
define void @atomic128_store_seq_cst(i128* %a) nounwind uwtable {
entry:
@@ -320,4 +320,4 @@
ret void
}
; CHECK: atomic128_store_seq_cst
-; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 32)
+; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 100532)
Modified: llvm/branches/R600/test/MC/ARM/diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/MC/ARM/diagnostics.s?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/MC/ARM/diagnostics.s (original)
+++ llvm/branches/R600/test/MC/ARM/diagnostics.s Thu Oct 11 16:28:00 2012
@@ -361,3 +361,13 @@
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: cps f,#1
@ CHECK-ERRORS: ^
+
+ @ Bad operands for msr
+ msr #0, #0
+ msr foo, #0
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: msr #0, #0
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: msr foo, #0
+@ CHECK-ERRORS: ^
Added: llvm/branches/R600/test/MC/Mips/mips-expansions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/MC/Mips/mips-expansions.s?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/MC/Mips/mips-expansions.s (added)
+++ llvm/branches/R600/test/MC/Mips/mips-expansions.s Thu Oct 11 16:28:00 2012
@@ -0,0 +1,27 @@
+# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
+# Check that the assembler can handle the documented syntax
+# for macro instructions
+# CHECK: .section __TEXT,__text,regular,pure_instructions
+#------------------------------------------------------------------------------
+# Load immediate instructions
+#------------------------------------------------------------------------------
+# CHECK: ori $5, $zero, 123 # encoding: [0x7b,0x00,0x05,0x34]
+# CHECK: addiu $6, $zero, -2345 # encoding: [0xd7,0xf6,0x06,0x24]
+# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c]
+# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34]
+# CHECK: addiu $4, $zero, 20 # encoding: [0x14,0x00,0x04,0x24]
+# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c]
+# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34]
+# CHECK: addiu $4, $5, 20 # encoding: [0x14,0x00,0xa4,0x24]
+# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c]
+# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34]
+# CHECK: addu $7, $7, $8 # encoding: [0x21,0x38,0xe8,0x00]
+
+ li $5,123
+ li $6,-2345
+ li $7,65538
+
+ la $a0, 20
+ la $7,65538
+ la $a0, 20($a1)
+ la $7,65538($8)
Modified: llvm/branches/R600/test/MC/Mips/mips-fpu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/MC/Mips/mips-fpu-instructions.s?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/MC/Mips/mips-fpu-instructions.s (original)
+++ llvm/branches/R600/test/MC/Mips/mips-fpu-instructions.s Thu Oct 11 16:28:00 2012
@@ -149,6 +149,14 @@
# CHECK: mthi $7 # encoding: [0x11,0x00,0xe0,0x00]
# CHECK: mtlo $7 # encoding: [0x13,0x00,0xe0,0x00]
# CHECK: swc1 $f9, 9158($7) # encoding: [0xc6,0x23,0xe9,0xe4]
+# CHECK: mfc0 $6, $7, 0 # encoding: [0x00,0x38,0x06,0x40]
+# CHECK: mtc0 $9, $8, 0 # encoding: [0x00,0x40,0x89,0x40]
+# CHECK: mfc2 $5, $7, 0 # encoding: [0x00,0x38,0x05,0x48]
+# CHECK: mtc2 $9, $4, 0 # encoding: [0x00,0x20,0x89,0x48]
+# CHECK: mfc0 $6, $7, 2 # encoding: [0x02,0x38,0x06,0x40]
+# CHECK: mtc0 $9, $8, 3 # encoding: [0x03,0x40,0x89,0x40]
+# CHECK: mfc2 $5, $7, 4 # encoding: [0x04,0x38,0x05,0x48]
+# CHECK: mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48]
cfc1 $a2,$0
mfc1 $a2,$f7
@@ -160,3 +168,11 @@
mthi $a3
mtlo $a3
swc1 $f9,9158($a3)
+ mfc0 $6, $7
+ mtc0 $9, $8
+ mfc2 $5, $7
+ mtc2 $9, $4
+ mfc0 $6, $7, 2
+ mtc0 $9, $8, 3
+ mfc2 $5, $7, 4
+ mtc2 $9, $4, 5
Modified: llvm/branches/R600/test/MC/Mips/mips_directives.s
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/MC/Mips/mips_directives.s?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/MC/Mips/mips_directives.s (original)
+++ llvm/branches/R600/test/MC/Mips/mips_directives.s Thu Oct 11 16:28:00 2012
@@ -1,10 +1,16 @@
# RUN: llvm-mc -triple mips-unknown-unknown %s
-
+#this test produces no output so there isS no FileCheck call
$BB0_2:
+ .ent directives_test
.frame $sp,0,$ra
.mask 0x00000000,0
.fmask 0x00000000,0
.set noreorder
.set nomacro
+ .set noat
$JTI0_0:
.gpword ($BB0_2)
+ .set at=$12
+ .set macro
+ .set reorder
+ .end directives_test
Modified: llvm/branches/R600/test/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Makefile?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Makefile (original)
+++ llvm/branches/R600/test/Makefile Thu Oct 11 16:28:00 2012
@@ -29,11 +29,6 @@
LIT_ARGS := -s -v
endif
-# -jN causes crash on Cygwin's python.
-ifneq (,$(filter $(HOST_OS),Cygwin))
- LIT_ARGS += -j1
-endif
-
ifdef TESTSUITE
LIT_TESTSUITE := $(TESTSUITE)
CLEANED_TESTSUITE := $(patsubst %/,%,$(TESTSUITE))
Added: llvm/branches/R600/test/Other/ResponseFile.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Other/ResponseFile.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/Other/ResponseFile.ll (added)
+++ llvm/branches/R600/test/Other/ResponseFile.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,9 @@
+; RUN: echo %s > %t.list
+; RUN: llvm-as @%t.list -o %t.bc
+; RUN: llvm-nm %t.bc 2>&1 | FileCheck %s
+
+; CHECK: T foobar
+
+define void @foobar() {
+ ret void
+}
Added: llvm/branches/R600/test/Transforms/DeadArgElim/dbginfo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/DeadArgElim/dbginfo.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/Transforms/DeadArgElim/dbginfo.ll (added)
+++ llvm/branches/R600/test/Transforms/DeadArgElim/dbginfo.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,64 @@
+; RUN: opt %s -deadargelim -S | FileCheck %s
+; PR14016
+
+; Check that debug info metadata for subprograms stores pointers to
+; updated LLVM functions.
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+ at x = global i32 0, align 4
+
+define void @_Z3runv() uwtable {
+entry:
+ call void @_ZN12_GLOBAL__N_18dead_argEPv(i8* null), !dbg !10
+ call void (...)* @_ZN12_GLOBAL__N_111dead_varargEz(), !dbg !12
+ ret void, !dbg !13
+}
+
+; Argument will be deleted
+define internal void @_ZN12_GLOBAL__N_18dead_argEPv(i8* %foo) nounwind uwtable {
+entry:
+ %0 = load i32* @x, align 4, !dbg !14
+ %inc = add nsw i32 %0, 1, !dbg !14
+ store i32 %inc, i32* @x, align 4, !dbg !14
+ ret void, !dbg !16
+}
+
+; Vararg will be deleted
+define internal void @_ZN12_GLOBAL__N_111dead_varargEz(...) nounwind uwtable {
+entry:
+ %0 = load i32* @x, align 4, !dbg !17
+ %inc = add nsw i32 %0, 1, !dbg !17
+ store i32 %inc, i32* @x, align 4, !dbg !17
+ ret void, !dbg !19
+}
+
+!llvm.dbg.cu = !{!0}
+
+!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"test.cc", metadata !"/home/samsonov/tmp/clang-di", metadata !"clang version 3.2 (trunk 165305)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ] [/home/samsonov/tmp/clang-di/test.cc] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !2}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{metadata !5, metadata !8, metadata !9}
+!5 = metadata !{i32 786478, i32 0, metadata !6, metadata !"run", metadata !"run", metadata !"", metadata !6, i32 8, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @_Z3runv, null, null, metadata !1, i32 8} ; [ DW_TAG_subprogram ] [line 8] [def] [run]
+!6 = metadata !{i32 786473, metadata !"test.cc", metadata !"/home/samsonov/tmp/clang-di", null} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = metadata !{i32 786478, i32 0, metadata !6, metadata !"dead_vararg", metadata !"dead_vararg", metadata !"", metadata !6, i32 5, metadata !7, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (...)* @_ZN12_GLOBAL__N_111dead_varargEz, null, null, metadata !1, i32 5} ; [ DW_TAG_subprogram ] [line 5] [local] [def] [dead_vararg]
+
+; CHECK: metadata !"dead_vararg"{{.*}}void ()* @_ZN12_GLOBAL__N_111dead_varargEz
+
+!9 = metadata !{i32 786478, i32 0, metadata !6, metadata !"dead_arg", metadata !"dead_arg", metadata !"", metadata !6, i32 4, metadata !7, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i8*)* @_ZN12_GLOBAL__N_18dead_argEPv, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 4] [local] [def] [dead_arg]
+
+; CHECK: metadata !"dead_arg"{{.*}}void ()* @_ZN12_GLOBAL__N_18dead_argEPv
+
+!10 = metadata !{i32 8, i32 14, metadata !11, null}
+!11 = metadata !{i32 786443, metadata !5, i32 8, i32 12, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] [/home/samsonov/tmp/clang-di/test.cc]
+!12 = metadata !{i32 8, i32 27, metadata !11, null}
+!13 = metadata !{i32 8, i32 42, metadata !11, null}
+!14 = metadata !{i32 4, i32 28, metadata !15, null}
+!15 = metadata !{i32 786443, metadata !9, i32 4, i32 26, metadata !6, i32 2} ; [ DW_TAG_lexical_block ] [/home/samsonov/tmp/clang-di/test.cc]
+!16 = metadata !{i32 4, i32 33, metadata !15, null}
+!17 = metadata !{i32 5, i32 25, metadata !18, null}
+!18 = metadata !{i32 786443, metadata !8, i32 5, i32 23, metadata !6, i32 1} ; [ DW_TAG_lexical_block ] [/home/samsonov/tmp/clang-di/test.cc]
+!19 = metadata !{i32 5, i32 30, metadata !18, null}
Added: llvm/branches/R600/test/Transforms/EarlyCSE/commute.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/EarlyCSE/commute.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/Transforms/EarlyCSE/commute.ll (added)
+++ llvm/branches/R600/test/Transforms/EarlyCSE/commute.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,66 @@
+; RUN: opt < %s -S -early-cse | FileCheck %s
+
+; CHECK: @test1
+define void @test1(float %A, float %B, float* %PA, float* %PB) {
+ ; CHECK-NEXT: fadd
+ ; CHECK-NEXT: store
+ ; CHECK-NEXT: store
+ ; CHECK-NEXT: ret
+ %C = fadd float %A, %B
+ store float %C, float* %PA
+ %D = fadd float %B, %A
+ store float %D, float* %PB
+ ret void
+}
+
+; CHECK: @test2
+define void @test2(float %A, float %B, i1* %PA, i1* %PB) {
+ ; CHECK-NEXT: fcmp
+ ; CHECK-NEXT: store
+ ; CHECK-NEXT: store
+ ; CHECK-NEXT: ret
+ %C = fcmp eq float %A, %B
+ store i1 %C, i1* %PA
+ %D = fcmp eq float %B, %A
+ store i1 %D, i1* %PB
+ ret void
+}
+
+; CHECK: @test3
+define void @test3(float %A, float %B, i1* %PA, i1* %PB) {
+ ; CHECK-NEXT: fcmp
+ ; CHECK-NEXT: store
+ ; CHECK-NEXT: store
+ ; CHECK-NEXT: ret
+ %C = fcmp uge float %A, %B
+ store i1 %C, i1* %PA
+ %D = fcmp ule float %B, %A
+ store i1 %D, i1* %PB
+ ret void
+}
+
+; CHECK: @test4
+define void @test4(i32 %A, i32 %B, i1* %PA, i1* %PB) {
+ ; CHECK-NEXT: icmp
+ ; CHECK-NEXT: store
+ ; CHECK-NEXT: store
+ ; CHECK-NEXT: ret
+ %C = icmp eq i32 %A, %B
+ store i1 %C, i1* %PA
+ %D = icmp eq i32 %B, %A
+ store i1 %D, i1* %PB
+ ret void
+}
+
+; CHECK: @test5
+define void @test5(i32 %A, i32 %B, i1* %PA, i1* %PB) {
+ ; CHECK-NEXT: icmp
+ ; CHECK-NEXT: store
+ ; CHECK-NEXT: store
+ ; CHECK-NEXT: ret
+ %C = icmp sgt i32 %A, %B
+ store i1 %C, i1* %PA
+ %D = icmp slt i32 %B, %A
+ store i1 %D, i1* %PB
+ ret void
+}
Modified: llvm/branches/R600/test/Transforms/IndVarSimplify/2004-04-05-InvokeCastCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/IndVarSimplify/2004-04-05-InvokeCastCrash.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Transforms/IndVarSimplify/2004-04-05-InvokeCastCrash.ll (original)
+++ llvm/branches/R600/test/Transforms/IndVarSimplify/2004-04-05-InvokeCastCrash.ll Thu Oct 11 16:28:00 2012
@@ -39,11 +39,11 @@
%"struct.llvm::SymbolTable" = type opaque
%"struct.llvm::SymbolTableListTraits<llvm::Argument,llvm::Function,llvm::Function,llvm::ilist_traits<llvm::Argument> >" = type { %"struct.llvm::Function"*, %"struct.llvm::Function"* }
%"struct.llvm::SymbolTableListTraits<llvm::Instruction,llvm::BasicBlock,llvm::Function,llvm::ilist_traits<llvm::Instruction> >" = type { %"struct.llvm::Function"*, %"struct.llvm::BasicBlock"* }
- %"struct.llvm::TargetData" = type { %"struct.llvm::FunctionPass", i1, i8, i8, i8, i8, i8, i8, i8, i8 }
+ %"struct.llvm::DataLayout" = type { %"struct.llvm::FunctionPass", i1, i8, i8, i8, i8, i8, i8, i8, i8 }
%"struct.llvm::TargetFrameInfo" = type { i32 (...)**, i32, i32, i32 }
%"struct.llvm::TargetInstrDescriptor" = type { i8*, i32, i32, i32, i1, i32, i32, i32, i32, i32, i32*, i32* }
%"struct.llvm::TargetInstrInfo" = type { i32 (...)**, %"struct.llvm::TargetInstrDescriptor"*, i32, i32 }
- %"struct.llvm::TargetMachine" = type { i32 (...)**, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >", %"struct.llvm::TargetData", %"struct.llvm::IntrinsicLowering"* }
+ %"struct.llvm::TargetMachine" = type { i32 (...)**, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >", %"struct.llvm::DataLayout", %"struct.llvm::IntrinsicLowering"* }
%"struct.llvm::TargetRegClassInfo" = type { i32 (...)**, i32, i32, i32 }
%"struct.llvm::TargetRegInfo" = type { i32 (...)**, %"struct.std::vector<const llvm::TargetRegClassInfo*,std::allocator<const llvm::TargetRegClassInfo*> >", %"struct.llvm::TargetMachine"* }
%"struct.llvm::Type" = type { %"struct.llvm::Value", i32, i32, i1, i32, %"struct.llvm::Type"*, %"struct.std::vector<llvm::PATypeHandle,std::allocator<llvm::PATypeHandle> >" }
Modified: llvm/branches/R600/test/Transforms/IndVarSimplify/crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/IndVarSimplify/crash.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Transforms/IndVarSimplify/crash.ll (original)
+++ llvm/branches/R600/test/Transforms/IndVarSimplify/crash.ll Thu Oct 11 16:28:00 2012
@@ -87,3 +87,29 @@
main.f.exit: ; preds = %"3.i"
unreachable
}
+
+
+; PR13967
+
+define void @f() nounwind ssp {
+bb:
+ br label %bb4
+
+bb4:
+ %tmp = phi i64 [ %tmp5, %bb7 ], [ undef, %bb ]
+ %tmp5 = add nsw i64 %tmp, 1
+ %extract.t1 = trunc i64 %tmp5 to i32
+ br i1 false, label %bb6, label %bb7
+
+bb6:
+ br label %bb7
+
+bb7:
+ %.off0 = phi i32 [ undef, %bb6 ], [ %extract.t1, %bb4 ]
+ %tmp8 = icmp eq i32 %.off0, 0
+ br i1 %tmp8, label %bb9, label %bb4
+
+bb9:
+ ret void
+}
+
Modified: llvm/branches/R600/test/Transforms/InstCombine/align-addr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/InstCombine/align-addr.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Transforms/InstCombine/align-addr.ll (original)
+++ llvm/branches/R600/test/Transforms/InstCombine/align-addr.ll Thu Oct 11 16:28:00 2012
@@ -58,3 +58,19 @@
store double %n, double* %p
ret double %t
}
+
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
+
+declare void @use(i8*)
+
+%struct.s = type { i32, i32, i32, i32 }
+
+define void @test3(%struct.s* sret %a4) {
+; Check that the alignment is bumped up the alignment of the sret type.
+; CHECK: @test3
+ %a4.cast = bitcast %struct.s* %a4 to i8*
+ call void @llvm.memset.p0i8.i64(i8* %a4.cast, i8 0, i64 16, i32 1, i1 false)
+; CHECK: call void @llvm.memset.p0i8.i64(i8* %a4.cast, i8 0, i64 16, i32 4, i1 false)
+ call void @use(i8* %a4.cast)
+ ret void
+}
Modified: llvm/branches/R600/test/Transforms/InstCombine/and-fcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/InstCombine/and-fcmp.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Transforms/InstCombine/and-fcmp.ll (original)
+++ llvm/branches/R600/test/Transforms/InstCombine/and-fcmp.ll Thu Oct 11 16:28:00 2012
@@ -10,7 +10,7 @@
; CHECK: fcmp oeq float %x, %y
; CHECK-NOT: fcmp ueq float %x, %y
; CHECK-NOT: fcmp ord float %x, %y
-; CHECK-NOW: and
+; CHECK-NOT: and
}
define zeroext i8 @t2(float %x, float %y) nounwind {
Modified: llvm/branches/R600/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll (original)
+++ llvm/branches/R600/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll Thu Oct 11 16:28:00 2012
@@ -9,11 +9,11 @@
define float @f() {
entry:
%a_var = alloca %a
- %b_var = alloca %b
+ %b_var = alloca %b, align 1
call void @g(%a* %a_var)
%a_i8 = bitcast %a* %a_var to i8*
%b_i8 = bitcast %b* %b_var to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %b_i8, i8* %a_i8, i32 4, i32 4, i1 false)
+ call void @llvm.memcpy.p0i8.p0i8.i32(i8* %b_i8, i8* %a_i8, i32 4, i32 1, i1 false)
%tmp1 = getelementptr %b* %b_var, i32 0, i32 0
%tmp2 = load float* %tmp1
ret float %tmp2
Modified: llvm/branches/R600/test/Transforms/MemCpyOpt/align.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/MemCpyOpt/align.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Transforms/MemCpyOpt/align.ll (original)
+++ llvm/branches/R600/test/Transforms/MemCpyOpt/align.ll Thu Oct 11 16:28:00 2012
@@ -1,12 +1,15 @@
-; RUN: opt < %s -S -memcpyopt | FileCheck %s
+; RUN: opt < %s -S -basicaa -memcpyopt | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
+
; The resulting memset is only 4-byte aligned, despite containing
; a 16-byte aligned store in the middle.
-; CHECK: call void @llvm.memset.p0i8.i64(i8* {{.*}}, i8 0, i64 16, i32 4, i1 false)
-
define void @foo(i32* %p) {
+; CHECK: @foo
+; CHECK: call void @llvm.memset.p0i8.i64(i8* {{.*}}, i8 0, i64 16, i32 4, i1 false)
%a0 = getelementptr i32* %p, i64 0
store i32 0, i32* %a0, align 4
%a1 = getelementptr i32* %p, i64 1
@@ -17,3 +20,18 @@
store i32 0, i32* %a3, align 4
ret void
}
+
+; Replacing %a8 with %a4 in the memset requires boosting the alignment of %a4.
+
+define void @bar() {
+; CHECK: @bar
+; CHECK: %a4 = alloca i32, align 8
+; CHECK-NOT: memcpy
+ %a4 = alloca i32, align 4
+ %a8 = alloca i32, align 8
+ %a8.cast = bitcast i32* %a8 to i8*
+ %a4.cast = bitcast i32* %a4 to i8*
+ call void @llvm.memset.p0i8.i64(i8* %a8.cast, i8 0, i64 4, i32 8, i1 false)
+ call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a4.cast, i8* %a8.cast, i64 4, i32 4, i1 false)
+ ret void
+}
Modified: llvm/branches/R600/test/Transforms/SROA/alignment.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/SROA/alignment.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Transforms/SROA/alignment.ll (original)
+++ llvm/branches/R600/test/Transforms/SROA/alignment.ll Thu Oct 11 16:28:00 2012
@@ -1,5 +1,5 @@
; RUN: opt < %s -sroa -S | FileCheck %s
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
@@ -31,8 +31,8 @@
define void @test2() {
; CHECK: @test2
; CHECK: alloca i16
-; CHECK: load i8* %{{.*}}, align 1
-; CHECK: store i8 42, i8* %{{.*}}, align 1
+; CHECK: load i8* %{{.*}}
+; CHECK: store i8 42, i8* %{{.*}}
; CHECK: ret void
entry:
@@ -41,8 +41,8 @@
%cast1 = bitcast i8* %gep1 to i16*
store volatile i16 0, i16* %cast1
%gep2 = getelementptr { i8, i8, i8, i8 }* %a, i32 0, i32 2
- %result = load i8* %gep2, align 2
- store i8 42, i8* %gep2, align 2
+ %result = load i8* %gep2
+ store i8 42, i8* %gep2
ret void
}
@@ -114,3 +114,89 @@
ret void
}
+
+define void @test5() {
+; Test that we preserve underaligned loads and stores when splitting.
+; CHECK: @test5
+; CHECK: alloca [9 x i8]
+; CHECK: alloca [9 x i8]
+; CHECK: store volatile double 0.0{{.*}}, double* %{{.*}}, align 1
+; CHECK: load i16* %{{.*}}, align 1
+; CHECK: load double* %{{.*}}, align 1
+; CHECK: store volatile double %{{.*}}, double* %{{.*}}, align 1
+; CHECK: load i16* %{{.*}}, align 1
+; CHECK: ret void
+
+entry:
+ %a = alloca [18 x i8]
+ %raw1 = getelementptr inbounds [18 x i8]* %a, i32 0, i32 0
+ %ptr1 = bitcast i8* %raw1 to double*
+ store volatile double 0.0, double* %ptr1, align 1
+ %weird_gep1 = getelementptr inbounds [18 x i8]* %a, i32 0, i32 7
+ %weird_cast1 = bitcast i8* %weird_gep1 to i16*
+ %weird_load1 = load i16* %weird_cast1, align 1
+
+ %raw2 = getelementptr inbounds [18 x i8]* %a, i32 0, i32 9
+ %ptr2 = bitcast i8* %raw2 to double*
+ %d1 = load double* %ptr1, align 1
+ store volatile double %d1, double* %ptr2, align 1
+ %weird_gep2 = getelementptr inbounds [18 x i8]* %a, i32 0, i32 16
+ %weird_cast2 = bitcast i8* %weird_gep2 to i16*
+ %weird_load2 = load i16* %weird_cast2, align 1
+
+ ret void
+}
+
+define void @test6() {
+; Test that we promote alignment when the underlying alloca switches to one
+; that innately provides it.
+; CHECK: @test6
+; CHECK: alloca double
+; CHECK: alloca double
+; CHECK-NOT: align
+; CHECK: ret void
+
+entry:
+ %a = alloca [16 x i8]
+ %raw1 = getelementptr inbounds [16 x i8]* %a, i32 0, i32 0
+ %ptr1 = bitcast i8* %raw1 to double*
+ store volatile double 0.0, double* %ptr1, align 1
+
+ %raw2 = getelementptr inbounds [16 x i8]* %a, i32 0, i32 8
+ %ptr2 = bitcast i8* %raw2 to double*
+ %val = load double* %ptr1, align 1
+ store volatile double %val, double* %ptr2, align 1
+
+ ret void
+}
+
+define void @test7(i8* %out) {
+; Test that we properly compute the destination alignment when rewriting
+; memcpys as direct loads or stores.
+; CHECK: @test7
+; CHECK-NOT: alloca
+
+entry:
+ %a = alloca [16 x i8]
+ %raw1 = getelementptr inbounds [16 x i8]* %a, i32 0, i32 0
+ %ptr1 = bitcast i8* %raw1 to double*
+ %raw2 = getelementptr inbounds [16 x i8]* %a, i32 0, i32 8
+ %ptr2 = bitcast i8* %raw2 to double*
+
+ call void @llvm.memcpy.p0i8.p0i8.i32(i8* %raw1, i8* %out, i32 16, i32 0, i1 false)
+; CHECK: %[[val2:.*]] = load double* %{{.*}}, align 1
+; CHECK: %[[val1:.*]] = load double* %{{.*}}, align 1
+
+ %val1 = load double* %ptr2, align 1
+ %val2 = load double* %ptr1, align 1
+
+ store double %val1, double* %ptr1, align 1
+ store double %val2, double* %ptr2, align 1
+
+ call void @llvm.memcpy.p0i8.p0i8.i32(i8* %out, i8* %raw1, i32 16, i32 0, i1 false)
+; CHECK: store double %[[val1]], double* %{{.*}}, align 1
+; CHECK: store double %[[val2]], double* %{{.*}}, align 1
+
+ ret void
+; CHECK: ret void
+}
Modified: llvm/branches/R600/test/Transforms/SROA/basictest.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/SROA/basictest.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Transforms/SROA/basictest.ll (original)
+++ llvm/branches/R600/test/Transforms/SROA/basictest.ll Thu Oct 11 16:28:00 2012
@@ -1,7 +1,7 @@
; RUN: opt < %s -sroa -S | FileCheck %s
; RUN: opt < %s -sroa -force-ssa-updater -S | FileCheck %s
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
declare void @llvm.lifetime.start(i64, i8* nocapture)
declare void @llvm.lifetime.end(i64, i8* nocapture)
@@ -862,8 +862,7 @@
; Ensure that we handle overlapping memcpy intrinsics correctly, especially in
; the case where there is a directly identical value for both source and dest.
; CHECK: @PR13916.1
-; FIXME: We shouldn't leave this alloca around.
-; CHECK: alloca
+; CHECK-NOT: alloca
; CHECK: ret void
entry:
@@ -878,8 +877,7 @@
; different pointer value chains, but during rewriting we coalesce them into the
; same value.
; CHECK: @PR13916.2
-; FIXME: We shouldn't leave this alloca around.
-; CHECK: alloca
+; CHECK-NOT: alloca
; CHECK: ret void
entry:
@@ -897,3 +895,76 @@
%tmp2 = load i8* %gep
ret void
}
+
+define void @PR13990() {
+; Ensure we can handle cases where processing one alloca causes the other
+; alloca to become dead and get deleted. This might crash or fail under
+; Valgrind if we regress.
+; CHECK: @PR13990
+; CHECK-NOT: alloca
+; CHECK: unreachable
+; CHECK: unreachable
+
+entry:
+ %tmp1 = alloca i8*
+ %tmp2 = alloca i8*
+ br i1 undef, label %bb1, label %bb2
+
+bb1:
+ store i8* undef, i8** %tmp2
+ br i1 undef, label %bb2, label %bb3
+
+bb2:
+ %tmp50 = select i1 undef, i8** %tmp2, i8** %tmp1
+ br i1 undef, label %bb3, label %bb4
+
+bb3:
+ unreachable
+
+bb4:
+ unreachable
+}
+
+define double @PR13969(double %x) {
+; Check that we detect when promotion will un-escape an alloca and iterate to
+; re-try running SROA over that alloca. Without that, the two allocas that are
+; stored into a dead alloca don't get rewritten and promoted.
+; CHECK: @PR13969
+
+entry:
+ %a = alloca double
+ %b = alloca double*
+ %c = alloca double
+; CHECK-NOT: alloca
+
+ store double %x, double* %a
+ store double* %c, double** %b
+ store double* %a, double** %b
+ store double %x, double* %c
+ %ret = load double* %a
+; CHECK-NOT: store
+; CHECK-NOT: load
+
+ ret double %ret
+; CHECK: ret double %x
+}
+
+%PR14034.struct = type { { {} }, i32, %PR14034.list }
+%PR14034.list = type { %PR14034.list*, %PR14034.list* }
+
+define void @PR14034() {
+; This test case tries to form GEPs into the empty leading struct members, and
+; subsequently crashed (under valgrind) before we fixed the PR. The important
+; thing is to handle empty structs gracefully.
+; CHECK: @PR14034
+
+entry:
+ %a = alloca %PR14034.struct
+ %list = getelementptr %PR14034.struct* %a, i32 0, i32 2
+ %prev = getelementptr %PR14034.list* %list, i32 0, i32 1
+ store %PR14034.list* undef, %PR14034.list** %prev
+ %cast0 = bitcast %PR14034.struct* undef to i8*
+ %cast1 = bitcast %PR14034.struct* %a to i8*
+ call void @llvm.memcpy.p0i8.p0i8.i32(i8* %cast0, i8* %cast1, i32 12, i32 0, i1 false)
+ ret void
+}
Added: llvm/branches/R600/test/Transforms/SROA/big-endian.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/SROA/big-endian.ll?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/test/Transforms/SROA/big-endian.ll (added)
+++ llvm/branches/R600/test/Transforms/SROA/big-endian.ll Thu Oct 11 16:28:00 2012
@@ -0,0 +1,108 @@
+; RUN: opt < %s -sroa -S | FileCheck %s
+; RUN: opt < %s -sroa -force-ssa-updater -S | FileCheck %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
+
+define i8 @test1() {
+; We fully promote these to the i24 load or store size, resulting in just masks
+; and other operations that instcombine will fold, but no alloca. Note this is
+; the same as test12 in basictest.ll, but here we assert big-endian byte
+; ordering.
+;
+; CHECK: @test1
+
+entry:
+ %a = alloca [3 x i8]
+ %b = alloca [3 x i8]
+; CHECK-NOT: alloca
+
+ %a0ptr = getelementptr [3 x i8]* %a, i64 0, i32 0
+ store i8 0, i8* %a0ptr
+ %a1ptr = getelementptr [3 x i8]* %a, i64 0, i32 1
+ store i8 0, i8* %a1ptr
+ %a2ptr = getelementptr [3 x i8]* %a, i64 0, i32 2
+ store i8 0, i8* %a2ptr
+ %aiptr = bitcast [3 x i8]* %a to i24*
+ %ai = load i24* %aiptr
+; CHCEK-NOT: store
+; CHCEK-NOT: load
+; CHECK: %[[mask0:.*]] = and i24 undef, 65535
+; CHECK-NEXT: %[[mask1:.*]] = and i24 %[[mask0]], -65281
+; CHECK-NEXT: %[[mask2:.*]] = and i24 %[[mask1]], -256
+
+ %biptr = bitcast [3 x i8]* %b to i24*
+ store i24 %ai, i24* %biptr
+ %b0ptr = getelementptr [3 x i8]* %b, i64 0, i32 0
+ %b0 = load i8* %b0ptr
+ %b1ptr = getelementptr [3 x i8]* %b, i64 0, i32 1
+ %b1 = load i8* %b1ptr
+ %b2ptr = getelementptr [3 x i8]* %b, i64 0, i32 2
+ %b2 = load i8* %b2ptr
+; CHCEK-NOT: store
+; CHCEK-NOT: load
+; CHECK: %[[shift0:.*]] = lshr i24 %[[mask2]], 16
+; CHECK-NEXT: %[[trunc0:.*]] = trunc i24 %[[shift0]] to i8
+; CHECK-NEXT: %[[shift1:.*]] = lshr i24 %[[mask2]], 8
+; CHECK-NEXT: %[[trunc1:.*]] = trunc i24 %[[shift1]] to i8
+; CHECK-NEXT: %[[trunc2:.*]] = trunc i24 %[[mask2]] to i8
+
+ %bsum0 = add i8 %b0, %b1
+ %bsum1 = add i8 %bsum0, %b2
+ ret i8 %bsum1
+; CHECK: %[[sum0:.*]] = add i8 %[[trunc0]], %[[trunc1]]
+; CHECK-NEXT: %[[sum1:.*]] = add i8 %[[sum0]], %[[trunc2]]
+; CHECK-NEXT: ret i8 %[[sum1]]
+}
+
+define i64 @test2() {
+; Test for various mixed sizes of integer loads and stores all getting
+; promoted.
+;
+; CHECK: @test2
+
+entry:
+ %a = alloca [7 x i8]
+; CHECK-NOT: alloca
+
+ %a0ptr = getelementptr [7 x i8]* %a, i64 0, i32 0
+ %a1ptr = getelementptr [7 x i8]* %a, i64 0, i32 1
+ %a2ptr = getelementptr [7 x i8]* %a, i64 0, i32 2
+ %a3ptr = getelementptr [7 x i8]* %a, i64 0, i32 3
+
+; CHCEK-NOT: store
+; CHCEK-NOT: load
+
+ %a0i16ptr = bitcast i8* %a0ptr to i16*
+ store i16 1, i16* %a0i16ptr
+; CHECK: %[[mask:.*]] = and i56 undef, 1099511627775
+; CHECK-NEXT: %[[or:.*]] = or i56 %[[mask]], 1099511627776
+
+ %a1i4ptr = bitcast i8* %a1ptr to i4*
+ store i4 1, i4* %a1i4ptr
+; CHECK: %[[mask:.*]] = and i56 %[[or]], -16492674416641
+; CHECK-NEXT: %[[or:.*]] = or i56 %[[mask]], 1099511627776
+
+ store i8 1, i8* %a2ptr
+; CHECK-NEXT: %[[mask:.*]] = and i56 %[[or]], -1095216660481
+; CHECK-NEXT: %[[or:.*]] = or i56 %[[mask]], 4294967296
+
+ %a3i24ptr = bitcast i8* %a3ptr to i24*
+ store i24 1, i24* %a3i24ptr
+; CHECK-NEXT: %[[mask:.*]] = and i56 %[[or]], -4294967041
+; CHECK-NEXT: %[[or:.*]] = or i56 %[[mask]], 256
+
+ %a2i40ptr = bitcast i8* %a2ptr to i40*
+ store i40 1, i40* %a2i40ptr
+; CHECK-NEXT: %[[mask:.*]] = and i56 %[[or]], -1099511627776
+; CHECK-NEXT: %[[or:.*]] = or i56 %[[mask]], 1
+
+; CHCEK-NOT: store
+; CHCEK-NOT: load
+
+ %aiptr = bitcast [7 x i8]* %a to i56*
+ %ai = load i56* %aiptr
+ %ret = zext i56 %ai to i64
+ ret i64 %ret
+; CHECK: %[[ret:.*]] = zext i56 %[[or]] to i64
+; CHECK-NEXT: ret i64 %[[ret]]
+}
Modified: llvm/branches/R600/test/Transforms/SROA/fca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/SROA/fca.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Transforms/SROA/fca.ll (original)
+++ llvm/branches/R600/test/Transforms/SROA/fca.ll Thu Oct 11 16:28:00 2012
@@ -1,6 +1,6 @@
; RUN: opt < %s -sroa -S | FileCheck %s
; RUN: opt < %s -sroa -force-ssa-updater -S | FileCheck %s
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
define { i32, i32 } @test0(i32 %x, i32 %y) {
; CHECK: @test0
Modified: llvm/branches/R600/test/Transforms/SROA/phi-and-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/SROA/phi-and-select.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Transforms/SROA/phi-and-select.ll (original)
+++ llvm/branches/R600/test/Transforms/SROA/phi-and-select.ll Thu Oct 11 16:28:00 2012
@@ -1,5 +1,5 @@
; RUN: opt < %s -sroa -S | FileCheck %s
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
define i32 @test1() {
; CHECK: @test1
Modified: llvm/branches/R600/test/Transforms/SROA/vector-promotion.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/SROA/vector-promotion.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Transforms/SROA/vector-promotion.ll (original)
+++ llvm/branches/R600/test/Transforms/SROA/vector-promotion.ll Thu Oct 11 16:28:00 2012
@@ -1,5 +1,5 @@
; RUN: opt < %s -sroa -S | FileCheck %s
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
%S1 = type { i64, [42 x float] }
Modified: llvm/branches/R600/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll (original)
+++ llvm/branches/R600/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll Thu Oct 11 16:28:00 2012
@@ -85,3 +85,31 @@
; CHECK: if.end7:
; CHECK: phi i32* [ %a, %if.then ], [ null, %if.then4 ], [ null, %if.else ]
}
+
+define i32 @test4(i32* %a, i32 %b, i32* %c, i32 %d) nounwind {
+entry:
+ %tobool = icmp eq i32 %b, 0
+ br i1 %tobool, label %if.else, label %if.then
+
+if.then: ; preds = %entry
+ tail call void @bar() nounwind
+ br label %if.end7
+
+if.else: ; preds = %entry
+ %tobool3 = icmp eq i32 %d, 0
+ br i1 %tobool3, label %if.end7, label %if.then4
+
+if.then4: ; preds = %if.else
+ tail call void @bar() nounwind
+ br label %if.end7
+
+if.end7: ; preds = %if.else, %if.then4, %if.then
+ %x.0 = phi i32* [ %a, %if.then ], [ null, %if.then4 ], [ null, %if.else ]
+ %gep = getelementptr i32* %x.0, i32 10
+ %tmp9 = load i32* %gep
+ %tmp10 = or i32 %tmp9, 1
+ store i32 %tmp10, i32* %gep
+ ret i32 %tmp9
+; CHECK: @test4
+; CHECK-NOT: phi
+}
Modified: llvm/branches/R600/test/lit.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/test/lit.cfg?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/test/lit.cfg (original)
+++ llvm/branches/R600/test/lit.cfg Thu Oct 11 16:28:00 2012
@@ -139,6 +139,13 @@
###
+# Provide a target triple for mcjit tests
+mcjit_triple = config.target_triple
+# Force ELF format on Windows
+if re.search(r'cygwin|mingw32|win32', mcjit_triple):
+ mcjit_triple += "-elf"
+config.substitutions.append( ('%mcjit_triple', mcjit_triple) )
+
# When running under valgrind, we mangle '-vg' or '-vg_leak' onto the end of the
# triple so we can check it with XFAIL and XTARGET.
config.target_triple += lit.valgrindTriple
Modified: llvm/branches/R600/tools/bugpoint/ExtractFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/tools/bugpoint/ExtractFunction.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/tools/bugpoint/ExtractFunction.cpp (original)
+++ llvm/branches/R600/tools/bugpoint/ExtractFunction.cpp Thu Oct 11 16:28:00 2012
@@ -14,6 +14,7 @@
#include "BugDriver.h"
#include "llvm/Constants.h"
+#include "llvm/DataLayout.h"
#include "llvm/DerivedTypes.h"
#include "llvm/LLVMContext.h"
#include "llvm/Module.h"
@@ -25,7 +26,6 @@
#include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/Utils/Cloning.h"
#include "llvm/Transforms/Utils/CodeExtractor.h"
-#include "llvm/Target/TargetData.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/FileUtilities.h"
Modified: llvm/branches/R600/tools/bugpoint/OptimizerDriver.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/tools/bugpoint/OptimizerDriver.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/tools/bugpoint/OptimizerDriver.cpp (original)
+++ llvm/branches/R600/tools/bugpoint/OptimizerDriver.cpp Thu Oct 11 16:28:00 2012
@@ -16,11 +16,11 @@
//===----------------------------------------------------------------------===//
#include "BugDriver.h"
+#include "llvm/DataLayout.h"
#include "llvm/Module.h"
#include "llvm/PassManager.h"
#include "llvm/Analysis/Verifier.h"
#include "llvm/Bitcode/ReaderWriter.h"
-#include "llvm/Target/TargetData.h"
#include "llvm/Support/FileUtilities.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/SystemUtils.h"
Modified: llvm/branches/R600/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/tools/llc/llc.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/tools/llc/llc.cpp (original)
+++ llvm/branches/R600/tools/llc/llc.cpp Thu Oct 11 16:28:00 2012
@@ -14,6 +14,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/LLVMContext.h"
+#include "llvm/DataLayout.h"
#include "llvm/Module.h"
#include "llvm/PassManager.h"
#include "llvm/Pass.h"
@@ -34,7 +35,6 @@
#include "llvm/Support/Signals.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
-#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Target/TargetMachine.h"
#include <memory>
@@ -506,10 +506,10 @@
PM.add(TLI);
// Add the target data from the target machine, if it exists, or the module.
- if (const TargetData *TD = Target.getTargetData())
- PM.add(new TargetData(*TD));
+ if (const DataLayout *TD = Target.getDataLayout())
+ PM.add(new DataLayout(*TD));
else
- PM.add(new TargetData(mod));
+ PM.add(new DataLayout(mod));
// Override default to generate verbose assembly.
Target.setAsmVerbosityDefault(true);
Modified: llvm/branches/R600/tools/lli/lli.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/tools/lli/lli.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/tools/lli/lli.cpp (original)
+++ llvm/branches/R600/tools/lli/lli.cpp Thu Oct 11 16:28:00 2012
@@ -338,6 +338,10 @@
AllocatedCodeMem[i].size());
}
+static int jit_noop() {
+ return 0;
+}
+
void *LLIMCJITMemoryManager::getPointerToNamedFunction(const std::string &Name,
bool AbortOnFailure) {
#if defined(__linux__)
@@ -360,6 +364,14 @@
if (Name == "mknod") return (void*)(intptr_t)&mknod;
#endif // __linux__
+ // We should not invoke parent's ctors/dtors from generated main()!
+ // On Mingw and Cygwin, the symbol __main is resolved to
+ // callee's(eg. tools/lli) one, to invoke wrong duplicated ctors
+ // (and register wrong callee's dtors with atexit(3)).
+ // We expect ExecutionEngine::runStaticConstructorsDestructors()
+ // is called before ExecutionEngine::runFunctionAsMain() is called.
+ if (Name == "__main") return (void*)(intptr_t)&jit_noop;
+
const char *NameStr = Name.c_str();
void *Ptr = sys::DynamicLibrary::SearchForAddressOfSymbol(NameStr);
if (Ptr) return Ptr;
Modified: llvm/branches/R600/tools/llvm-extract/llvm-extract.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/tools/llvm-extract/llvm-extract.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/tools/llvm-extract/llvm-extract.cpp (original)
+++ llvm/branches/R600/tools/llvm-extract/llvm-extract.cpp Thu Oct 11 16:28:00 2012
@@ -18,7 +18,7 @@
#include "llvm/Assembly/PrintModulePass.h"
#include "llvm/Bitcode/ReaderWriter.h"
#include "llvm/Transforms/IPO.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/IRReader.h"
#include "llvm/Support/ManagedStatic.h"
@@ -206,7 +206,7 @@
// In addition to deleting all other functions, we also want to spiff it
// up a little bit. Do this now.
PassManager Passes;
- Passes.add(new TargetData(M.get())); // Use correct TargetData
+ Passes.add(new DataLayout(M.get())); // Use correct DataLayout
std::vector<GlobalValue*> Gvs(GVs.begin(), GVs.end());
Modified: llvm/branches/R600/tools/llvm-rtdyld/llvm-rtdyld.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/tools/llvm-rtdyld/llvm-rtdyld.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/tools/llvm-rtdyld/llvm-rtdyld.cpp (original)
+++ llvm/branches/R600/tools/llvm-rtdyld/llvm-rtdyld.cpp Thu Oct 11 16:28:00 2012
@@ -14,6 +14,8 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/OwningPtr.h"
#include "llvm/ExecutionEngine/RuntimeDyld.h"
+#include "llvm/ExecutionEngine/ObjectImage.h"
+#include "llvm/ExecutionEngine/ObjectBuffer.h"
#include "llvm/Object/MachOObject.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ManagedStatic.h"
@@ -120,12 +122,14 @@
for(unsigned i = 0, e = InputFileList.size(); i != e; ++i) {
// Load the input memory buffer.
OwningPtr<MemoryBuffer> InputBuffer;
+ OwningPtr<ObjectImage> LoadedObject;
if (error_code ec = MemoryBuffer::getFileOrSTDIN(InputFileList[i],
InputBuffer))
return Error("unable to read input: '" + ec.message() + "'");
- // Load the object file into it.
- if (Dyld.loadObject(InputBuffer.take())) {
+ // Load the object file
+ LoadedObject.reset(Dyld.loadObject(new ObjectBuffer(InputBuffer.take())));
+ if (!LoadedObject) {
return Error(Dyld.getErrorString());
}
}
Modified: llvm/branches/R600/tools/lto/LTOCodeGenerator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/tools/lto/LTOCodeGenerator.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/tools/lto/LTOCodeGenerator.cpp (original)
+++ llvm/branches/R600/tools/lto/LTOCodeGenerator.cpp Thu Oct 11 16:28:00 2012
@@ -15,6 +15,7 @@
#include "LTOCodeGenerator.h"
#include "LTOModule.h"
#include "llvm/Constants.h"
+#include "llvm/DataLayout.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Linker.h"
#include "llvm/LLVMContext.h"
@@ -29,7 +30,6 @@
#include "llvm/MC/SubtargetFeature.h"
#include "llvm/Target/Mangler.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Transforms/IPO.h"
@@ -293,7 +293,7 @@
// mark which symbols can not be internalized
MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(),NULL);
- Mangler mangler(Context, *_target->getTargetData());
+ Mangler mangler(Context, *_target->getDataLayout());
std::vector<const char*> mustPreserveList;
SmallPtrSet<GlobalValue*, 8> asmUsed;
@@ -361,8 +361,8 @@
// Start off with a verification pass.
passes.add(createVerifierPass());
- // Add an appropriate TargetData instance for this module...
- passes.add(new TargetData(*_target->getTargetData()));
+ // Add an appropriate DataLayout instance for this module...
+ passes.add(new DataLayout(*_target->getDataLayout()));
// Enabling internalize here would use its AllButMain variant. It
// keeps only main if it exists and does nothing for libraries. Instead
@@ -376,7 +376,7 @@
FunctionPassManager *codeGenPasses = new FunctionPassManager(mergedModule);
- codeGenPasses->add(new TargetData(*_target->getTargetData()));
+ codeGenPasses->add(new DataLayout(*_target->getDataLayout()));
formatted_raw_ostream Out(out);
Modified: llvm/branches/R600/tools/lto/LTOModule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/tools/lto/LTOModule.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/tools/lto/LTOModule.cpp (original)
+++ llvm/branches/R600/tools/lto/LTOModule.cpp Thu Oct 11 16:28:00 2012
@@ -158,7 +158,7 @@
LTOModule::LTOModule(llvm::Module *m, llvm::TargetMachine *t)
: _module(m), _target(t),
_context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(), NULL),
- _mangler(_context, *_target->getTargetData()) {}
+ _mangler(_context, *_target->getDataLayout()) {}
/// isBitcodeFile - Returns 'true' if the file (or memory contents) is LLVM
/// bitcode.
Modified: llvm/branches/R600/tools/lto/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/tools/lto/Makefile?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/tools/lto/Makefile (original)
+++ llvm/branches/R600/tools/lto/Makefile Thu Oct 11 16:28:00 2012
@@ -49,4 +49,11 @@
-Wl,-install_name \
-Wl,"@executable_path/../lib/lib$(LIBRARYNAME)$(SHLIBEXT)"
endif
+
+ # If we're doing an Apple-style build, add the LTO object path.
+ ifeq ($(RC_BUILDIT),YES)
+ TempFile := $(shell mkdir -p ${OBJROOT}/dSYMs ; mktemp ${OBJROOT}/dSYMs/llvm-lto.XXXXXX)
+ LLVMLibsOptions := $(LLVMLibsOptions) \
+ -Wl,-object_path_lto -Wl,$(TempFile)
+ endif
endif
Modified: llvm/branches/R600/tools/opt/opt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/tools/opt/opt.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/tools/opt/opt.cpp (original)
+++ llvm/branches/R600/tools/opt/opt.cpp Thu Oct 11 16:28:00 2012
@@ -13,6 +13,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/LLVMContext.h"
+#include "llvm/DataLayout.h"
#include "llvm/DebugInfo.h"
#include "llvm/Module.h"
#include "llvm/PassManager.h"
@@ -23,7 +24,6 @@
#include "llvm/Analysis/LoopPass.h"
#include "llvm/Analysis/RegionPass.h"
#include "llvm/Analysis/CallGraph.h"
-#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLibraryInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/StringSet.h"
@@ -568,13 +568,13 @@
TLI->disableAllFunctions();
Passes.add(TLI);
- // Add an appropriate TargetData instance for this module.
- TargetData *TD = 0;
+ // Add an appropriate DataLayout instance for this module.
+ DataLayout *TD = 0;
const std::string &ModuleDataLayout = M.get()->getDataLayout();
if (!ModuleDataLayout.empty())
- TD = new TargetData(ModuleDataLayout);
+ TD = new DataLayout(ModuleDataLayout);
else if (!DefaultDataLayout.empty())
- TD = new TargetData(DefaultDataLayout);
+ TD = new DataLayout(DefaultDataLayout);
if (TD)
Passes.add(TD);
@@ -583,7 +583,7 @@
if (OptLevelO1 || OptLevelO2 || OptLevelOs || OptLevelOz || OptLevelO3) {
FPasses.reset(new FunctionPassManager(M.get()));
if (TD)
- FPasses->add(new TargetData(*TD));
+ FPasses->add(new DataLayout(*TD));
}
if (PrintBreakpoints) {
Modified: llvm/branches/R600/unittests/ADT/StringRefTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/ADT/StringRefTest.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/unittests/ADT/StringRefTest.cpp (original)
+++ llvm/branches/R600/unittests/ADT/StringRefTest.cpp Thu Oct 11 16:28:00 2012
@@ -456,4 +456,27 @@
}
}
+
+static const char* BadStrings[] = {
+ "18446744073709551617" // value just over max
+ , "123456789012345678901" // value way too large
+ , "4t23v" // illegal decimal characters
+ , "0x123W56" // illegal hex characters
+ , "0b2" // illegal bin characters
+ , "08" // illegal oct characters
+ , "0o8" // illegal oct characters
+ , "-123" // negative unsigned value
+};
+
+
+TEST(StringRefTest, getAsUnsignedIntegerBadStrings) {
+ unsigned long long U64;
+ for (size_t i = 0; i < array_lengthof(BadStrings); ++i) {
+ bool IsBadNumber = StringRef(BadStrings[i]).getAsInteger(0, U64);
+ ASSERT_TRUE(IsBadNumber);
+ }
+}
+
+
+
} // end anonymous namespace
Modified: llvm/branches/R600/unittests/ExecutionEngine/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/ExecutionEngine/CMakeLists.txt?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/unittests/ExecutionEngine/CMakeLists.txt (original)
+++ llvm/branches/R600/unittests/ExecutionEngine/CMakeLists.txt Thu Oct 11 16:28:00 2012
@@ -7,3 +7,4 @@
)
add_subdirectory(JIT)
+add_subdirectory(MCJIT)
Modified: llvm/branches/R600/unittests/ExecutionEngine/JIT/JITTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/ExecutionEngine/JIT/JITTest.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/unittests/ExecutionEngine/JIT/JITTest.cpp (original)
+++ llvm/branches/R600/unittests/ExecutionEngine/JIT/JITTest.cpp Thu Oct 11 16:28:00 2012
@@ -224,6 +224,9 @@
OwningPtr<ExecutionEngine> TheJIT;
};
+// Tests on ARM disabled as we're running the old jit
+#if !defined(__arm__)
+
// Regression test for a bug. The JIT used to allocate globals inside the same
// memory block used for the function, and when the function code was freed,
// the global was left in the same place. This test allocates a function
@@ -292,6 +295,8 @@
EXPECT_EQ(3, *GPtr);
}
+#endif // !defined(__arm__)
+
int PlusOne(int arg) {
return arg + 1;
}
@@ -521,6 +526,9 @@
}
#endif // !ARM && !PPC
+// Tests on ARM disabled as we're running the old jit
+#if !defined(__arm__)
+
TEST_F(JITTest, FunctionPointersOutliveTheirCreator) {
TheJIT->DisableLazyCompilation(true);
LoadAssembly("define i8()* @get_foo_addr() { "
@@ -555,6 +563,8 @@
#endif
}
+#endif //!defined(__arm__)
+
// ARM does not have an implementation
// of replaceMachineCodeForFunction(), so recompileAndRelinkFunction
// doesn't work.
@@ -599,6 +609,9 @@
int32_t JITTest_AvailableExternallyGlobal = 42;
namespace {
+// Tests on ARM disabled as we're running the old jit
+#if !defined(__arm__)
+
TEST_F(JITTest, AvailableExternallyGlobalIsntEmitted) {
TheJIT->DisableLazyCompilation(true);
LoadAssembly("@JITTest_AvailableExternallyGlobal = "
@@ -615,7 +628,7 @@
EXPECT_EQ(42, loader()) << "func should return 42 from the external global,"
<< " not 7 from the IR version.";
}
-
+#endif //!defined(__arm__)
} // anonymous namespace
// This function is intentionally defined differently in the statically-compiled
// program from the IR input to the JIT to assert that the JIT doesn't use its
Added: llvm/branches/R600/unittests/ExecutionEngine/MCJIT/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/ExecutionEngine/MCJIT/CMakeLists.txt?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/unittests/ExecutionEngine/MCJIT/CMakeLists.txt (added)
+++ llvm/branches/R600/unittests/ExecutionEngine/MCJIT/CMakeLists.txt Thu Oct 11 16:28:00 2012
@@ -0,0 +1,25 @@
+set(LLVM_LINK_COMPONENTS
+ asmparser
+ bitreader
+ bitwriter
+ mcjit
+ jit
+ nativecodegen
+ )
+
+set(MCJITTestsSources
+ MCJITTest.cpp
+ SectionMemoryManager.cpp
+ )
+
+if(MSVC)
+ list(APPEND MCJITTestsSources MCJITTests.def)
+endif()
+
+add_llvm_unittest(MCJITTests
+ ${MCJITTestsSources}
+ )
+
+if(MINGW OR CYGWIN)
+ set_property(TARGET MCJITTests PROPERTY LINK_FLAGS -Wl,--export-all-symbols)
+endif()
Added: llvm/branches/R600/unittests/ExecutionEngine/MCJIT/MCJITTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/ExecutionEngine/MCJIT/MCJITTest.cpp?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/unittests/ExecutionEngine/MCJIT/MCJITTest.cpp (added)
+++ llvm/branches/R600/unittests/ExecutionEngine/MCJIT/MCJITTest.cpp Thu Oct 11 16:28:00 2012
@@ -0,0 +1,226 @@
+//===- MCJITTest.cpp - Unit tests for the MCJIT ---------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This test suite verifies basic MCJIT functionality such as making function
+// calls, using global variables, and compiling multpile modules.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/ExecutionEngine/MCJIT.h"
+#include "MCJITTestBase.h"
+#include "SectionMemoryManager.h"
+#include "gtest/gtest.h"
+
+using namespace llvm;
+
+class MCJITTest : public testing::Test, public MCJITTestBase {
+protected:
+
+ virtual void SetUp() {
+ M.reset(createEmptyModule("<main>"));
+ }
+};
+
+namespace {
+
+// FIXME: In order to JIT an empty module, there needs to be
+// an interface to ExecutionEngine that forces compilation but
+// does require retrieval of a pointer to a function/global.
+/*
+TEST_F(MCJITTest, empty_module) {
+ createJIT(M.take());
+ //EXPECT_NE(0, TheJIT->getObjectImage())
+ // << "Unable to generate executable loaded object image";
+}
+*/
+
+TEST_F(MCJITTest, global_variable) {
+ SKIP_UNSUPPORTED_PLATFORM;
+
+ int initialValue = 5;
+ GlobalValue *Global = insertGlobalInt32(M.get(), "test_global", initialValue);
+ createJIT(M.take());
+ void *globalPtr = TheJIT->getPointerToGlobal(Global);
+ EXPECT_TRUE(0 != globalPtr)
+ << "Unable to get pointer to global value from JIT";
+
+ EXPECT_EQ(initialValue, *(int32_t*)globalPtr)
+ << "Unexpected initial value of global";
+}
+
+TEST_F(MCJITTest, add_function) {
+ SKIP_UNSUPPORTED_PLATFORM;
+
+ Function *F = insertAddFunction(M.get());
+ createJIT(M.take());
+ void *addPtr = TheJIT->getPointerToFunction(F);
+ EXPECT_TRUE(0 != addPtr)
+ << "Unable to get pointer to function from JIT";
+
+ int (*AddPtrTy)(int, int) = (int(*)(int, int))(intptr_t)addPtr;
+ EXPECT_EQ(0, AddPtrTy(0, 0));
+ EXPECT_EQ(3, AddPtrTy(1, 2));
+ EXPECT_EQ(-5, AddPtrTy(-2, -3));
+}
+
+TEST_F(MCJITTest, run_main) {
+ SKIP_UNSUPPORTED_PLATFORM;
+
+ int rc = 6;
+ Function *Main = insertMainFunction(M.get(), 6);
+ createJIT(M.take());
+ void *vPtr = TheJIT->getPointerToFunction(Main);
+ EXPECT_TRUE(0 != vPtr)
+ << "Unable to get pointer to main() from JIT";
+
+ int (*FuncPtr)(void) = (int(*)(void))(intptr_t)vPtr;
+ int returnCode = FuncPtr();
+ EXPECT_EQ(returnCode, rc);
+}
+
+TEST_F(MCJITTest, return_global) {
+ SKIP_UNSUPPORTED_PLATFORM;
+
+ int32_t initialNum = 7;
+ GlobalVariable *GV = insertGlobalInt32(M.get(), "myglob", initialNum);
+
+ Function *ReturnGlobal = startFunction<int32_t(void)>(M.get(),
+ "ReturnGlobal");
+ Value *ReadGlobal = Builder.CreateLoad(GV);
+ endFunctionWithRet(ReturnGlobal, ReadGlobal);
+
+ createJIT(M.take());
+ void *rgvPtr = TheJIT->getPointerToFunction(ReturnGlobal);
+ EXPECT_TRUE(0 != rgvPtr);
+
+ int32_t(*FuncPtr)(void) = (int32_t(*)(void))(intptr_t)rgvPtr;
+ EXPECT_EQ(initialNum, FuncPtr())
+ << "Invalid value for global returned from JITted function";
+}
+
+// FIXME: This case fails due to a bug with getPointerToGlobal().
+// The bug is due to MCJIT not having an implementation of getPointerToGlobal()
+// which results in falling back on the ExecutionEngine implementation that
+// allocates a new memory block for the global instead of using the same
+// global variable that is emitted by MCJIT. Hence, the pointer (gvPtr below)
+// has the correct initial value, but updates to the real global (accessed by
+// JITted code) are not propagated. Instead, getPointerToGlobal() should return
+// a pointer into the loaded ObjectImage to reference the emitted global.
+/*
+TEST_F(MCJITTest, increment_global) {
+ SKIP_UNSUPPORTED_PLATFORM;
+
+ int32_t initialNum = 5;
+ Function *IncrementGlobal = startFunction<int32_t(void)>(M.get(), "IncrementGlobal");
+ GlobalVariable *GV = insertGlobalInt32(M.get(), "my_global", initialNum);
+ Value *DerefGV = Builder.CreateLoad(GV);
+ Value *AddResult = Builder.CreateAdd(DerefGV,
+ ConstantInt::get(Context, APInt(32, 1)));
+ Builder.CreateStore(AddResult, GV);
+ endFunctionWithRet(IncrementGlobal, AddResult);
+
+ createJIT(M.take());
+ void *gvPtr = TheJIT->getPointerToGlobal(GV);
+ EXPECT_EQ(initialNum, *(int32_t*)gvPtr);
+
+ void *vPtr = TheJIT->getPointerToFunction(IncrementGlobal);
+ EXPECT_TRUE(0 != vPtr)
+ << "Unable to get pointer to main() from JIT";
+
+ int32_t(*FuncPtr)(void) = (int32_t(*)(void))(intptr_t)vPtr;
+
+ for(int i = 1; i < 3; ++i) {
+ int32_t result = FuncPtr();
+ EXPECT_EQ(initialNum + i, result); // OK
+ EXPECT_EQ(initialNum + i, *(int32_t*)gvPtr); // FAILS
+ }
+}
+*/
+
+TEST_F(MCJITTest, multiple_functions) {
+ SKIP_UNSUPPORTED_PLATFORM;
+
+ unsigned int numLevels = 23;
+ int32_t innerRetVal= 5;
+
+ Function *Inner = startFunction<int32_t(void)>(M.get(), "Inner");
+ endFunctionWithRet(Inner, ConstantInt::get(Context, APInt(32, innerRetVal)));
+
+ Function *Outer;
+ for (unsigned int i = 0; i < numLevels; ++i) {
+ std::stringstream funcName;
+ funcName << "level_" << i;
+ Outer = startFunction<int32_t(void)>(M.get(), funcName.str());
+ Value *innerResult = Builder.CreateCall(Inner);
+ endFunctionWithRet(Outer, innerResult);
+
+ Inner = Outer;
+ }
+
+ createJIT(M.take());
+ void *vPtr = TheJIT->getPointerToFunction(Outer);
+ EXPECT_TRUE(0 != vPtr)
+ << "Unable to get pointer to outer function from JIT";
+
+ int32_t(*FuncPtr)(void) = (int32_t(*)(void))(intptr_t)vPtr;
+ EXPECT_EQ(innerRetVal, FuncPtr())
+ << "Incorrect result returned from function";
+}
+
+// FIXME: ExecutionEngine has no support empty modules
+/*
+TEST_F(MCJITTest, multiple_empty_modules) {
+ SKIP_UNSUPPORTED_PLATFORM;
+
+ createJIT(M.take());
+ // JIT-compile
+ EXPECT_NE(0, TheJIT->getObjectImage())
+ << "Unable to generate executable loaded object image";
+
+ TheJIT->addModule(createEmptyModule("<other module>"));
+ TheJIT->addModule(createEmptyModule("<other other module>"));
+
+ // JIT again
+ EXPECT_NE(0, TheJIT->getObjectImage())
+ << "Unable to generate executable loaded object image";
+}
+*/
+
+// FIXME: MCJIT must support multiple modules
+/*
+TEST_F(MCJITTest, multiple_modules) {
+ SKIP_UNSUPPORTED_PLATFORM;
+
+ Function *Callee = insertAddFunction(M.get());
+ createJIT(M.take());
+
+ // caller function is defined in a different module
+ M.reset(createEmptyModule("<caller module>"));
+
+ Function *CalleeRef = insertExternalReferenceToFunction(M.get(), Callee);
+ Function *Caller = insertSimpleCallFunction(M.get(), CalleeRef);
+
+ TheJIT->addModule(M.take());
+
+ // get a function pointer in a module that was not used in EE construction
+ void *vPtr = TheJIT->getPointerToFunction(Caller);
+ EXPECT_NE(0, vPtr)
+ << "Unable to get pointer to caller function from JIT";
+
+ int(*FuncPtr)(int, int) = (int(*)(int, int))(intptr_t)vPtr;
+ EXPECT_EQ(0, FuncPtr(0, 0));
+ EXPECT_EQ(30, FuncPtr(10, 20));
+ EXPECT_EQ(-30, FuncPtr(-10, -20));
+
+ // ensure caller is destroyed before callee (free use before def)
+ M.reset();
+}
+*/
+
+}
Added: llvm/branches/R600/unittests/ExecutionEngine/MCJIT/MCJITTestBase.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/ExecutionEngine/MCJIT/MCJITTestBase.h?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/unittests/ExecutionEngine/MCJIT/MCJITTestBase.h (added)
+++ llvm/branches/R600/unittests/ExecutionEngine/MCJIT/MCJITTestBase.h Thu Oct 11 16:28:00 2012
@@ -0,0 +1,245 @@
+//===- MCJITTestBase.h - Common base class for MCJIT Unit tests ----------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class implements common functionality required by the MCJIT unit tests,
+// as well as logic to skip tests on unsupported architectures and operating
+// systems.
+//
+//===----------------------------------------------------------------------===//
+
+
+#ifndef MCJIT_TEST_BASE_H
+#define MCJIT_TEST_BASE_H
+
+#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Config/config.h"
+#include "llvm/ExecutionEngine/ExecutionEngine.h"
+#include "llvm/Function.h"
+#include "llvm/IRBuilder.h"
+#include "llvm/LLVMContext.h"
+#include "llvm/Module.h"
+#include "llvm/Support/CodeGen.h"
+#include "llvm/Support/Host.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/TypeBuilder.h"
+
+#include "SectionMemoryManager.h"
+
+// Used to skip tests on unsupported architectures and operating systems.
+// To skip a test, add this macro at the top of a test-case in a suite that
+// inherits from MCJITTestBase. See MCJITTest.cpp for examples.
+#define SKIP_UNSUPPORTED_PLATFORM \
+ do \
+ if (!ArchSupportsMCJIT() || !OSSupportsMCJIT()) \
+ return; \
+ while(0);
+
+namespace llvm {
+
+class MCJITTestBase {
+protected:
+
+ MCJITTestBase()
+ : OptLevel(CodeGenOpt::None)
+ , RelocModel(Reloc::Default)
+ , CodeModel(CodeModel::Default)
+ , MArch("")
+ , Builder(Context)
+ , MM(new SectionMemoryManager)
+ , HostTriple(LLVM_HOSTTRIPLE)
+ {
+ InitializeNativeTarget();
+ InitializeNativeTargetAsmPrinter();
+
+#ifdef LLVM_ON_WIN32
+ // On Windows, generate ELF objects by specifying "-elf" in triple
+ HostTriple += "-elf";
+#endif // LLVM_ON_WIN32
+ HostTriple = Triple::normalize(HostTriple);
+
+ // The architectures below are known to be compatible with MCJIT as they
+ // are copied from test/ExecutionEngine/MCJIT/lit.local.cfg and should be
+ // kept in sync.
+ SupportedArchs.push_back(Triple::arm);
+ SupportedArchs.push_back(Triple::mips);
+ SupportedArchs.push_back(Triple::x86);
+ SupportedArchs.push_back(Triple::x86_64);
+
+ // The operating systems below are known to be incompatible with MCJIT as
+ // they are copied from the test/ExecutionEngine/MCJIT/lit.local.cfg and
+ // should be kept in sync.
+ UnsupportedOSs.push_back(Triple::Cygwin);
+ UnsupportedOSs.push_back(Triple::Darwin);
+ }
+
+ /// Returns true if the host architecture is known to support MCJIT
+ bool ArchSupportsMCJIT() {
+ Triple Host(HostTriple);
+ if (std::find(SupportedArchs.begin(), SupportedArchs.end(), Host.getArch())
+ == SupportedArchs.end()) {
+ return false;
+ }
+ return true;
+ }
+
+ /// Returns true if the host OS is known to support MCJIT
+ bool OSSupportsMCJIT() {
+ Triple Host(HostTriple);
+ if (std::find(UnsupportedOSs.begin(), UnsupportedOSs.end(), Host.getOS())
+ == UnsupportedOSs.end()) {
+ return true;
+ }
+ return false;
+ }
+
+ Module *createEmptyModule(StringRef Name) {
+ Module * M = new Module(Name, Context);
+ M->setTargetTriple(Triple::normalize(HostTriple));
+ return M;
+ }
+
+ template<typename FuncType>
+ Function *startFunction(Module *M, StringRef Name) {
+ Function *Result = Function::Create(
+ TypeBuilder<FuncType, false>::get(Context),
+ GlobalValue::ExternalLinkage, Name, M);
+
+ BasicBlock *BB = BasicBlock::Create(Context, Name, Result);
+ Builder.SetInsertPoint(BB);
+
+ return Result;
+ }
+
+ void endFunctionWithRet(Function *Func, Value *RetValue) {
+ Builder.CreateRet(RetValue);
+ }
+
+ // Inserts a simple function that invokes Callee and takes the same arguments:
+ // int Caller(...) { return Callee(...); }
+ template<typename Signature>
+ Function *insertSimpleCallFunction(Module *M, Function *Callee) {
+ Function *Result = startFunction<Signature>(M, "caller");
+
+ SmallVector<Value*, 1> CallArgs;
+
+ Function::arg_iterator arg_iter = Result->arg_begin();
+ for(;arg_iter != Result->arg_end(); ++arg_iter)
+ CallArgs.push_back(arg_iter);
+
+ Value *ReturnCode = Builder.CreateCall(Callee, CallArgs);
+ Builder.CreateRet(ReturnCode);
+ return Result;
+ }
+
+ // Inserts a function named 'main' that returns a uint32_t:
+ // int32_t main() { return X; }
+ // where X is given by returnCode
+ Function *insertMainFunction(Module *M, uint32_t returnCode) {
+ Function *Result = startFunction<int32_t(void)>(M, "main");
+
+ Value *ReturnVal = ConstantInt::get(Context, APInt(32, returnCode));
+ endFunctionWithRet(Result, ReturnVal);
+
+ return Result;
+ }
+
+ // Inserts a function
+ // int32_t add(int32_t a, int32_t b) { return a + b; }
+ // in the current module and returns a pointer to it.
+ Function *insertAddFunction(Module *M, StringRef Name = "add") {
+ Function *Result = startFunction<int32_t(int32_t, int32_t)>(M, Name);
+
+ Function::arg_iterator args = Result->arg_begin();
+ Value *Arg1 = args;
+ Value *Arg2 = ++args;
+ Value *AddResult = Builder.CreateAdd(Arg1, Arg2);
+
+ endFunctionWithRet(Result, AddResult);
+
+ return Result;
+ }
+
+ // Inserts an declaration to a function defined elsewhere
+ Function *insertExternalReferenceToFunction(Module *M, StringRef Name,
+ FunctionType *FuncTy) {
+ Function *Result = Function::Create(FuncTy,
+ GlobalValue::ExternalLinkage,
+ Name, M);
+ return Result;
+ }
+
+ // Inserts an declaration to a function defined elsewhere
+ Function *insertExternalReferenceToFunction(Module *M, Function *Func) {
+ Function *Result = Function::Create(Func->getFunctionType(),
+ GlobalValue::AvailableExternallyLinkage,
+ Func->getName(), M);
+ return Result;
+ }
+
+ // Inserts a global variable of type int32
+ GlobalVariable *insertGlobalInt32(Module *M,
+ StringRef name,
+ int32_t InitialValue) {
+ Type *GlobalTy = TypeBuilder<types::i<32>, true>::get(Context);
+ Constant *IV = ConstantInt::get(Context, APInt(32, InitialValue));
+ GlobalVariable *Global = new GlobalVariable(*M,
+ GlobalTy,
+ false,
+ GlobalValue::ExternalLinkage,
+ IV,
+ name);
+ return Global;
+ }
+
+ void createJIT(Module *M) {
+
+ // Due to the EngineBuilder constructor, it is required to have a Module
+ // in order to construct an ExecutionEngine (i.e. MCJIT)
+ assert(M != 0 && "a non-null Module must be provided to create MCJIT");
+
+ EngineBuilder EB(M);
+ std::string Error;
+ TheJIT.reset(EB.setEngineKind(EngineKind::JIT)
+ .setUseMCJIT(true) /* can this be folded into the EngineKind enum? */
+ .setJITMemoryManager(MM)
+ .setErrorStr(&Error)
+ .setOptLevel(CodeGenOpt::None)
+ .setAllocateGVsWithCode(false) /*does this do anything?*/
+ .setCodeModel(CodeModel::JITDefault)
+ .setRelocationModel(Reloc::Default)
+ .setMArch(MArch)
+ .setMCPU(sys::getHostCPUName())
+ //.setMAttrs(MAttrs)
+ .create());
+ // At this point, we cannot modify the module any more.
+ assert(TheJIT.get() != NULL && "error creating MCJIT with EngineBuilder");
+ }
+
+ LLVMContext Context;
+ CodeGenOpt::Level OptLevel;
+ Reloc::Model RelocModel;
+ CodeModel::Model CodeModel;
+ StringRef MArch;
+ SmallVector<std::string, 1> MAttrs;
+ OwningPtr<TargetMachine> TM;
+ OwningPtr<ExecutionEngine> TheJIT;
+ IRBuilder<> Builder;
+ JITMemoryManager *MM;
+
+ std::string HostTriple;
+ SmallVector<Triple::ArchType, 4> SupportedArchs;
+ SmallVector<Triple::OSType, 4> UnsupportedOSs;
+
+ OwningPtr<Module> M;
+};
+
+} // namespace llvm
+
+#endif // MCJIT_TEST_H
Added: llvm/branches/R600/unittests/ExecutionEngine/MCJIT/MCJITTests.def
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/ExecutionEngine/MCJIT/MCJITTests.def?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/unittests/ExecutionEngine/MCJIT/MCJITTests.def (added)
+++ llvm/branches/R600/unittests/ExecutionEngine/MCJIT/MCJITTests.def Thu Oct 11 16:28:00 2012
@@ -0,0 +1 @@
+EXPORTS
Copied: llvm/branches/R600/unittests/ExecutionEngine/MCJIT/Makefile (from r165622, llvm/branches/R600/unittests/ExecutionEngine/Makefile)
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/ExecutionEngine/MCJIT/Makefile?p2=llvm/branches/R600/unittests/ExecutionEngine/MCJIT/Makefile&p1=llvm/branches/R600/unittests/ExecutionEngine/Makefile&r1=165622&r2=165748&rev=165748&view=diff
==============================================================================
--- llvm/branches/R600/unittests/ExecutionEngine/Makefile (original)
+++ llvm/branches/R600/unittests/ExecutionEngine/MCJIT/Makefile Thu Oct 11 16:28:00 2012
@@ -1,4 +1,4 @@
-##===- unittests/ExecutionEngine/Makefile ------------------*- Makefile -*-===##
+##===- unittests/ExecutionEngine/MCJIT/Makefile ------------*- Makefile -*-===##
#
# The LLVM Compiler Infrastructure
#
@@ -7,10 +7,12 @@
#
##===----------------------------------------------------------------------===##
-LEVEL = ../..
-TESTNAME = ExecutionEngine
-LINK_COMPONENTS :=interpreter
-PARALLEL_DIRS = JIT
+LEVEL = ../../..
+TESTNAME = MCJIT
+LINK_COMPONENTS := core jit mcjit native support
include $(LEVEL)/Makefile.config
include $(LLVM_SRC_ROOT)/unittests/Makefile.unittest
+
+# Permit these tests to use the MCJIT's symbolic lookup.
+LD.Flags += $(RDYNAMIC)
Added: llvm/branches/R600/unittests/ExecutionEngine/MCJIT/SectionMemoryManager.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/ExecutionEngine/MCJIT/SectionMemoryManager.cpp?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/unittests/ExecutionEngine/MCJIT/SectionMemoryManager.cpp (added)
+++ llvm/branches/R600/unittests/ExecutionEngine/MCJIT/SectionMemoryManager.cpp Thu Oct 11 16:28:00 2012
@@ -0,0 +1,135 @@
+//===-- SectionMemoryManager.cpp - The memory manager for MCJIT -----------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the implementation of the section-based memory manager
+// used by MCJIT.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Config/config.h"
+#include "llvm/Support/DynamicLibrary.h"
+
+#include "SectionMemoryManager.h"
+
+#ifdef __linux__
+// These includes used by SectionMemoryManager::getPointerToNamedFunction()
+// for Glibc trickery. Look comments in this function for more information.
+#ifdef HAVE_SYS_STAT_H
+#include <sys/stat.h>
+#endif
+#include <fcntl.h>
+#include <unistd.h>
+#endif
+
+namespace llvm {
+
+uint8_t *SectionMemoryManager::allocateDataSection(uintptr_t Size,
+ unsigned Alignment,
+ unsigned SectionID) {
+ if (!Alignment)
+ Alignment = 16;
+ uint8_t *Addr = (uint8_t*)calloc((Size + Alignment - 1)/Alignment, Alignment);
+ AllocatedDataMem.push_back(sys::MemoryBlock(Addr, Size));
+ return Addr;
+}
+
+uint8_t *SectionMemoryManager::allocateCodeSection(uintptr_t Size,
+ unsigned Alignment,
+ unsigned SectionID) {
+ if (!Alignment)
+ Alignment = 16;
+ unsigned NeedAllocate = Alignment * ((Size + Alignment - 1)/Alignment + 1);
+ uintptr_t Addr = 0;
+ // Look in the list of free code memory regions and use a block there if one
+ // is available.
+ for (int i = 0, e = FreeCodeMem.size(); i != e; ++i) {
+ sys::MemoryBlock &MB = FreeCodeMem[i];
+ if (MB.size() >= NeedAllocate) {
+ Addr = (uintptr_t)MB.base();
+ uintptr_t EndOfBlock = Addr + MB.size();
+ // Align the address.
+ Addr = (Addr + Alignment - 1) & ~(uintptr_t)(Alignment - 1);
+ // Store cutted free memory block.
+ FreeCodeMem[i] = sys::MemoryBlock((void*)(Addr + Size),
+ EndOfBlock - Addr - Size);
+ return (uint8_t*)Addr;
+ }
+ }
+
+ // No pre-allocated free block was large enough. Allocate a new memory region.
+ sys::MemoryBlock MB = sys::Memory::AllocateRWX(NeedAllocate, 0, 0);
+
+ AllocatedCodeMem.push_back(MB);
+ Addr = (uintptr_t)MB.base();
+ uintptr_t EndOfBlock = Addr + MB.size();
+ // Align the address.
+ Addr = (Addr + Alignment - 1) & ~(uintptr_t)(Alignment - 1);
+ // The AllocateRWX may allocate much more memory than we need. In this case,
+ // we store the unused memory as a free memory block.
+ unsigned FreeSize = EndOfBlock-Addr-Size;
+ if (FreeSize > 16)
+ FreeCodeMem.push_back(sys::MemoryBlock((void*)(Addr + Size), FreeSize));
+
+ // Return aligned address
+ return (uint8_t*)Addr;
+}
+
+void SectionMemoryManager::invalidateInstructionCache() {
+ for (int i = 0, e = AllocatedCodeMem.size(); i != e; ++i)
+ sys::Memory::InvalidateInstructionCache(AllocatedCodeMem[i].base(),
+ AllocatedCodeMem[i].size());
+}
+
+void *SectionMemoryManager::getPointerToNamedFunction(const std::string &Name,
+ bool AbortOnFailure) {
+#if defined(__linux__)
+ //===--------------------------------------------------------------------===//
+ // Function stubs that are invoked instead of certain library calls
+ //
+ // Force the following functions to be linked in to anything that uses the
+ // JIT. This is a hack designed to work around the all-too-clever Glibc
+ // strategy of making these functions work differently when inlined vs. when
+ // not inlined, and hiding their real definitions in a separate archive file
+ // that the dynamic linker can't see. For more info, search for
+ // 'libc_nonshared.a' on Google, or read http://llvm.org/PR274.
+ if (Name == "stat") return (void*)(intptr_t)&stat;
+ if (Name == "fstat") return (void*)(intptr_t)&fstat;
+ if (Name == "lstat") return (void*)(intptr_t)&lstat;
+ if (Name == "stat64") return (void*)(intptr_t)&stat64;
+ if (Name == "fstat64") return (void*)(intptr_t)&fstat64;
+ if (Name == "lstat64") return (void*)(intptr_t)&lstat64;
+ if (Name == "atexit") return (void*)(intptr_t)&atexit;
+ if (Name == "mknod") return (void*)(intptr_t)&mknod;
+#endif // __linux__
+
+ const char *NameStr = Name.c_str();
+ void *Ptr = sys::DynamicLibrary::SearchForAddressOfSymbol(NameStr);
+ if (Ptr) return Ptr;
+
+ // If it wasn't found and if it starts with an underscore ('_') character,
+ // try again without the underscore.
+ if (NameStr[0] == '_') {
+ Ptr = sys::DynamicLibrary::SearchForAddressOfSymbol(NameStr+1);
+ if (Ptr) return Ptr;
+ }
+
+ if (AbortOnFailure)
+ report_fatal_error("Program used external function '" + Name +
+ "' which could not be resolved!");
+ return 0;
+}
+
+SectionMemoryManager::~SectionMemoryManager() {
+ for (unsigned i = 0, e = AllocatedCodeMem.size(); i != e; ++i)
+ sys::Memory::ReleaseRWX(AllocatedCodeMem[i]);
+ for (unsigned i = 0, e = AllocatedDataMem.size(); i != e; ++i)
+ free(AllocatedDataMem[i].base());
+}
+
+} // namespace llvm
Added: llvm/branches/R600/unittests/ExecutionEngine/MCJIT/SectionMemoryManager.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/ExecutionEngine/MCJIT/SectionMemoryManager.h?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/unittests/ExecutionEngine/MCJIT/SectionMemoryManager.h (added)
+++ llvm/branches/R600/unittests/ExecutionEngine/MCJIT/SectionMemoryManager.h Thu Oct 11 16:28:00 2012
@@ -0,0 +1,117 @@
+//===-- SectionMemoryManager.h - Memory allocator for MCJIT -----*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the declaration of a section-based memory manager used by
+// the MCJIT execution engine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_EXECUTION_ENGINE_SECTION_MEMORY_MANAGER_H
+#define LLVM_EXECUTION_ENGINE_SECTION_MEMORY_MANAGER_H
+
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ExecutionEngine/JITMemoryManager.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/Memory.h"
+
+namespace llvm {
+
+// Section-based memory manager for MCJIT
+class SectionMemoryManager : public JITMemoryManager {
+
+public:
+
+ SectionMemoryManager() { }
+ ~SectionMemoryManager();
+
+ virtual uint8_t *allocateCodeSection(uintptr_t Size, unsigned Alignment,
+ unsigned SectionID);
+
+ virtual uint8_t *allocateDataSection(uintptr_t Size, unsigned Alignment,
+ unsigned SectionID);
+
+ virtual void *getPointerToNamedFunction(const std::string &Name,
+ bool AbortOnFailure = true);
+
+ // Invalidate instruction cache for code sections. Some platforms with
+ // separate data cache and instruction cache require explicit cache flush,
+ // otherwise JIT code manipulations (like resolved relocations) will get to
+ // the data cache but not to the instruction cache.
+ virtual void invalidateInstructionCache();
+
+private:
+
+ SmallVector<sys::MemoryBlock, 16> AllocatedDataMem;
+ SmallVector<sys::MemoryBlock, 16> AllocatedCodeMem;
+ SmallVector<sys::MemoryBlock, 16> FreeCodeMem;
+
+public:
+ ///
+ /// Functions below are not used by MCJIT, but must be implemented because
+ /// they are declared as pure virtuals in the base class.
+ ///
+
+ virtual void setMemoryWritable() {
+ llvm_unreachable("Unexpected call!");
+ }
+ virtual void setMemoryExecutable() {
+ llvm_unreachable("Unexpected call!");
+ }
+ virtual void setPoisonMemory(bool poison) {
+ llvm_unreachable("Unexpected call!");
+ }
+ virtual void AllocateGOT() {
+ llvm_unreachable("Unexpected call!");
+ }
+ virtual uint8_t *getGOTBase() const {
+ llvm_unreachable("Unexpected call!");
+ return 0;
+ }
+ virtual uint8_t *startFunctionBody(const Function *F,
+ uintptr_t &ActualSize){
+ llvm_unreachable("Unexpected call!");
+ return 0;
+ }
+ virtual uint8_t *allocateStub(const GlobalValue* F, unsigned StubSize,
+ unsigned Alignment) {
+ llvm_unreachable("Unexpected call!");
+ return 0;
+ }
+ virtual void endFunctionBody(const Function *F, uint8_t *FunctionStart,
+ uint8_t *FunctionEnd) {
+ llvm_unreachable("Unexpected call!");
+ }
+ virtual uint8_t *allocateSpace(intptr_t Size, unsigned Alignment) {
+ llvm_unreachable("Unexpected call!");
+ return 0;
+ }
+ virtual uint8_t *allocateGlobal(uintptr_t Size, unsigned Alignment) {
+ llvm_unreachable("Unexpected call!");
+ return 0;
+ }
+ virtual void deallocateFunctionBody(void *Body) {
+ llvm_unreachable("Unexpected call!");
+ }
+ virtual uint8_t *startExceptionTable(const Function *F,
+ uintptr_t &ActualSize) {
+ llvm_unreachable("Unexpected call!");
+ return 0;
+ }
+ virtual void endExceptionTable(const Function *F, uint8_t *TableStart,
+ uint8_t *TableEnd, uint8_t *FrameRegister) {
+ llvm_unreachable("Unexpected call!");
+ }
+ virtual void deallocateExceptionTable(void *ET) {
+ llvm_unreachable("Unexpected call!");
+ }
+};
+
+}
+
+#endif // LLVM_EXECUTION_ENGINE_SECTION_MEMORY_MANAGER_H
Modified: llvm/branches/R600/unittests/ExecutionEngine/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/ExecutionEngine/Makefile?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/unittests/ExecutionEngine/Makefile (original)
+++ llvm/branches/R600/unittests/ExecutionEngine/Makefile Thu Oct 11 16:28:00 2012
@@ -10,7 +10,7 @@
LEVEL = ../..
TESTNAME = ExecutionEngine
LINK_COMPONENTS :=interpreter
-PARALLEL_DIRS = JIT
+PARALLEL_DIRS = JIT MCJIT
include $(LEVEL)/Makefile.config
include $(LLVM_SRC_ROOT)/unittests/Makefile.unittest
Modified: llvm/branches/R600/unittests/Support/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/Support/CMakeLists.txt?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/unittests/Support/CMakeLists.txt (original)
+++ llvm/branches/R600/unittests/Support/CMakeLists.txt Thu Oct 11 16:28:00 2012
@@ -17,6 +17,7 @@
LeakDetectorTest.cpp
ManagedStatic.cpp
MathExtrasTest.cpp
+ MemoryBufferTest.cpp
MemoryTest.cpp
Path.cpp
RegexTest.cpp
Added: llvm/branches/R600/unittests/Support/MemoryBufferTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/Support/MemoryBufferTest.cpp?rev=165748&view=auto
==============================================================================
--- llvm/branches/R600/unittests/Support/MemoryBufferTest.cpp (added)
+++ llvm/branches/R600/unittests/Support/MemoryBufferTest.cpp Thu Oct 11 16:28:00 2012
@@ -0,0 +1,99 @@
+//===- llvm/unittest/Support/MemoryBufferTest.cpp - MemoryBuffer tests ----===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements unit tests for the MemoryBuffer support class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Support/MemoryBuffer.h"
+#include "llvm/ADT/OwningPtr.h"
+
+#include "gtest/gtest.h"
+
+using namespace llvm;
+
+class MemoryBufferTest : public testing::Test {
+protected:
+ MemoryBufferTest()
+ : data("this is some data")
+ { }
+
+ virtual void SetUp() { }
+
+ typedef OwningPtr<MemoryBuffer> OwningBuffer;
+
+ std::string data;
+};
+
+namespace {
+
+TEST_F(MemoryBufferTest, get) {
+ // Default name and null-terminator flag
+ OwningBuffer MB1(MemoryBuffer::getMemBuffer(data));
+ EXPECT_TRUE(0 != MB1.get());
+
+ // RequiresNullTerminator = false
+ OwningBuffer MB2(MemoryBuffer::getMemBuffer(data, "one", false));
+ EXPECT_TRUE(0 != MB2.get());
+
+ // RequiresNullTerminator = true
+ OwningBuffer MB3(MemoryBuffer::getMemBuffer(data, "two", true));
+ EXPECT_TRUE(0 != MB3.get());
+
+ // verify all 3 buffers point to the same address
+ EXPECT_EQ(MB1->getBufferStart(), MB2->getBufferStart());
+ EXPECT_EQ(MB2->getBufferStart(), MB3->getBufferStart());
+
+ // verify the original data is unmodified after deleting the buffers
+ MB1.reset();
+ MB2.reset();
+ MB3.reset();
+ EXPECT_EQ("this is some data", data);
+}
+
+TEST_F(MemoryBufferTest, copy) {
+ // copy with no name
+ OwningBuffer MBC1(MemoryBuffer::getMemBufferCopy(data));
+ EXPECT_TRUE(0 != MBC1.get());
+
+ // copy with a name
+ OwningBuffer MBC2(MemoryBuffer::getMemBufferCopy(data, "copy"));
+ EXPECT_TRUE(0 != MBC2.get());
+
+ // verify the two copies do not point to the same place
+ EXPECT_NE(MBC1->getBufferStart(), MBC2->getBufferStart());
+}
+
+TEST_F(MemoryBufferTest, make_new) {
+ // 0-sized buffer
+ OwningBuffer Zero(MemoryBuffer::getNewUninitMemBuffer(0));
+ EXPECT_TRUE(0 != Zero.get());
+
+ // uninitialized buffer with no name
+ OwningBuffer One(MemoryBuffer::getNewUninitMemBuffer(321));
+ EXPECT_TRUE(0 != One.get());
+
+ // uninitialized buffer with name
+ OwningBuffer Two(MemoryBuffer::getNewUninitMemBuffer(123, "bla"));
+ EXPECT_TRUE(0 != Two.get());
+
+ // 0-initialized buffer with no name
+ OwningBuffer Three(MemoryBuffer::getNewMemBuffer(321, data));
+ EXPECT_TRUE(0 != Three.get());
+ for (size_t i = 0; i < 321; ++i)
+ EXPECT_EQ(0, Three->getBufferStart()[0]);
+
+ // 0-initialized buffer with name
+ OwningBuffer Four(MemoryBuffer::getNewMemBuffer(123, "zeros"));
+ EXPECT_TRUE(0 != Four.get());
+ for (size_t i = 0; i < 123; ++i)
+ EXPECT_EQ(0, Four->getBufferStart()[0]);
+}
+
+}
Modified: llvm/branches/R600/unittests/VMCore/InstructionsTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/VMCore/InstructionsTest.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/unittests/VMCore/InstructionsTest.cpp (original)
+++ llvm/branches/R600/unittests/VMCore/InstructionsTest.cpp Thu Oct 11 16:28:00 2012
@@ -9,6 +9,7 @@
#include "llvm/BasicBlock.h"
#include "llvm/Constants.h"
+#include "llvm/DataLayout.h"
#include "llvm/DerivedTypes.h"
#include "llvm/IRBuilder.h"
#include "llvm/Instructions.h"
@@ -17,7 +18,6 @@
#include "llvm/Operator.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Analysis/ValueTracking.h"
-#include "llvm/Target/TargetData.h"
#include "gtest/gtest.h"
namespace llvm {
@@ -183,7 +183,7 @@
EXPECT_NE(S3, Gep3);
int64_t Offset;
- TargetData TD("e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3"
+ DataLayout TD("e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3"
"2:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80"
":128:128-n8:16:32:64-S128");
// Make sure we don't crash
Modified: llvm/branches/R600/unittests/VMCore/PassManagerTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/unittests/VMCore/PassManagerTest.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/unittests/VMCore/PassManagerTest.cpp (original)
+++ llvm/branches/R600/unittests/VMCore/PassManagerTest.cpp Thu Oct 11 16:28:00 2012
@@ -14,7 +14,7 @@
#include "llvm/Pass.h"
#include "llvm/Analysis/LoopPass.h"
#include "llvm/CallGraphSCCPass.h"
-#include "llvm/Target/TargetData.h"
+#include "llvm/DataLayout.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Constants.h"
@@ -94,7 +94,7 @@
initializeModuleNDMPass(*PassRegistry::getPassRegistry());
}
virtual bool runOnModule(Module &M) {
- EXPECT_TRUE(getAnalysisIfAvailable<TargetData>());
+ EXPECT_TRUE(getAnalysisIfAvailable<DataLayout>());
run++;
return false;
}
@@ -167,7 +167,7 @@
initializeCGPassPass(*PassRegistry::getPassRegistry());
}
virtual bool runOnSCC(CallGraphSCC &SCMM) {
- EXPECT_TRUE(getAnalysisIfAvailable<TargetData>());
+ EXPECT_TRUE(getAnalysisIfAvailable<DataLayout>());
run();
return false;
}
@@ -177,7 +177,7 @@
public:
virtual bool runOnFunction(Function &F) {
// FIXME: PR4112
- // EXPECT_TRUE(getAnalysisIfAvailable<TargetData>());
+ // EXPECT_TRUE(getAnalysisIfAvailable<DataLayout>());
run();
return false;
}
@@ -204,7 +204,7 @@
return false;
}
virtual bool runOnLoop(Loop *L, LPPassManager &LPM) {
- EXPECT_TRUE(getAnalysisIfAvailable<TargetData>());
+ EXPECT_TRUE(getAnalysisIfAvailable<DataLayout>());
run();
return false;
}
@@ -241,7 +241,7 @@
return false;
}
virtual bool runOnBasicBlock(BasicBlock &BB) {
- EXPECT_TRUE(getAnalysisIfAvailable<TargetData>());
+ EXPECT_TRUE(getAnalysisIfAvailable<DataLayout>());
run();
return false;
}
@@ -266,7 +266,7 @@
initializeFPassPass(*PassRegistry::getPassRegistry());
}
virtual bool runOnModule(Module &M) {
- EXPECT_TRUE(getAnalysisIfAvailable<TargetData>());
+ EXPECT_TRUE(getAnalysisIfAvailable<DataLayout>());
for (Module::iterator I=M.begin(),E=M.end(); I != E; ++I) {
Function &F = *I;
{
@@ -292,7 +292,7 @@
mNDM->run = mNDNM->run = mDNM->run = mNDM2->run = 0;
PassManager Passes;
- Passes.add(new TargetData(&M));
+ Passes.add(new DataLayout(&M));
Passes.add(mNDM2);
Passes.add(mNDM);
Passes.add(mNDNM);
@@ -316,7 +316,7 @@
mNDM->run = mNDNM->run = mDNM->run = mNDM2->run = 0;
PassManager Passes;
- Passes.add(new TargetData(&M));
+ Passes.add(new DataLayout(&M));
Passes.add(mNDM);
Passes.add(mNDNM);
Passes.add(mNDM2);// invalidates mNDM needed by mDNM
@@ -338,7 +338,7 @@
OwningPtr<Module> M(makeLLVMModule());
T *P = new T();
PassManager Passes;
- Passes.add(new TargetData(M.get()));
+ Passes.add(new DataLayout(M.get()));
Passes.add(P);
Passes.run(*M);
T::finishedOK(run);
@@ -349,7 +349,7 @@
Module *M = makeLLVMModule();
T *P = new T();
PassManager Passes;
- Passes.add(new TargetData(M));
+ Passes.add(new DataLayout(M));
Passes.add(P);
Passes.run(*M);
T::finishedOK(run, N);
@@ -387,7 +387,7 @@
SCOPED_TRACE("Running OnTheFlyTest");
struct OnTheFlyTest *O = new OnTheFlyTest();
PassManager Passes;
- Passes.add(new TargetData(M));
+ Passes.add(new DataLayout(M));
Passes.add(O);
Passes.run(*M);
Modified: llvm/branches/R600/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/utils/TableGen/AsmMatcherEmitter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/branches/R600/utils/TableGen/AsmMatcherEmitter.cpp Thu Oct 11 16:28:00 2012
@@ -1716,9 +1716,9 @@
OpOS << "void " << Target.getName() << ClassName << "::\n"
<< "convertToMapAndConstraints(unsigned Kind,\n";
OpOS.indent(27);
- OpOS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
- << " SmallVectorImpl<std::pair< unsigned, std::string > >"
- << " &MapAndConstraints) {\n"
+ OpOS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
+ OpOS.indent(27);
+ OpOS << "MatchInstMapAndConstraintsImpl &MapAndConstraints) {\n"
<< " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
<< " unsigned NumMCOperands = 0;\n"
<< " const uint8_t *Converter = ConversionTable[Kind];\n"
@@ -1728,7 +1728,7 @@
<< " case CVT_Reg:\n"
<< " case CVT_Tied:\n"
<< " MapAndConstraints.push_back(std::make_pair(NumMCOperands,"
- << "\"r\"));\n"
+ << "\"m\"));\n"
<< " ++NumMCOperands;\n"
<< " break;\n";
@@ -1826,7 +1826,7 @@
// Add a handler for the operand number lookup.
OpOS << " case " << Name << ":\n"
<< " MapAndConstraints.push_back(std::make_pair(NumMCOperands"
- << ",\"r\"));\n"
+ << ",\"m\"));\n"
<< " NumMCOperands += " << OpInfo.MINumOperands << ";\n"
<< " break;\n";
break;
@@ -1896,7 +1896,7 @@
OpOS << " case " << Name << ":\n"
<< " MapAndConstraints.push_back(std::make_pair(NumMCOperands"
- << ",\"r\"));\n"
+ << ",\"m\"));\n"
<< " ++NumMCOperands;\n"
<< " break;\n";
}
@@ -2606,15 +2606,16 @@
<< " const SmallVectorImpl<MCParsedAsmOperand*> "
<< "&Operands);\n";
OS << " void convertToMapAndConstraints(unsigned Kind,\n ";
- OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
- << " SmallVectorImpl<std::pair< unsigned, std::string > >"
- << " &MapAndConstraints);\n";
+ OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n";
+ OS.indent(29);
+ OS << "MatchInstMapAndConstraintsImpl &MapAndConstraints);\n";
OS << " bool mnemonicIsValid(StringRef Mnemonic);\n";
- OS << " unsigned MatchInstructionImpl(\n"
- << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
- << " unsigned &Kind, MCInst &Inst,\n"
- << " SmallVectorImpl<std::pair< unsigned, std::string > > "
- << "&MapAndConstraints,\n"
+ OS << " unsigned MatchInstructionImpl(\n";
+ OS.indent(27);
+ OS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"
+ << " unsigned &Kind, MCInst &Inst,\n";
+ OS.indent(30);
+ OS << "MatchInstMapAndConstraintsImpl &MapAndConstraints,\n"
<< " unsigned &ErrorInfo,"
<< " bool matchingInlineAsm,\n"
<< " unsigned VariantID = 0);\n";
Modified: llvm/branches/R600/utils/TableGen/CallingConvEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/utils/TableGen/CallingConvEmitter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/utils/TableGen/CallingConvEmitter.cpp (original)
+++ llvm/branches/R600/utils/TableGen/CallingConvEmitter.cpp Thu Oct 11 16:28:00 2012
@@ -177,12 +177,12 @@
if (Size)
O << Size << ", ";
else
- O << "\n" << IndentStr << " State.getTarget().getTargetData()"
+ O << "\n" << IndentStr << " State.getTarget().getDataLayout()"
"->getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), ";
if (Align)
O << Align;
else
- O << "\n" << IndentStr << " State.getTarget().getTargetData()"
+ O << "\n" << IndentStr << " State.getTarget().getDataLayout()"
"->getABITypeAlignment(EVT(LocVT).getTypeForEVT(State.getContext()))";
if (Action->isSubClassOf("CCAssignToStackWithShadow"))
O << ", " << getQualifiedName(Action->getValueAsDef("ShadowReg"));
Modified: llvm/branches/R600/utils/TableGen/CodeGenSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/utils/TableGen/CodeGenSchedule.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/utils/TableGen/CodeGenSchedule.cpp (original)
+++ llvm/branches/R600/utils/TableGen/CodeGenSchedule.cpp Thu Oct 11 16:28:00 2012
@@ -18,6 +18,8 @@
#include "CodeGenTarget.h"
#include "llvm/TableGen/Error.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/Regex.h"
+#include "llvm/ADT/STLExtras.h"
using namespace llvm;
@@ -34,11 +36,64 @@
}
#endif
+// (instrs a, b, ...) Evaluate and union all arguments. Identical to AddOp.
+struct InstrsOp : public SetTheory::Operator {
+ void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts) {
+ ST.evaluate(Expr->arg_begin(), Expr->arg_end(), Elts);
+ }
+};
+
+// (instregex "OpcPat",...) Find all instructions matching an opcode pattern.
+//
+// TODO: Since this is a prefix match, perform a binary search over the
+// instruction names using lower_bound. Note that the predefined instrs must be
+// scanned linearly first. However, this is only safe if the regex pattern has
+// no top-level bars. The DAG already has a list of patterns, so there's no
+// reason to use top-level bars, but we need a way to verify they don't exist
+// before implementing the optimization.
+struct InstRegexOp : public SetTheory::Operator {
+ const CodeGenTarget &Target;
+ InstRegexOp(const CodeGenTarget &t): Target(t) {}
+
+ void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts) {
+ SmallVector<Regex*, 4> RegexList;
+ for (DagInit::const_arg_iterator
+ AI = Expr->arg_begin(), AE = Expr->arg_end(); AI != AE; ++AI) {
+ StringInit *SI = dynamic_cast<StringInit*>(*AI);
+ if (!SI)
+ throw "instregex requires pattern string: " + Expr->getAsString();
+ std::string pat = SI->getValue();
+ // Implement a python-style prefix match.
+ if (pat[0] != '^') {
+ pat.insert(0, "^(");
+ pat.insert(pat.end(), ')');
+ }
+ RegexList.push_back(new Regex(pat));
+ }
+ for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
+ E = Target.inst_end(); I != E; ++I) {
+ for (SmallVectorImpl<Regex*>::iterator
+ RI = RegexList.begin(), RE = RegexList.end(); RI != RE; ++RI) {
+ if ((*RI)->match((*I)->TheDef->getName()))
+ Elts.insert((*I)->TheDef);
+ }
+ }
+ DeleteContainerPointers(RegexList);
+ }
+};
+
/// CodeGenModels ctor interprets machine model records and populates maps.
CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK,
const CodeGenTarget &TGT):
Records(RK), Target(TGT), NumItineraryClasses(0) {
+ Sets.addFieldExpander("InstRW", "Instrs");
+
+ // Allow Set evaluation to recognize the dags used in InstRW records:
+ // (instrs Op1, Op1...)
+ Sets.addOperator("instrs", new InstrsOp);
+ Sets.addOperator("instregex", new InstRegexOp(Target));
+
// Instantiate a CodeGenProcModel for each SchedMachineModel with the values
// that are explicitly referenced in tablegen records. Resources associated
// with each processor will be derived later. Populate ProcModelMap with the
@@ -72,9 +127,6 @@
// Infer new SchedClasses from SchedVariant.
inferSchedClasses();
- DEBUG(for (unsigned i = 0; i < SchedClasses.size(); ++i)
- SchedClasses[i].dump(this));
-
// Populate each CodeGenProcModel's WriteResDefs, ReadAdvanceDefs, and
// ProcResourceDefs.
collectProcResources();
@@ -228,12 +280,12 @@
std::sort(SWDefs.begin(), SWDefs.end(), LessRecord());
for (RecIter SWI = SWDefs.begin(), SWE = SWDefs.end(); SWI != SWE; ++SWI) {
assert(!getSchedRWIdx(*SWI, /*IsRead=*/false) && "duplicate SchedWrite");
- SchedWrites.push_back(CodeGenSchedRW(*SWI));
+ SchedWrites.push_back(CodeGenSchedRW(SchedWrites.size(), *SWI));
}
std::sort(SRDefs.begin(), SRDefs.end(), LessRecord());
for (RecIter SRI = SRDefs.begin(), SRE = SRDefs.end(); SRI != SRE; ++SRI) {
assert(!getSchedRWIdx(*SRI, /*IsRead-*/true) && "duplicate SchedWrite");
- SchedReads.push_back(CodeGenSchedRW(*SRI));
+ SchedReads.push_back(CodeGenSchedRW(SchedReads.size(), *SRI));
}
// Initialize WriteSequence vectors.
for (std::vector<CodeGenSchedRW>::iterator WI = SchedWrites.begin(),
@@ -365,6 +417,47 @@
}
}
+// Expand a SchedWrite as a sequence following any aliases that coincide with
+// the given processor model.
+void CodeGenSchedModels::expandRWSeqForProc(
+ unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
+ const CodeGenProcModel &ProcModel) const {
+
+ const CodeGenSchedRW &SchedWrite = getSchedRW(RWIdx, IsRead);
+ Record *AliasDef = 0;
+ for (RecIter AI = SchedWrite.Aliases.begin(), AE = SchedWrite.Aliases.end();
+ AI != AE; ++AI) {
+ const CodeGenSchedRW &AliasRW = getSchedRW((*AI)->getValueAsDef("AliasRW"));
+ if ((*AI)->getValueInit("SchedModel")->isComplete()) {
+ Record *ModelDef = (*AI)->getValueAsDef("SchedModel");
+ if (&getProcModel(ModelDef) != &ProcModel)
+ continue;
+ }
+ if (AliasDef)
+ throw TGError(AliasRW.TheDef->getLoc(), "Multiple aliases "
+ "defined for processor " + ProcModel.ModelName +
+ " Ensure only one SchedAlias exists per RW.");
+ AliasDef = AliasRW.TheDef;
+ }
+ if (AliasDef) {
+ expandRWSeqForProc(getSchedRWIdx(AliasDef, IsRead),
+ RWSeq, IsRead,ProcModel);
+ return;
+ }
+ if (!SchedWrite.IsSequence) {
+ RWSeq.push_back(RWIdx);
+ return;
+ }
+ int Repeat =
+ SchedWrite.TheDef ? SchedWrite.TheDef->getValueAsInt("Repeat") : 1;
+ for (int i = 0; i < Repeat; ++i) {
+ for (IdxIter I = SchedWrite.Sequence.begin(), E = SchedWrite.Sequence.end();
+ I != E; ++I) {
+ expandRWSeqForProc(*I, RWSeq, IsRead, ProcModel);
+ }
+ }
+}
+
// Find the existing SchedWrite that models this sequence of writes.
unsigned CodeGenSchedModels::findRWForSequence(const IdxVec &Seq,
bool IsRead) {
@@ -390,13 +483,13 @@
if (Idx)
return Idx;
- CodeGenSchedRW SchedRW(Seq, genRWName(Seq, IsRead));
- if (IsRead) {
+ unsigned RWIdx = IsRead ? SchedReads.size() : SchedWrites.size();
+ CodeGenSchedRW SchedRW(RWIdx, IsRead, Seq, genRWName(Seq, IsRead));
+ if (IsRead)
SchedReads.push_back(SchedRW);
- return SchedReads.size() - 1;
- }
- SchedWrites.push_back(SchedRW);
- return SchedWrites.size() - 1;
+ else
+ SchedWrites.push_back(SchedRW);
+ return RWIdx;
}
/// Visit all the instruction definitions for this target to gather and
@@ -475,7 +568,7 @@
RWI != RWE; ++RWI) {
const CodeGenProcModel &ProcModel =
getProcModel((*RWI)->getValueAsDef("SchedModel"));
- dbgs() << "InstrRW on " << ProcModel.ModelName << " for " << InstName;
+ dbgs() << "InstRW on " << ProcModel.ModelName << " for " << InstName;
IdxVec Writes;
IdxVec Reads;
findRWs((*RWI)->getValueAsListOfDefs("OperandReadWrites"),
@@ -608,9 +701,11 @@
// determined from ItinDef or SchedRW.
SmallVector<std::pair<unsigned, SmallVector<Record *, 8> >, 4> ClassInstrs;
// Sort Instrs into sets.
- RecVec InstDefs = InstRWDef->getValueAsListOfDefs("Instrs");
- std::sort(InstDefs.begin(), InstDefs.end(), LessRecord());
- for (RecIter I = InstDefs.begin(), E = InstDefs.end(); I != E; ++I) {
+ const RecVec *InstDefs = Sets.expand(InstRWDef);
+ if (InstDefs->empty())
+ throw TGError(InstRWDef->getLoc(), "No matching instruction opcodes");
+
+ for (RecIter I = InstDefs->begin(), E = InstDefs->end(); I != E; ++I) {
unsigned SCIdx = 0;
InstClassMapTy::const_iterator Pos = InstrClassMap.find(*I);
if (Pos != InstrClassMap.end())
@@ -659,13 +754,22 @@
SC.ProcIndices.push_back(0);
// Map each Instr to this new class.
// Note that InstDefs may be a smaller list than InstRWDef's "Instrs".
+ Record *RWModelDef = InstRWDef->getValueAsDef("SchedModel");
+ SmallSet<unsigned, 4> RemappedClassIDs;
for (ArrayRef<Record*>::const_iterator
II = InstDefs.begin(), IE = InstDefs.end(); II != IE; ++II) {
unsigned OldSCIdx = InstrClassMap[*II];
- if (OldSCIdx) {
- SC.InstRWs.insert(SC.InstRWs.end(),
- SchedClasses[OldSCIdx].InstRWs.begin(),
- SchedClasses[OldSCIdx].InstRWs.end());
+ if (OldSCIdx && RemappedClassIDs.insert(OldSCIdx)) {
+ for (RecIter RI = SchedClasses[OldSCIdx].InstRWs.begin(),
+ RE = SchedClasses[OldSCIdx].InstRWs.end(); RI != RE; ++RI) {
+ if ((*RI)->getValueAsDef("SchedModel") == RWModelDef) {
+ throw TGError(InstRWDef->getLoc(), "Overlapping InstRW def " +
+ (*II)->getName() + " also matches " +
+ (*RI)->getValue("Instrs")->getValue()->getAsString());
+ }
+ assert(*RI != InstRWDef && "SchedClass has duplicate InstRW def");
+ SC.InstRWs.push_back(*RI);
+ }
}
InstrClassMap[*II] = SCIdx;
}
@@ -776,8 +880,8 @@
void CodeGenSchedModels::inferFromInstRWs(unsigned SCIdx) {
const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;
for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end(); RWI != RWE; ++RWI) {
- RecVec Instrs = (*RWI)->getValueAsListOfDefs("Instrs");
- RecIter II = Instrs.begin(), IE = Instrs.end();
+ const RecVec *InstDefs = Sets.expand(*RWI);
+ RecIter II = InstDefs->begin(), IE = InstDefs->end();
for (; II != IE; ++II) {
if (InstrClassMap[*II] == SCIdx)
break;
@@ -797,13 +901,13 @@
namespace {
// Helper for substituteVariantOperand.
struct TransVariant {
- Record *VariantDef;
- unsigned RWIdx; // Index of this variant's matched type.
+ Record *VarOrSeqDef; // Variant or sequence.
+ unsigned RWIdx; // Index of this variant or sequence's matched type.
unsigned ProcIdx; // Processor model index or zero for any.
unsigned TransVecIdx; // Index into PredTransitions::TransVec.
TransVariant(Record *def, unsigned rwi, unsigned pi, unsigned ti):
- VariantDef(def), RWIdx(rwi), ProcIdx(pi), TransVecIdx(ti) {}
+ VarOrSeqDef(def), RWIdx(rwi), ProcIdx(pi), TransVecIdx(ti) {}
};
// Associate a predicate with the SchedReadWrite that it guards.
@@ -846,6 +950,9 @@
private:
bool mutuallyExclusive(Record *PredDef, ArrayRef<PredCheck> Term);
+ void getIntersectingVariants(
+ const CodeGenSchedRW &SchedRW, unsigned TransIdx,
+ std::vector<TransVariant> &IntersectingVariants);
void pushVariant(const TransVariant &VInfo, bool IsRead);
};
} // anonymous
@@ -878,6 +985,137 @@
return false;
}
+static bool hasAliasedVariants(const CodeGenSchedRW &RW,
+ CodeGenSchedModels &SchedModels) {
+ if (RW.HasVariants)
+ return true;
+
+ for (RecIter I = RW.Aliases.begin(), E = RW.Aliases.end(); I != E; ++I) {
+ const CodeGenSchedRW &AliasRW =
+ SchedModels.getSchedRW((*I)->getValueAsDef("AliasRW"));
+ if (AliasRW.HasVariants)
+ return true;
+ if (AliasRW.IsSequence) {
+ IdxVec ExpandedRWs;
+ SchedModels.expandRWSequence(AliasRW.Index, ExpandedRWs, AliasRW.IsRead);
+ for (IdxIter SI = ExpandedRWs.begin(), SE = ExpandedRWs.end();
+ SI != SE; ++SI) {
+ if (hasAliasedVariants(SchedModels.getSchedRW(*SI, AliasRW.IsRead),
+ SchedModels)) {
+ return true;
+ }
+ }
+ }
+ }
+ return false;
+}
+
+static bool hasVariant(ArrayRef<PredTransition> Transitions,
+ CodeGenSchedModels &SchedModels) {
+ for (ArrayRef<PredTransition>::iterator
+ PTI = Transitions.begin(), PTE = Transitions.end();
+ PTI != PTE; ++PTI) {
+ for (SmallVectorImpl<SmallVector<unsigned,4> >::const_iterator
+ WSI = PTI->WriteSequences.begin(), WSE = PTI->WriteSequences.end();
+ WSI != WSE; ++WSI) {
+ for (SmallVectorImpl<unsigned>::const_iterator
+ WI = WSI->begin(), WE = WSI->end(); WI != WE; ++WI) {
+ if (hasAliasedVariants(SchedModels.getSchedWrite(*WI), SchedModels))
+ return true;
+ }
+ }
+ for (SmallVectorImpl<SmallVector<unsigned,4> >::const_iterator
+ RSI = PTI->ReadSequences.begin(), RSE = PTI->ReadSequences.end();
+ RSI != RSE; ++RSI) {
+ for (SmallVectorImpl<unsigned>::const_iterator
+ RI = RSI->begin(), RE = RSI->end(); RI != RE; ++RI) {
+ if (hasAliasedVariants(SchedModels.getSchedRead(*RI), SchedModels))
+ return true;
+ }
+ }
+ }
+ return false;
+}
+
+// Populate IntersectingVariants with any variants or aliased sequences of the
+// given SchedRW whose processor indices and predicates are not mutually
+// exclusive with the given transition,
+void PredTransitions::getIntersectingVariants(
+ const CodeGenSchedRW &SchedRW, unsigned TransIdx,
+ std::vector<TransVariant> &IntersectingVariants) {
+
+ std::vector<TransVariant> Variants;
+ if (SchedRW.HasVariants) {
+ unsigned VarProcIdx = 0;
+ if (SchedRW.TheDef->getValueInit("SchedModel")->isComplete()) {
+ Record *ModelDef = SchedRW.TheDef->getValueAsDef("SchedModel");
+ VarProcIdx = SchedModels.getProcModel(ModelDef).Index;
+ }
+ // Push each variant. Assign TransVecIdx later.
+ const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");
+ for (RecIter RI = VarDefs.begin(), RE = VarDefs.end(); RI != RE; ++RI)
+ Variants.push_back(TransVariant(*RI, SchedRW.Index, VarProcIdx, 0));
+ }
+ for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
+ AI != AE; ++AI) {
+ // If either the SchedAlias itself or the SchedReadWrite that it aliases
+ // to is defined within a processor model, constrain all variants to
+ // that processor.
+ unsigned AliasProcIdx = 0;
+ if ((*AI)->getValueInit("SchedModel")->isComplete()) {
+ Record *ModelDef = (*AI)->getValueAsDef("SchedModel");
+ AliasProcIdx = SchedModels.getProcModel(ModelDef).Index;
+ }
+ const CodeGenSchedRW &AliasRW =
+ SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
+
+ if (AliasRW.HasVariants) {
+ const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants");
+ for (RecIter RI = VarDefs.begin(), RE = VarDefs.end(); RI != RE; ++RI)
+ Variants.push_back(TransVariant(*RI, AliasRW.Index, AliasProcIdx, 0));
+ }
+ if (AliasRW.IsSequence) {
+ Variants.push_back(
+ TransVariant(AliasRW.TheDef, SchedRW.Index, AliasProcIdx, 0));
+ }
+ }
+ for (unsigned VIdx = 0, VEnd = Variants.size(); VIdx != VEnd; ++VIdx) {
+ TransVariant &Variant = Variants[VIdx];
+ // Don't expand variants if the processor models don't intersect.
+ // A zero processor index means any processor.
+ SmallVector<unsigned, 4> &ProcIndices = TransVec[TransIdx].ProcIndices;
+ if (ProcIndices[0] && Variants[VIdx].ProcIdx) {
+ unsigned Cnt = std::count(ProcIndices.begin(), ProcIndices.end(),
+ Variant.ProcIdx);
+ if (!Cnt)
+ continue;
+ if (Cnt > 1) {
+ const CodeGenProcModel &PM =
+ *(SchedModels.procModelBegin() + Variant.ProcIdx);
+ throw TGError(Variant.VarOrSeqDef->getLoc(),
+ "Multiple variants defined for processor " + PM.ModelName +
+ " Ensure only one SchedAlias exists per RW.");
+ }
+ }
+ if (Variant.VarOrSeqDef->isSubClassOf("SchedVar")) {
+ Record *PredDef = Variant.VarOrSeqDef->getValueAsDef("Predicate");
+ if (mutuallyExclusive(PredDef, TransVec[TransIdx].PredTerm))
+ continue;
+ }
+ if (IntersectingVariants.empty()) {
+ // The first variant builds on the existing transition.
+ Variant.TransVecIdx = TransIdx;
+ IntersectingVariants.push_back(Variant);
+ }
+ else {
+ // Push another copy of the current transition for more variants.
+ Variant.TransVecIdx = TransVec.size();
+ IntersectingVariants.push_back(Variant);
+ TransVec.push_back(TransVec[TransIdx]);
+ }
+ }
+}
+
// Push the Reads/Writes selected by this variant onto the PredTransition
// specified by VInfo.
void PredTransitions::
@@ -885,17 +1123,23 @@
PredTransition &Trans = TransVec[VInfo.TransVecIdx];
- Record *PredDef = VInfo.VariantDef->getValueAsDef("Predicate");
- Trans.PredTerm.push_back(PredCheck(IsRead, VInfo.RWIdx,PredDef));
-
// If this operand transition is reached through a processor-specific alias,
// then the whole transition is specific to this processor.
if (VInfo.ProcIdx != 0)
Trans.ProcIndices.assign(1, VInfo.ProcIdx);
- RecVec SelectedDefs = VInfo.VariantDef->getValueAsListOfDefs("Selected");
IdxVec SelectedRWs;
- SchedModels.findRWs(SelectedDefs, SelectedRWs, IsRead);
+ if (VInfo.VarOrSeqDef->isSubClassOf("SchedVar")) {
+ Record *PredDef = VInfo.VarOrSeqDef->getValueAsDef("Predicate");
+ Trans.PredTerm.push_back(PredCheck(IsRead, VInfo.RWIdx,PredDef));
+ RecVec SelectedDefs = VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected");
+ SchedModels.findRWs(SelectedDefs, SelectedRWs, IsRead);
+ }
+ else {
+ assert(VInfo.VarOrSeqDef->isSubClassOf("WriteSequence") &&
+ "variant must be a SchedVariant or aliased WriteSequence");
+ SelectedRWs.push_back(SchedModels.getSchedRWIdx(VInfo.VarOrSeqDef, IsRead));
+ }
const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(VInfo.RWIdx, IsRead);
@@ -939,45 +1183,6 @@
}
}
-static bool hasAliasedVariants(const CodeGenSchedRW &RW,
- CodeGenSchedModels &SchedModels) {
- if (RW.HasVariants)
- return true;
-
- for (RecIter I = RW.Aliases.begin(), E = RW.Aliases.end(); I != E; ++I) {
- if (SchedModels.getSchedRW((*I)->getValueAsDef("AliasRW")).HasVariants)
- return true;
- }
- return false;
-}
-
-static bool hasVariant(ArrayRef<PredTransition> Transitions,
- CodeGenSchedModels &SchedModels) {
- for (ArrayRef<PredTransition>::iterator
- PTI = Transitions.begin(), PTE = Transitions.end();
- PTI != PTE; ++PTI) {
- for (SmallVectorImpl<SmallVector<unsigned,4> >::const_iterator
- WSI = PTI->WriteSequences.begin(), WSE = PTI->WriteSequences.end();
- WSI != WSE; ++WSI) {
- for (SmallVectorImpl<unsigned>::const_iterator
- WI = WSI->begin(), WE = WSI->end(); WI != WE; ++WI) {
- if (hasAliasedVariants(SchedModels.getSchedWrite(*WI), SchedModels))
- return true;
- }
- }
- for (SmallVectorImpl<SmallVector<unsigned,4> >::const_iterator
- RSI = PTI->ReadSequences.begin(), RSE = PTI->ReadSequences.end();
- RSI != RSE; ++RSI) {
- for (SmallVectorImpl<unsigned>::const_iterator
- RI = RSI->begin(), RE = RSI->end(); RI != RE; ++RI) {
- if (hasAliasedVariants(SchedModels.getSchedRead(*RI), SchedModels))
- return true;
- }
- }
- }
- return false;
-}
-
// RWSeq is a sequence of all Reads or all Writes for the next read or write
// operand. StartIdx is an index into TransVec where partial results
// starts. RWSeq must be applied to all transitions between StartIdx and the end
@@ -1003,64 +1208,9 @@
continue;
}
// Distribute this partial PredTransition across intersecting variants.
- RecVec Variants;
- if (SchedRW.HasVariants)
- Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");
- IdxVec VarRWIds(Variants.size(), *RWI);
- IdxVec VarProcModels(Variants.size(), 0);
- for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
- AI != AE; ++AI) {
- unsigned AIdx;
- const CodeGenSchedRW &AliasRW =
- SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"), AIdx);
- if (!AliasRW.HasVariants)
- continue;
-
- RecVec AliasVars = AliasRW.TheDef->getValueAsListOfDefs("Variants");
- Variants.insert(Variants.end(), AliasVars.begin(), AliasVars.end());
-
- VarRWIds.resize(Variants.size(), AIdx);
-
- Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
- VarProcModels.resize(Variants.size(),
- SchedModels.getProcModel(ModelDef).Index);
- }
+ // This will push a copies of TransVec[TransIdx] on the back of TransVec.
std::vector<TransVariant> IntersectingVariants;
- for (unsigned VIdx = 0, VEnd = Variants.size(); VIdx != VEnd; ++VIdx) {
- Record *PredDef = Variants[VIdx]->getValueAsDef("Predicate");
-
- // Don't expand variants if the processor models don't intersect.
- // A zero processor index means any processor.
- SmallVector<unsigned, 4> &ProcIndices = TransVec[TransIdx].ProcIndices;
- if (ProcIndices[0] != 0 && VarProcModels[VIdx] != 0) {
- unsigned Cnt = std::count(ProcIndices.begin(), ProcIndices.end(),
- VarProcModels[VIdx]);
- if (!Cnt)
- continue;
- if (Cnt > 1) {
- const CodeGenProcModel &PM =
- *(SchedModels.procModelBegin() + VarProcModels[VIdx]);
- throw TGError(Variants[VIdx]->getLoc(), "Multiple variants defined "
- "for processor " + PM.ModelName +
- " Ensure only one SchedAlias exists per RW.");
- }
- }
- if (mutuallyExclusive(PredDef, TransVec[TransIdx].PredTerm))
- continue;
- if (IntersectingVariants.empty()) {
- // The first variant builds on the existing transition.
- IntersectingVariants.push_back(
- TransVariant(Variants[VIdx], VarRWIds[VIdx], VarProcModels[VIdx],
- TransIdx));
- }
- else {
- // Push another copy of the current transition for more variants.
- IntersectingVariants.push_back(
- TransVariant(Variants[VIdx], VarRWIds[VIdx], VarProcModels[VIdx],
- TransVec.size()));
- TransVec.push_back(TransVec[TransIdx]);
- }
- }
+ getIntersectingVariants(SchedRW, TransIdx, IntersectingVariants);
if (IntersectingVariants.empty())
throw TGError(SchedRW.TheDef->getLoc(), "No variant of this type has a "
"matching predicate on any processor ");
@@ -1299,50 +1449,57 @@
}
}
-
-// Collect resources for a set of read/write types and processor indices.
-void CodeGenSchedModels::collectRWResources(const IdxVec &Writes,
- const IdxVec &Reads,
+void CodeGenSchedModels::collectRWResources(unsigned RWIdx, bool IsRead,
const IdxVec &ProcIndices) {
-
- for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) {
- const CodeGenSchedRW &SchedRW = getSchedRW(*WI, /*IsRead=*/false);
- if (SchedRW.TheDef && SchedRW.TheDef->isSubClassOf("SchedWriteRes")) {
+ const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead);
+ if (SchedRW.TheDef) {
+ if (!IsRead && SchedRW.TheDef->isSubClassOf("SchedWriteRes")) {
for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end();
PI != PE; ++PI) {
addWriteRes(SchedRW.TheDef, *PI);
}
}
- for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
- AI != AE; ++AI) {
- const CodeGenSchedRW &AliasRW =
- getSchedRW((*AI)->getValueAsDef("AliasRW"));
- if (AliasRW.TheDef && AliasRW.TheDef->isSubClassOf("SchedWriteRes")) {
- Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
- addWriteRes(AliasRW.TheDef, getProcModel(ModelDef).Index);
- }
- }
- }
- for (IdxIter RI = Reads.begin(), RE = Reads.end(); RI != RE; ++RI) {
- const CodeGenSchedRW &SchedRW = getSchedRW(*RI, /*IsRead=*/true);
- if (SchedRW.TheDef && SchedRW.TheDef->isSubClassOf("SchedReadAdvance")) {
+ else if (IsRead && SchedRW.TheDef->isSubClassOf("SchedReadAdvance")) {
for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end();
PI != PE; ++PI) {
addReadAdvance(SchedRW.TheDef, *PI);
}
}
- for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
- AI != AE; ++AI) {
- const CodeGenSchedRW &AliasRW =
- getSchedRW((*AI)->getValueAsDef("AliasRW"));
- if (AliasRW.TheDef && AliasRW.TheDef->isSubClassOf("SchedReadAdvance")) {
- Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
- addReadAdvance(AliasRW.TheDef, getProcModel(ModelDef).Index);
- }
+ }
+ for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
+ AI != AE; ++AI) {
+ IdxVec AliasProcIndices;
+ if ((*AI)->getValueInit("SchedModel")->isComplete()) {
+ AliasProcIndices.push_back(
+ getProcModel((*AI)->getValueAsDef("SchedModel")).Index);
+ }
+ else
+ AliasProcIndices = ProcIndices;
+ const CodeGenSchedRW &AliasRW = getSchedRW((*AI)->getValueAsDef("AliasRW"));
+ assert(AliasRW.IsRead == IsRead && "cannot alias reads to writes");
+
+ IdxVec ExpandedRWs;
+ expandRWSequence(AliasRW.Index, ExpandedRWs, IsRead);
+ for (IdxIter SI = ExpandedRWs.begin(), SE = ExpandedRWs.end();
+ SI != SE; ++SI) {
+ collectRWResources(*SI, IsRead, AliasProcIndices);
}
}
}
+// Collect resources for a set of read/write types and processor indices.
+void CodeGenSchedModels::collectRWResources(const IdxVec &Writes,
+ const IdxVec &Reads,
+ const IdxVec &ProcIndices) {
+
+ for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI)
+ collectRWResources(*WI, /*IsRead=*/false, ProcIndices);
+
+ for (IdxIter RI = Reads.begin(), RE = Reads.end(); RI != RE; ++RI)
+ collectRWResources(*RI, /*IsRead=*/true, ProcIndices);
+}
+
+
// Find the processor's resource units for this kind of resource.
Record *CodeGenSchedModels::findProcResUnits(Record *ProcResKind,
const CodeGenProcModel &PM) const {
Modified: llvm/branches/R600/utils/TableGen/CodeGenSchedule.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/utils/TableGen/CodeGenSchedule.h?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/utils/TableGen/CodeGenSchedule.h (original)
+++ llvm/branches/R600/utils/TableGen/CodeGenSchedule.h Thu Oct 11 16:28:00 2012
@@ -15,6 +15,7 @@
#ifndef CODEGEN_SCHEDULE_H
#define CODEGEN_SCHEDULE_H
+#include "SetTheory.h"
#include "llvm/TableGen/Record.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/ADT/DenseMap.h"
@@ -43,8 +44,10 @@
/// IsVariadic controls whether the variants are expanded into multiple operands
/// or a sequence of writes on one operand.
struct CodeGenSchedRW {
+ unsigned Index;
std::string Name;
Record *TheDef;
+ bool IsRead;
bool IsAlias;
bool HasVariants;
bool IsVariadic;
@@ -52,10 +55,12 @@
IdxVec Sequence;
RecVec Aliases;
- CodeGenSchedRW(): TheDef(0), IsAlias(false), HasVariants(false),
+ CodeGenSchedRW(): Index(0), TheDef(0), IsAlias(false), HasVariants(false),
IsVariadic(false), IsSequence(false) {}
- CodeGenSchedRW(Record *Def): TheDef(Def), IsAlias(false), IsVariadic(false) {
+ CodeGenSchedRW(unsigned Idx, Record *Def): Index(Idx), TheDef(Def),
+ IsAlias(false), IsVariadic(false) {
Name = Def->getName();
+ IsRead = Def->isSubClassOf("SchedRead");
HasVariants = Def->isSubClassOf("SchedVariant");
if (HasVariants)
IsVariadic = Def->getValueAsBit("Variadic");
@@ -66,9 +71,10 @@
IsSequence = Def->isSubClassOf("WriteSequence");
}
- CodeGenSchedRW(const IdxVec &Seq, const std::string &Name):
- Name(Name), TheDef(0), IsAlias(false), HasVariants(false),
- IsVariadic(false), IsSequence(true), Sequence(Seq) {
+ CodeGenSchedRW(unsigned Idx, bool Read, const IdxVec &Seq,
+ const std::string &Name):
+ Index(Idx), Name(Name), TheDef(0), IsRead(Read), IsAlias(false),
+ HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) {
assert(Sequence.size() > 1 && "implied sequence needs >1 RWs");
}
@@ -203,6 +209,9 @@
RecordKeeper &Records;
const CodeGenTarget &Target;
+ // Map dag expressions to Instruction lists.
+ SetTheory Sets;
+
// List of unique processor models.
std::vector<CodeGenProcModel> ProcModels;
@@ -286,15 +295,14 @@
const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const {
return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx);
}
- CodeGenSchedRW &getSchedRW(Record *Def, unsigned &Idx) {
+ CodeGenSchedRW &getSchedRW(Record *Def) {
bool IsRead = Def->isSubClassOf("SchedRead");
- Idx = getSchedRWIdx(Def, IsRead);
+ unsigned Idx = getSchedRWIdx(Def, IsRead);
return const_cast<CodeGenSchedRW&>(
IsRead ? getSchedRead(Idx) : getSchedWrite(Idx));
}
- CodeGenSchedRW &getSchedRW(Record *Def) {
- unsigned Idx;
- return getSchedRW(Def, Idx);
+ const CodeGenSchedRW &getSchedRW(Record*Def) const {
+ return const_cast<CodeGenSchedModels&>(*this).getSchedRW(Def);
}
unsigned getSchedRWIdx(Record *Def, bool IsRead, unsigned After = 0) const;
@@ -340,6 +348,8 @@
void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const;
void expandRWSequence(unsigned RWIdx, IdxVec &RWSeq, bool IsRead) const;
+ void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
+ const CodeGenProcModel &ProcModel) const;
unsigned addSchedClass(const IdxVec &OperWrites, const IdxVec &OperReads,
const IdxVec &ProcIndices);
@@ -384,6 +394,9 @@
void collectItinProcResources(Record *ItinClassDef);
+ void collectRWResources(unsigned RWIdx, bool IsRead,
+ const IdxVec &ProcIndices);
+
void collectRWResources(const IdxVec &Writes, const IdxVec &Reads,
const IdxVec &ProcIndices);
Modified: llvm/branches/R600/utils/TableGen/FixedLenDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/utils/TableGen/FixedLenDecoderEmitter.cpp (original)
+++ llvm/branches/R600/utils/TableGen/FixedLenDecoderEmitter.cpp Thu Oct 11 16:28:00 2012
@@ -1758,7 +1758,7 @@
// FIXME: This need to be extended to handle instructions with custom
// decoder methods, and operands with (simple) MIOperandInfo's.
TypedInit *TI = dynamic_cast<TypedInit*>(NI->first);
- RecordRecTy *Type = dynamic_cast<RecordRecTy*>(TI->getType());
+ RecordRecTy *Type = dyn_cast<RecordRecTy>(TI->getType());
Record *TypeRecord = Type->getRecord();
bool isReg = false;
if (TypeRecord->isSubClassOf("RegisterOperand"))
Modified: llvm/branches/R600/utils/TableGen/IntrinsicEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/utils/TableGen/IntrinsicEmitter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/utils/TableGen/IntrinsicEmitter.cpp (original)
+++ llvm/branches/R600/utils/TableGen/IntrinsicEmitter.cpp Thu Oct 11 16:28:00 2012
@@ -547,6 +547,7 @@
OS << " AttributeWithIndex AWI[" << maxArgAttrs+1 << "];\n";
OS << " unsigned NumAttrs = 0;\n";
OS << " if (id != 0) {\n";
+ OS << " SmallVector<Attributes::AttrVal, 8> AttrVec;\n";
OS << " switch(IntrinsicsToAttributesMap[id - ";
if (TargetOnly)
OS << "Intrinsic::num_intrinsics";
@@ -564,58 +565,49 @@
unsigned numAttrs = 0;
// The argument attributes are alreadys sorted by argument index.
- for (unsigned ai = 0, ae = intrinsic.ArgumentAttributes.size(); ai != ae;) {
- unsigned argNo = intrinsic.ArgumentAttributes[ai].first;
+ unsigned ai = 0, ae = intrinsic.ArgumentAttributes.size();
+ if (ae) {
+ while (ai != ae) {
+ unsigned argNo = intrinsic.ArgumentAttributes[ai].first;
+
+ OS << " AttrVec.clear();\n";
+
+ do {
+ switch (intrinsic.ArgumentAttributes[ai].second) {
+ case CodeGenIntrinsic::NoCapture:
+ OS << " AttrVec.push_back(Attributes::NoCapture);\n";
+ break;
+ }
- OS << " AWI[" << numAttrs++ << "] = AttributeWithIndex::get("
- << argNo+1 << ", ";
+ ++ai;
+ } while (ai != ae && intrinsic.ArgumentAttributes[ai].first == argNo);
- bool moreThanOne = false;
-
- do {
- if (moreThanOne) OS << '|';
-
- switch (intrinsic.ArgumentAttributes[ai].second) {
- case CodeGenIntrinsic::NoCapture:
- OS << "Attribute::NoCapture";
- break;
- }
-
- ++ai;
- moreThanOne = true;
- } while (ai != ae && intrinsic.ArgumentAttributes[ai].first == argNo);
-
- OS << ");\n";
+ OS << " AWI[" << numAttrs++ << "] = AttributeWithIndex::get("
+ << argNo+1 << ", AttrVec);\n";
+ }
}
ModRefKind modRef = getModRefKind(intrinsic);
if (!intrinsic.canThrow || modRef || intrinsic.isNoReturn) {
- OS << " AWI[" << numAttrs++ << "] = AttributeWithIndex::get(~0, ";
- bool Emitted = false;
- if (!intrinsic.canThrow) {
- OS << "Attribute::NoUnwind";
- Emitted = true;
- }
-
- if (intrinsic.isNoReturn) {
- if (Emitted) OS << '|';
- OS << "Attribute::NoReturn";
- Emitted = true;
- }
+ OS << " AttrVec.clear();\n";
+
+ if (!intrinsic.canThrow)
+ OS << " AttrVec.push_back(Attributes::NoUnwind);\n";
+ if (intrinsic.isNoReturn)
+ OS << " AttrVec.push_back(Attributes::NoReturn);\n";
switch (modRef) {
case MRK_none: break;
case MRK_readonly:
- if (Emitted) OS << '|';
- OS << "Attribute::ReadOnly";
+ OS << " AttrVec.push_back(Attributes::ReadOnly);\n";
break;
case MRK_readnone:
- if (Emitted) OS << '|';
- OS << "Attribute::ReadNone";
+ OS << " AttrVec.push_back(Attributes::ReadNone);\n";
break;
}
- OS << ");\n";
+ OS << " AWI[" << numAttrs++ << "] = AttributeWithIndex::get(~0, "
+ << "AttrVec);\n";
}
if (numAttrs) {
Modified: llvm/branches/R600/utils/TableGen/SetTheory.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/utils/TableGen/SetTheory.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/utils/TableGen/SetTheory.cpp (original)
+++ llvm/branches/R600/utils/TableGen/SetTheory.cpp Thu Oct 11 16:28:00 2012
@@ -294,7 +294,10 @@
// This is the first time we see Set. Find a suitable expander.
try {
const std::vector<Record*> &SC = Set->getSuperClasses();
- for (unsigned i = 0, e = SC.size(); i != e; ++i)
+ for (unsigned i = 0, e = SC.size(); i != e; ++i) {
+ // Skip unnamed superclasses.
+ if (!dynamic_cast<const StringInit *>(SC[i]->getNameInit()))
+ continue;
if (Expander *Exp = Expanders.lookup(SC[i]->getName())) {
// This breaks recursive definitions.
RecVec &EltVec = Expansions[Set];
@@ -303,6 +306,7 @@
EltVec.assign(Elts.begin(), Elts.end());
return &EltVec;
}
+ }
} catch (const std::string &Error) {
throw TGError(Set->getLoc(), Error);
}
Modified: llvm/branches/R600/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/utils/TableGen/SubtargetEmitter.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/branches/R600/utils/TableGen/SubtargetEmitter.cpp Thu Oct 11 16:28:00 2012
@@ -11,6 +11,8 @@
//
//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "subtarget-emitter"
+
#include "CodeGenTarget.h"
#include "CodeGenSchedule.h"
#include "llvm/ADT/StringExtras.h"
@@ -621,10 +623,10 @@
raw_ostream &OS) {
char Sep = ProcModel.ProcResourceDefs.empty() ? ' ' : ',';
- OS << "\n// {Name, NumUnits, SuperIdx}\n";
+ OS << "\n// {Name, NumUnits, SuperIdx, IsBuffered}\n";
OS << "static const llvm::MCProcResourceDesc "
<< ProcModel.ModelName << "ProcResources" << "[] = {\n"
- << " {DBGFIELD(\"InvalidUnit\") 0, 0}" << Sep << "\n";
+ << " {DBGFIELD(\"InvalidUnit\") 0, 0, 0}" << Sep << "\n";
for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
Record *PRDef = ProcModel.ProcResourceDefs[i];
@@ -643,8 +645,8 @@
OS << " {DBGFIELD(\"" << PRDef->getName() << "\") ";
if (PRDef->getName().size() < 15)
OS.indent(15 - PRDef->getName().size());
- OS << PRDef->getValueAsInt("NumUnits") << ", " << SuperIdx
- << "}" << Sep << " // #" << i+1;
+ OS << PRDef->getValueAsInt("NumUnits") << ", " << SuperIdx << ", "
+ << PRDef->getValueAsBit("Buffered") << "}" << Sep << " // #" << i+1;
if (SuperDef)
OS << ", Super=" << SuperDef->getName();
OS << "\n";
@@ -662,15 +664,16 @@
if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes"))
return SchedWrite.TheDef;
- // Check this processor's list of aliases for SchedWrite.
Record *AliasDef = 0;
for (RecIter AI = SchedWrite.Aliases.begin(), AE = SchedWrite.Aliases.end();
AI != AE; ++AI) {
const CodeGenSchedRW &AliasRW =
SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
- Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
- if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
- continue;
+ if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
+ Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
+ if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
+ continue;
+ }
if (AliasDef)
throw TGError(AliasRW.TheDef->getLoc(), "Multiple aliases "
"defined for processor " + ProcModel.ModelName +
@@ -720,9 +723,11 @@
AI != AE; ++AI) {
const CodeGenSchedRW &AliasRW =
SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
- Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
- if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
- continue;
+ if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
+ Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
+ if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
+ continue;
+ }
if (AliasDef)
throw TGError(AliasRW.TheDef->getLoc(), "Multiple aliases "
"defined for processor " + ProcModel.ModelName +
@@ -769,6 +774,8 @@
std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back();
for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(),
SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) {
+ DEBUG(SCI->dump(&SchedModels));
+
SCTab.resize(SCTab.size() + 1);
MCSchedClassDesc &SCDesc = SCTab.back();
// SCDesc.Name is guarded by NDEBUG
@@ -817,8 +824,8 @@
}
}
else if (!SCI->InstRWs.empty()) {
- assert(SCI->Writes.empty() && SCI->Reads.empty() &&
- "InstRW class should not have its own ReadWrites");
+ // This class may have a default ReadWrite list which can be overriden by
+ // InstRW definitions.
Record *RWDef = 0;
for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end();
RWI != RWE; ++RWI) {
@@ -829,6 +836,8 @@
}
}
if (RWDef) {
+ Writes.clear();
+ Reads.clear();
SchedModels.findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),
Writes, Reads);
}
@@ -840,7 +849,8 @@
std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) {
IdxVec WriteSeq;
- SchedModels.expandRWSequence(*WI, WriteSeq, /*IsRead=*/false);
+ SchedModels.expandRWSeqForProc(*WI, WriteSeq, /*IsRead=*/false,
+ ProcModel);
// For each operand, create a latency entry.
MCWriteLatencyEntry WLEntry;
Modified: llvm/branches/R600/utils/TableGen/TableGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/utils/TableGen/TableGen.cpp?rev=165748&r1=165747&r2=165748&view=diff
==============================================================================
--- llvm/branches/R600/utils/TableGen/TableGen.cpp (original)
+++ llvm/branches/R600/utils/TableGen/TableGen.cpp Thu Oct 11 16:28:00 2012
@@ -20,7 +20,6 @@
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Main.h"
#include "llvm/TableGen/Record.h"
-#include "llvm/TableGen/TableGenAction.h"
using namespace llvm;
@@ -90,86 +89,83 @@
Class("class", cl::desc("Print Enum list for this class"),
cl::value_desc("class name"));
- class LLVMTableGenAction : public TableGenAction {
- public:
- bool operator()(raw_ostream &OS, RecordKeeper &Records) {
- switch (Action) {
- case PrintRecords:
- OS << Records; // No argument, dump all contents
- break;
- case GenEmitter:
- EmitCodeEmitter(Records, OS);
- break;
- case GenRegisterInfo:
- EmitRegisterInfo(Records, OS);
- break;
- case GenInstrInfo:
- EmitInstrInfo(Records, OS);
- break;
- case GenCallingConv:
- EmitCallingConv(Records, OS);
- break;
- case GenAsmWriter:
- EmitAsmWriter(Records, OS);
- break;
- case GenAsmMatcher:
- EmitAsmMatcher(Records, OS);
- break;
- case GenDisassembler:
- EmitDisassembler(Records, OS);
- break;
- case GenPseudoLowering:
- EmitPseudoLowering(Records, OS);
- break;
- case GenDAGISel:
- EmitDAGISel(Records, OS);
- break;
- case GenDFAPacketizer:
- EmitDFAPacketizer(Records, OS);
- break;
- case GenFastISel:
- EmitFastISel(Records, OS);
- break;
- case GenSubtarget:
- EmitSubtarget(Records, OS);
- break;
- case GenIntrinsic:
- EmitIntrinsics(Records, OS);
- break;
- case GenTgtIntrinsic:
- EmitIntrinsics(Records, OS, true);
- break;
- case GenEDInfo:
- EmitEnhancedDisassemblerInfo(Records, OS);
- break;
- case PrintEnums:
- {
- std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);
- for (unsigned i = 0, e = Recs.size(); i != e; ++i)
- OS << Recs[i]->getName() << ", ";
- OS << "\n";
- break;
- }
- case PrintSets:
- {
- SetTheory Sets;
- Sets.addFieldExpander("Set", "Elements");
- std::vector<Record*> Recs = Records.getAllDerivedDefinitions("Set");
- for (unsigned i = 0, e = Recs.size(); i != e; ++i) {
- OS << Recs[i]->getName() << " = [";
- const std::vector<Record*> *Elts = Sets.expand(Recs[i]);
- assert(Elts && "Couldn't expand Set instance");
- for (unsigned ei = 0, ee = Elts->size(); ei != ee; ++ei)
- OS << ' ' << (*Elts)[ei]->getName();
- OS << " ]\n";
- }
- break;
- }
- }
-
- return false;
+bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
+ switch (Action) {
+ case PrintRecords:
+ OS << Records; // No argument, dump all contents
+ break;
+ case GenEmitter:
+ EmitCodeEmitter(Records, OS);
+ break;
+ case GenRegisterInfo:
+ EmitRegisterInfo(Records, OS);
+ break;
+ case GenInstrInfo:
+ EmitInstrInfo(Records, OS);
+ break;
+ case GenCallingConv:
+ EmitCallingConv(Records, OS);
+ break;
+ case GenAsmWriter:
+ EmitAsmWriter(Records, OS);
+ break;
+ case GenAsmMatcher:
+ EmitAsmMatcher(Records, OS);
+ break;
+ case GenDisassembler:
+ EmitDisassembler(Records, OS);
+ break;
+ case GenPseudoLowering:
+ EmitPseudoLowering(Records, OS);
+ break;
+ case GenDAGISel:
+ EmitDAGISel(Records, OS);
+ break;
+ case GenDFAPacketizer:
+ EmitDFAPacketizer(Records, OS);
+ break;
+ case GenFastISel:
+ EmitFastISel(Records, OS);
+ break;
+ case GenSubtarget:
+ EmitSubtarget(Records, OS);
+ break;
+ case GenIntrinsic:
+ EmitIntrinsics(Records, OS);
+ break;
+ case GenTgtIntrinsic:
+ EmitIntrinsics(Records, OS, true);
+ break;
+ case GenEDInfo:
+ EmitEnhancedDisassemblerInfo(Records, OS);
+ break;
+ case PrintEnums:
+ {
+ std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);
+ for (unsigned i = 0, e = Recs.size(); i != e; ++i)
+ OS << Recs[i]->getName() << ", ";
+ OS << "\n";
+ break;
+ }
+ case PrintSets:
+ {
+ SetTheory Sets;
+ Sets.addFieldExpander("Set", "Elements");
+ std::vector<Record*> Recs = Records.getAllDerivedDefinitions("Set");
+ for (unsigned i = 0, e = Recs.size(); i != e; ++i) {
+ OS << Recs[i]->getName() << " = [";
+ const std::vector<Record*> *Elts = Sets.expand(Recs[i]);
+ assert(Elts && "Couldn't expand Set instance");
+ for (unsigned ei = 0, ee = Elts->size(); ei != ee; ++ei)
+ OS << ' ' << (*Elts)[ei]->getName();
+ OS << " ]\n";
}
- };
+ break;
+ }
+ }
+
+ return false;
+}
}
int main(int argc, char **argv) {
@@ -177,6 +173,5 @@
PrettyStackTraceProgram X(argc, argv);
cl::ParseCommandLineOptions(argc, argv);
- LLVMTableGenAction Action;
- return TableGenMain(argv[0], Action);
+ return TableGenMain(argv[0], &LLVMTableGenMain);
}
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