[llvm-branch-commits] [llvm-branch] r165012 - in /llvm/branches/R600/lib/Target/AMDGPU: MCTargetDesc/R600MCCodeEmitter.cpp R600Defines.h R600InstrInfo.h

[Tom Stellard]

Author: tstellar
Date: Tue Oct  2 09:15:43 2012
New Revision: 165012

URL: http://llvm.org/viewvc/llvm-project?rev=165012&view=rev
Log:
R600: Fix instruction encoding for r600 family GPUs

Tested-by: Michel Dänzer <michel.daenzer at amd.com>

https://bugs.freedesktop.org/show_bug.cgi?id=55217

Modified:
    llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
    llvm/branches/R600/lib/Target/AMDGPU/R600Defines.h
    llvm/branches/R600/lib/Target/AMDGPU/R600InstrInfo.h

Modified: llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp?rev=165012&r1=165011&r2=165012&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp Tue Oct  2 09:15:43 2012
@@ -216,8 +216,8 @@
 
   //older alu have different encoding for instructions with one or two src
   //parameters.
-  if (STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst &&
-      MI.getNumOperands() < 4) {
+  if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) &&
+      !(MCDesc.TSFlags & R600_InstFlag::OP3)) {
     uint64_t ISAOpCode = InstWord01 & (0x3FFULL << 39);
     InstWord01 &= ~(0x3FFULL << 39);
     InstWord01 |= ISAOpCode << 1;

Modified: llvm/branches/R600/lib/Target/AMDGPU/R600Defines.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/R600Defines.h?rev=165012&r1=165011&r2=165012&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/R600Defines.h (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/R600Defines.h Tue Oct  2 09:15:43 2012
@@ -20,3 +20,16 @@
 // Helper for finding getting the operand index for the instruction flags
 // operand.
 #define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
+
+namespace R600_InstFlag {
+	enum TIF {
+		TRANS_ONLY = (1 << 0),
+		TEX = (1 << 1),
+		REDUCTION = (1 << 2),
+		FC = (1 << 3),
+		TRIG = (1 << 4),
+		OP3 = (1 << 5),
+		VECTOR = (1 << 6)
+    //FlagOperand bits 7, 8
+	};
+}

Modified: llvm/branches/R600/lib/Target/AMDGPU/R600InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/R600InstrInfo.h?rev=165012&r1=165011&r2=165012&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/R600InstrInfo.h (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/R600InstrInfo.h Tue Oct  2 09:15:43 2012
@@ -128,17 +128,4 @@
 
 } // End llvm namespace
 
-namespace R600_InstFlag {
-	enum TIF {
-		TRANS_ONLY = (1 << 0),
-		TEX = (1 << 1),
-		REDUCTION = (1 << 2),
-		FC = (1 << 3),
-		TRIG = (1 << 4),
-		OP3 = (1 << 5),
-		VECTOR = (1 << 6)
-    //FlagOperand bits 7, 8
-	};
-}
-
 #endif // R600INSTRINFO_H_