[llvm-branch-commits] [llvm-branch] r168849 - in /llvm/branches/release_32: ./ lib/CodeGen/RegisterCoalescer.cpp test/CodeGen/ARM/coalesce-subregs.ll

[Pawel Wodnicki]

Author: pawel
Date: Wed Nov 28 20:35:17 2012
New Revision: 168849

URL: http://llvm.org/viewvc/llvm-project?rev=168849&view=rev
Log:
Merging r168837: into the 3.2 release branch.

Avoid rewriting instructions twice.

This could cause miscompilations in targets where sub-register
composition is not always idempotent (ARM).

<rdar://problem/12758887>

Modified:
    llvm/branches/release_32/   (props changed)
    llvm/branches/release_32/lib/CodeGen/RegisterCoalescer.cpp
    llvm/branches/release_32/test/CodeGen/ARM/coalesce-subregs.ll

Propchange: llvm/branches/release_32/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed Nov 28 20:35:17 2012
@@ -1,3 +1,3 @@
 /llvm/branches/Apple/Pertwee:110850,110961
 /llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,167718-167719,167731,167737,167743,167750,167784,167811,167817,167855,167860-167864,167875,167912,167942,167948,167966,168001,168035,168181,168186,168189,168196-168198,168227,168280,168291,168316,168319-168320,168346,168352,168354,168361,168364,168512,168765,168799
+/llvm/trunk:155241,167718-167719,167731,167737,167743,167750,167784,167811,167817,167855,167860-167864,167875,167912,167942,167948,167966,168001,168035,168181,168186,168189,168196-168198,168227,168280,168291,168316,168319-168320,168346,168352,168354,168361,168364,168512,168765,168799,168837

Modified: llvm/branches/release_32/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_32/lib/CodeGen/RegisterCoalescer.cpp?rev=168849&r1=168848&r2=168849&view=diff
==============================================================================
--- llvm/branches/release_32/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/branches/release_32/lib/CodeGen/RegisterCoalescer.cpp Wed Nov 28 20:35:17 2012
@@ -850,8 +850,17 @@
   // Update LiveDebugVariables.
   LDV->renameRegister(SrcReg, DstReg, SubIdx);
 
+  SmallPtrSet<MachineInstr*, 8> Visited;
   for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
        MachineInstr *UseMI = I.skipInstruction();) {
+    // Each instruction can only be rewritten once because sub-register
+    // composition is not always idempotent. When SrcReg != DstReg, rewriting
+    // the UseMI operands removes them from the SrcReg use-def chain, but when
+    // SrcReg is DstReg we could encounter UseMI twice if it has multiple
+    // operands mentioning the virtual register.
+    if (SrcReg == DstReg && !Visited.insert(UseMI))
+      continue;
+
     SmallVector<unsigned,8> Ops;
     bool Reads, Writes;
     tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);

Modified: llvm/branches/release_32/test/CodeGen/ARM/coalesce-subregs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_32/test/CodeGen/ARM/coalesce-subregs.ll?rev=168849&r1=168848&r2=168849&view=diff
==============================================================================
--- llvm/branches/release_32/test/CodeGen/ARM/coalesce-subregs.ll (original)
+++ llvm/branches/release_32/test/CodeGen/ARM/coalesce-subregs.ll Wed Nov 28 20:35:17 2012
@@ -317,3 +317,44 @@
   store <2 x i64> %result.2, <2 x i64>* %agg.result, align 128
   ret void
 }
+
+; <rdar://problem/12758887>
+; RegisterCoalescer::updateRegDefsUses() could visit an instruction more than
+; once under rare circumstances. When widening a register from QPR to DTriple
+; with the original virtual register in dsub_1_dsub_2, the double rewrite would
+; produce an invalid sub-register.
+;
+; This is because dsub_1_dsub_2 is not an idempotent sub-register index.
+; It will translate %vr:dsub_0 -> %vr:dsub_1.
+define hidden fastcc void @radar12758887() nounwind optsize ssp {
+entry:
+  br i1 undef, label %for.body, label %for.end70
+
+for.body:                                         ; preds = %for.end, %entry
+  br i1 undef, label %for.body29, label %for.end
+
+for.body29:                                       ; preds = %for.body29, %for.body
+  %0 = load <2 x double>* null, align 1
+  %splat40 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer
+  %mul41 = fmul <2 x double> undef, %splat40
+  %add42 = fadd <2 x double> undef, %mul41
+  %splat44 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 1, i32 1>
+  %mul45 = fmul <2 x double> undef, %splat44
+  %add46 = fadd <2 x double> undef, %mul45
+  br i1 undef, label %for.end, label %for.body29
+
+for.end:                                          ; preds = %for.body29, %for.body
+  %accumR2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add42, %for.body29 ]
+  %accumI2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add46, %for.body29 ]
+  %1 = shufflevector <2 x double> %accumI2.0.lcssa, <2 x double> undef, <2 x i32> <i32 1, i32 0>
+  %add58 = fadd <2 x double> undef, %1
+  %mul61 = fmul <2 x double> %add58, undef
+  %add63 = fadd <2 x double> undef, %mul61
+  %add64 = fadd <2 x double> undef, %add63
+  %add67 = fadd <2 x double> undef, %add64
+  store <2 x double> %add67, <2 x double>* undef, align 1
+  br i1 undef, label %for.end70, label %for.body
+
+for.end70:                                        ; preds = %for.end, %entry
+  ret void
+}