[llvm-branch-commits] [llvm-branch] r167837 - in /llvm/branches/R600/lib/Target/AMDGPU: SIInstrFormats.td SIInstructions.td

[Tom Stellard]

Author: tstellar
Date: Tue Nov 13 09:21:06 2012
New Revision: 167837

URL: http://llvm.org/viewvc/llvm-project?rev=167837&view=rev
Log:
SI: Only allow SGPR for the first operand of VOP3 instructions.

This is technically too strict: While a VOP3 instruction can only use one SGPR,
it can be used for any operand, even for several operands at the same. But for
now this is a simple solution which fixes the problem (e.g. causing broken
linear fog with radeonsi) at little extra cost (in the form of V_MOV_* from
SGPR to VGPR).

Patch by: Michel Dänzer

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>

Modified:
    llvm/branches/R600/lib/Target/AMDGPU/SIInstrFormats.td
    llvm/branches/R600/lib/Target/AMDGPU/SIInstructions.td

Modified: llvm/branches/R600/lib/Target/AMDGPU/SIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/SIInstrFormats.td?rev=167837&r1=167836&r2=167837&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/SIInstrFormats.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/SIInstrFormats.td Tue Nov 13 09:21:06 2012
@@ -35,10 +35,10 @@
   : VOP3b_2IN <op, opName, SReg_1, AllReg_32, VReg_32, pattern>;
 
 class VOP3_32 <bits<9> op, string opName, list<dag> pattern>
-  : VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
+  : VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
 
 class VOP3_64 <bits<9> op, string opName, list<dag> pattern>
-  : VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, AllReg_64:$src1, AllReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
+  : VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, VReg_64:$src1, VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
 
 
 class SOP1_32 <bits<8> op, string opName, list<dag> pattern>

Modified: llvm/branches/R600/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/R600/lib/Target/AMDGPU/SIInstructions.td?rev=167837&r1=167836&r2=167837&view=diff
==============================================================================
--- llvm/branches/R600/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/branches/R600/lib/Target/AMDGPU/SIInstructions.td Tue Nov 13 09:21:06 2012
@@ -1249,8 +1249,8 @@
 /**********   VOP3 Patterns    **********/
 /********** ================== **********/
 
-def : Pat <(f32 (IL_mad AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2)),
-           (V_MAD_LEGACY_F32 AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2,
+def : Pat <(f32 (IL_mad AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2)),
+           (V_MAD_LEGACY_F32 AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2,
             0, 0, 0, 0)>;
 
 } // End isSI predicate